The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL

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1 The UNIVERSITY f NORTH CAROLINA at CHAPEL HILL Cmp 541 Digital Lgic and Cmputer Design Prf. Mntek Singh Fall 2016 Lab #8: A Basic Datapath and Cntrl Unit Issued Wed 10/12/16; Due Wed 10/26/16 (11:59pm) This lab assignment cnsists f several steps, each building upn the previus. Detailed instructins are prvided. Verilg cde is prvided fr almst all f the designs, but sme prtins f the cde have been erased; in thse cases, it is yur task t cmplete and test yur cde carefully. Submissin instructins are at the end. Yu will learn the fllwing: Specifying memries in SystemVerilg Initializing memries Designing a multi-prted memry (3-prt register file) Integrating ALU, registers, memry, etc., t frm a full datapath Encding instructins Designing the cntrl unit fr a prcessr Mre practice with test fixtures Part 0: Understand hw memries are specified in SystemVerilg Memry Specificatin A typical single-prted RAM mdule is described in SystemVerilg as shwn in the file ram.sv. The number f prts in a memry is the number f distinct read/write peratins that can be perfrmed cncurrently. Thus, the number f prts typically is the number f distinct memry addresses that can be prvided t the memry. A single-prted RAM takes a single address as input, and can perfrm a read r write (determined by a write enable signal) t that address. Belw is the main part f a memry specificatin: lgic [Dbits-1:0] mem [Nlc-1:0]; clck) if(wr) mem[addr] <= din; assign dut = mem[addr]; // The actual strage where data resides // Memry write ccurs n clck tick // but nly if write is enabled // Memry read ccurs asynchrnusly Please refer t ram.sv fr the cmplete descriptin f the RAM mdule. Memry Initializatin An uninitialized memry mdule cntains junk (i.e., undefined values), althugh typically yur bard will initialize it t all zers (r nes). Yu can, hwever, specify the actual values t be stred in memry upn initializatin. This is dne using the cmmand $readmemh r $readmemb. The frmer cmmand allws yu t specify values in a file in hex frmat, while the latter uses binary frmat. 1 f 7

2 Add the fllwing line in the register file mdule right after the line where the cre f the strage is specified (i.e., right after lgic [Dbits-1 : 0] mem [Nlc-1 : 0]; ): initial $readmemh( mem_data.txt, mem, 0, Nlc-1); (Remember t put the initializatin line after the declaratin f the lgic type mem, and remember t replace mem with the actual name f yur memry strage.) The first argument t $readmemh is a string that is the name f the file t be read, line by line, during cmpilatin and synthesis, and its cntents are used t initialize memry values. The secnd argument is the name f the variable that is the memry strage. The last tw arguments specify the range f memry lcatins. In this case, they start with 0, and g up t Nlc-1, but yu are welcme t specify a subset f the range if yu d nt have data t initialize the entire memry. Create the file mem_data.txt in the prject flder (using an external editr), and add it t yur prject using Add Surce and selecting its type as Memry Initializatin File. Add values, ne per line, in hex. D nt prefix each value by h. Thus, if yur memry has 8-bit data, yur initializatin file may lk like this: 05 // Cmments are allwed A0 C1... Yu can als use the binary versin f the initializatin ($readmemb instead f $readmemh). In that case, the file will have a sequence f binary values, ne per line (n b befre thugh): 0000_0101 // Underscre can be used fr clarity 1010_ _0001 Remember that if yur datapath uses 32 bits, then the initializatin values in mem_data.txt will have t be 32-bit values as well. IMPORTANT: Yu must select the type f the file cntaining memry values as Memry Initializatin File. Otherwise, the tl may nt be able t access it prperly. 2 f 7

3 Part 1: Register File Tday yu begin t implement the MIPS subset that we will use fr this class. Yu will implement the prtin f the CPU datapath shwn in the fllwing diagram, and test it. Hwever, since we d nt yet have a surce fr instructins, and t aid in testing, we will slightly mdify this part f the datapath t prvide mre cntrllability and visibility. In particular, we will cut the feedback frm the ALU t the write prt f the register file, and instead allw Write data t be directly supplied by a test fixture. A mdified picture is shwn n the next page. First, yu will design a 3-prt register file. We call it 3-prt because three different addresses can be specified at any time: Read Address 1, Read Address 2, and Write Addr. These are required t access (up t) tw surce perands and ne destinatin perand required fr MIPS instructins. D the fllwing: Start with the ram_mdule frm the website. Mdify it t create a new mdule called register_file, which has the enhancements specified belw. A skeletn is prvided n the website (register_file.sv). three address inputs instead f just ne (e.g., ReadAddr1, ReadAddr2 and WriteAddr). tw data utputs instead f just ne (e.g., ReadData1 and ReadData2). the write enable and clck stay the same. when writing, WriteAddr is used t determine the memry lcatin t be written. when reading register 0, the value read shuld always be 0 (it des nt matter what value is written t it, r whether yu write any values int it). use parameters fr number f memry lcatins (Nlc), number f data bits (Dbits), and the name f the file which cntains initializatin values (initfile). While in the final CPU design, the three addresses will cme frm the register fields in the instructin being executed, fr nw yu will use a Verilg test fixture (in Part 2) t prvide these addresses, the data t be written, and the RegWrite signal. The test fixture des a few different reads and writes s yu can see via simulatin that yur register file is wrking. X Flags NOTE: We will NOT implement the datapath f this figure in this part. See figure n next page. 3 f 7

4 Part 2: Putting the datapath tgether Design a tp-level mdule that cntains the register file and yur ALU (frm Lab 3). Name the Verilg surce datapath.sv. This mdule must exactly crrespnd t the blck diagram belw. Nte the fllwing: T aid in testing yur design, send ReadData1, ReadData2 and ALUResult t the utput f the tp-level mdule s they can be easily bserved during simulatin. The Zer flag (Z) must als be generated as an utput frm the tp-level mdule (because branch instructins will need it). Fr nw, d nt feed the ALU result back t the register file. Instead, the data t be written int the register file shuld cme in directly frm the test fixture as an input t the tp-level mdule. The inputs t the tp-level mdule are: clck, RegWrite, the three addresses, the ALU peratin t be perfrmed (ALUFN), and the data t be written int the register file (WriteData). Use the Verilg test fixture prvided n the website t simulate and test yur design. The text fixture is self-checking, s any errrs will be flagged autmatically. Please use exactly the same names fr the tp-level inputs and utputs as used in the tester where the unit under test is instantiated. 4 f 7

5 Part 3: The Cntrl Unit In preparatin fr designing a full MIPS CPU, we will develp the Cntrl Unit in this exercise. Belw are tw diagrams f ur single-cycle MIPS CPU (frm Cmp411), first a tp-level verview, then a detailed ne. Here is the picture shwing the details: 5 f 7

6 In Part 2, we put the register file and the ALU tgether. Nw we will develp the cntrl unit. We will NOT yet develp the full MIPS datapath, nr will we be adding memries yet; thse tasks will be the next lab. The cntrl unit shuld handle ALL f the fllwing instructins: lw and sw addi, addiu, slti, sltiu, ri, lui NOTE 1: Cntrary t what yu may have learned earlier (e.g., in Cmp411), addiu actually des nt perfrm unsigned additin. In fact, it sign-extends the immediate. This instructin (alng with addu) was actually misnamed! The nly difference between addiu and addi is that addiu des nt cause an exceptin n verflw, whereas addi des. Since we are nt implementing exceptins, addiu and addi are identical fr ur purpses. NOTE 2: Als, cntrary t what yu may have learned earlier, sltiu actually sign-extends the immediate, but perfrms unsigned cmparisn, i.e. ALUFN is LTU. Als nte that ri shuld zer-extend the immediate because it is a lgical peratin! Finally, sign-extensin fr lui is a dn t-care because the 16-bit immediate is placed in the upper half f the register withut any need fr padding. R-type: add, sub, and, r, xr, nr, slt, sltu, sll, sllv, srl, sra beq, bne, j, jal and jr First study the Pwerpint slides n Single-Cycle MIPS prcessr. Next, fill ut the table belw with the values f all the cntrl signals fr the 25 basic MIPS instructins listed here. Instr werf wdsel wasel asel bsel sext wr alufn pcsel Z=1 Z=0 LW XX01 SW ADDI ADDIU SLTI SLTIU ORI LUI BEQ BNE J JAL ADD SUB AND OR XOR NOR SLT SLTU SLL SLLV SRL SRA JR MIPS instructin decding table These values will depend n the Z flag. 6 f 7

7 Using the values in this table, cmplete the Verilg descriptin f the cntrl unit in the file cntrller.sv available n the website. Use the Verilg test fixture prvided n the website t simulate and test yur design. The text fixture is selfchecking, s any errrs will be flagged autmatically. Please use exactly the same names fr the tp-level inputs and utputs as used in the tester. What t submit: Yur Verilg surce fr the register file (register_file.sv), datapath (datapath.sv), and cntrl unit (cntrller.sv) A picture f the instructin decding table frm Part 3. A screensht f the simulatin wavefrm windws f Parts 2 and 3 using the self-checking testers. Hw t submit: Please submit yur wrk by by 11:59pm, Oct 26 (Wed) as fllws: Send t: cmp541-submit-f16@cs.unc.edu Use subject line: Lab 8 Include the attachments as specified abve 7 f 7