LSN 7 Cache Memory. ECT466 Computer Architecture. Department of Engineering Technology

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1 LSN 7 Cache Memory Department of Engineering Technology

2 LSN 7 Cache Memory Join large storage device to high-speed memory Contains copies of regions of the main memory Uses locality of reference to increase efficiency in block transfers Spatial / Temporal Cache Size Cache hierarchy

3 LSN 7 Cache Organization Cache is organized by lines or blocks Cache memory stores the data from memory and part of the corresponding address as a tag

4 LSN 7 Cache Mapping Functions

5 LSN 7 Direct Mapping Each block in main memory is mapped into a single possible cache line Disadvantage in that each word in main memory is fixed to a single line in cache Cache Main Memory

6 LSN 7 Direct Mapping

7 LSN 7 Fully Associative Mapping Allows each main memory block to be loaded into any line of cache Cache must read every lines tag to see if desired data is in cache already Cache Main Memory

8 LSN 7 Fully Associative Mapping

9 LSN 7 Set Associative Mapping Cache is divided in sets, each with a grouping of lines Each block in main memory can be mapped into any line within a single set (of lines) within the cache Most common to use 2 lines per set (2-way) Cache Set Main Memory

10 LSN 7 Set Associative Mapping

11 LSN 7 Replacement Algorithms Needed for associative and set associative techniques Random Spread allocation uniformly, candidate blocks are randomly selected Least recently used To reduce a chance of throwing out information that will be needed soon, accesses to blocks are recorded FIFO Least/Most frequently used Most recently used

12 LSN 7 Cache Read Policy Read miss Read-through Reading directly from main memory to CPU No-read-through Reading from main memory to cache and then to CPU

13 LSN 7 Cache Write Policy Write hit Write-through / Write-back Write miss Write-allocate / No-write allocate Cache coherency Ensuring data between cache and main memory and any other caches is synchronized Bus watching with write through Hardware transparency Non-cacheable memory

14 LSN 7 Cache Write Policy Write miss Write-allocate Written block is brought into the cache and updated No-write allocate Directly update main memory without cache

15 LSN 7 Cache Design

16 LSN 7 Defining Cache Performance T access = t hit + (p miss * penalty miss )

17 LSN 7 Reducing Hit Time Make caches small and simple Low associativity Relatively small Pipline cache access

18 LSN 7 Reducing Miss Rate Increase block size Based on locality of reference principle

19 LSN 7 Reducing Miss Rate Increase associativity Reduce conflict misses

20 LSN 7 Reducing Miss Rate Prefetching Fetching data that you will probably need Instructions Data Fetch requested block and next sequential block Automatically fetch data into cache (spatial locality)

21 LSN 7 Reducing Miss Penalty Use more cache levels Average access time = HitTime L1 +MissRate L1 *MissPenalty L1 MissPenalty L1 = HitTime L2 +MissRate L2 *MissPenalty L2 etc.

22 LSN 7 Cache Design Line Size Based on probability of reuse on new data and already stored data Number of Caches Multilevel cache On-chip cache (L1) External cache (L2) etc. Cache structure Unified cache Split cache

23 LSN 7 Cache Design

24 LSN 7 Homework Reading Chapter , Assignment HWMRK5.pdf References Stallings, W, Computer Organization & Architecture, Prentice Hall, 7 th Ed., 2006 Animated tutorials for cache mapping techniques y/cache.html