CHAPTER 3 ASYNCHRONOUS PIPELINE CONTROLLER

Transcription

1 84 CHAPTER 3 ASYNCHRONOUS PIPELINE CONTROLLER 3.1 INTRODUCTION The introduction of several new asynchronous designs which provides high throughput and low latency is the significance of this chapter. The main target of this design is the dynamic data paths, dual rail and also the single rail. They consist of new pipelines which are latch free, and are well designed for fine grain. And each pipeline stages specifically in a single gate deep, the reduction of handshaking delay principles by employing new pipeline control structure in order to achieve high throughput in asynchronous pipeline. It is vital to differentiate between latency and throughput instead of simply giving them the name as performance. The prime point is that the asynchronous circuits consume only less power when compare to synchronous circuits. The reason is certain, since the global clock network will have to drive at a higher rate and the result is not desired though many pipelines stages are executed in instances. In asynchronous circuits the average case performance is exploited by low latency.

2 85 The intricacy of the presence of a global clocks skew is clearly known by the increased throughput present in circuits with very high density pipelining. 3.2 SYNCHRONOUS LOGIC The combinatorial logic is the basic concept of computing which takes up a setup of inputs and based on the number of inputs appropriate outputs are generated. For primitive systems which can perform a single function and which do not maintain state, this is more than enough and quite sufficient. In order to partition the circuits temporarily in a complex system, some form of timing is required. The importance of partitioning is to allow a single piece of combinatorial logic to be utilized for varied operations (i.e. various operands passed through an ALU). The synchronous circuits depend on external timing in order to find out the completion of each pipeline stage and then it registers to stop data in order to prevent overwriting the data in the next stage from the first stage. A synchronizing, periodic signal, Clock, facilitates the transition from present state to next state. Every change in logical level of its storage is ideal in a synchronous circuit Synchronous Logic Constructions In synchronous circuits shown in Figure 3.1, every flip-flop is connected to the clock net. A change takes place as the clock ticks, the resultant of one data changes into the input of the next data and these constructions is known as the pipeline. The pipelines are major part that divides the system temporarily and also spatially. A large operation that has

3 86 been already recycled temporarily by passing different data through it and also it can be divided spatially by allowing various operations to pass across varied parts of the unit at the same time. This is the general category of increasing throughput at the penalty of latency because of the added delay of the latches. Figure 3.2 depicts the data movement from one stage to the next consequence stage by transforming all data to the next stage at the rise of the clock. In order to ensure that enough time is provided for the result to be corrected a global clock is needed. Simultaneously it is accepted by the forthcoming stage and each stage holds only one data entry. Figure 3.1 Synchronous pipeline Synchronous Pipeline Properties In Figure 3.2,a serious of operations passing through a pipeline is clearly shown. The stage which has completed its logical reasoning can be represented by the shaded areas and ultimately the result is valid but it waits for the clock before it passes to the next stage. For example, if DO passes across stage 1 the result is ready ¼ th of a clock cycle before the forthcoming clock edge starts. At this time the data will not be able to move to the next stage. When DO crosses through stage 3 it needs the entire clock cycle to carry out its operations. This operation crosses the critical path when the

4 87 clock frequency was increased. At this juncture the circuit operation will fail since the result the logical operation will not be ready in time in order to be accepted into the next latch. Scarcely this operation takes place but in order to guarantee correct operation they force the clock to have a longer period. In case of worst operating conditions of the circuits this critical path delay may be noticed for the worst operating conditions of the circuits. The performance is degraded even further by this requirement. 3.3 ASYNCHRONOUS CIRCUITS Asynchronous circuits operates using event driven logic, instead of clock which provides global synchronization masking logic hazards and signaling the end of each computation step. Specifically asynchronous circuits are often decomposing into processing blocks that transfer data (tokens through asynchronous channel). This decomposition is very advantageous since it reuses asynchronous blocks and also makes the design of complex system simplified. Figure 3.2 Synchronous pipeline occupancy diagram

5 Requirements of Asynchronous Circuits The most simplified and predominant method of completion detection is to use the logic to create a completion signal instead of using matched delays. Figure 3.3 is an example of asynchronous pipeline. In this system a set of asynchronous pipeline control elements are present and it replaces the global clock. When a new data enters a stage, on the wire a request signal is automatically generated. This signal goes across the matched delay and the completion detection signal is combined with in. And after the evolution of the logic function the request signal is emitted on wire Req2, the data which has to be used in the next stage is now readily accepted. Figure 3.3 Asynchronous Pipeline The completion detection problem is solved in this approach. But still there is a problem of one piece of data overwritten in the other in the forthcoming pipeline stage. In order to provide a solution to this an acknowledge signal is being sent back to the requesting control and this acts as a signal to show that the data is accepted and that stage can be utilized by the next data. Consequently the data which is accepted is used in the next stage and as it happens simultaneously a request is emitted and again the cycle beings and continue in the next stage. And this process clearly state, this

6 89 is called handshaking. Handshaking is predominantly used in asynchronous system in order to guarantee a correct transfer of information. And another advantage is that the communication protocol is crystal clear and hence no assumptions are made on the delay of either sender or receiver Properties of Asynchronous pipeline circuits Figure 3.4 depicts an asynchronous pipeline executing the same computation asynchronous pipeline. In Figure 3.2 there is varied difference between two traces, since the optimizations discussed above are implemented. Asynchronous pipeline is faster. The reason for the improvement is at the completion of every stage, the data is determined individually, in spite of evaluating the worst case delay of the slowest stage (using a global clock). In asynchronous pipeline there are two different types of stalls and in both, a clock is used in the synchronous version. In stage2 the first is demonstrated and then DO is move to stage3. Here the new data is accepted by the stage2 hardware but D1 is yet to complete its function in stage1. This period is called starvation, since the data is not available and the hardware has to wait for the data. In this Figure 3.4 is demonstrated with dashed line across the stalling area. In the second type of stall, D2 starts its movement stage1 to stage2 but the stage is not prepared to accept new data since D1 is processed. Consequently blocking occurs since the data is readily available but it will have to wait for the availability of the hardware. In the same Figure it is shown that, the stalling with dashed line along the data shading is still present. When very few data elements are present in the pipeline, then starvation occurs and hence the throughput is low. At the same time when many data elements are present in the pipeline, then blockings occurs and causes high

7 90 latency. Hence the balanced pipeline will have low latency and high throughput. Figure 3.4 Asynchronous pipeline occupancy diagram Asynchronous circuits In Figure 3.5 shows the asynchronous circuit followed with single rail channel. Binary signals are used in asynchronous circuits but it does not have common and discrete time. Handshaking is used in these circuits between their components to carry out necessary synchronization, sequencing of operation and communication. Asynchronous circuit has got some inherent properties like robustness towards process parameters, low power consumption, high operating speed and less emission of electromagnetic noise. Figure 3.5 Asynchronous circuits

8 Asynchronous Design style: Handshake Protocols The bundled data is denoted as encoded information of its Boolean levels and acknowledge wires along with separate request are bundled with the data signals Asynchronous Channels In order to communicate data between a sender and receiver, asynchronous communication channel which is bundle of wire and protocol is required. The transmission of data is done by the encoding scheme in which one wire bit is used and the validity of the data is identified by sending an associated request line and this is called single rail encoding. As shown in Figure 3.6a. When a sender sends a protocol through a channel, it is called push channel, on the other hand the receiver which is asking for a new data is called pull channel. The directions of the request and acknowledge signals are reversed in both cases and the acknowledge signal from the sender to receiver indicate the validity of data. Hence the associated channel is known as bundled data channel as shown in Figure 3.6b. On the other hand when two wires are used for sending a data for each bit of information the coding is known as a dual rail channel as shown in Figure 3.6c, extensions to 1-of-N encoding also persists. The commonly used schemes are single rail and dual rail encoding and there exist tradeoffs between each. The data validity to be indicated by the data itself are allowed by the dual rail and 1-of-N encodings are often used in QDI designs. Contrary to this in single rail data there should be an associated request line driven by a matched delay line in order to be longer than the computation. This approach

9 92 needs careful timing analysis but one of the advantages is the reuse of synchronous single rail logic. Figure 3.6 (a) Abstract Channel Figure 3.6 (b) Bundled data channel Figure 3.6 (c) Dual rail channel Figure 3.6 Handshake protocols 3.4 FUNDAMENTAL DIFFERENCE BETWEEN ASYNCHRONOUS AND SYNCHRONOUS DESIGN The fundamental difference between asynchronous design and synchronous design is illustrated in Figure 3.7. The asynchronous design uses handshakes to synchronize local communications while the synchronous system has one global clock that must propagate to the entire chip. Switching of global clocking to local occurs, due to increased modularity, the needed

10 93 synchronization can potentially offer ease of design, more concurrency results in faster speed and due to switching activity lower energy consumption occurs only when and where needed. Figure 3.7 Comparison between synchronous and asynchronous design Paradigms 3.5 ASYNCHRONOUS PIPELINE CIRCUITS A request acknowledge handshake protocol is synchronized locally by parts of the circuit in a pipelined asynchronous system. The flow of data into and out of registers, which are usually implemented as latches and controlled by these handshakes. If the handshaking protocol prevents data from being lost or overwritten while still allowing for the flow of data between stages, the pipeline operates correctly. The basic structure of a selftimed pipeline is shown in Figure 3.8. A controller, a storage element ( data latch ) and processing logic is present in each pipeline stage. When the new data is ready, it is indicated by one stage generating a request for initialization of a handshake with its successor stage. Two actions are performed when the successor stage is empty and it accepts the data, they are:

11 94 (i) The predecessor is acknowledged for the data received and (ii) A similar handshake is initiated with its own successor stage. A variety of asynchronous pipeline controller implementations exist as many variations on this basic protocol have been developed Data Encoding in Asynchronous Pipeline Circuits Based on the data encoding employed, the pipeline styles can be categorized. To improve robustness and to reduce energy consumption data encodings are used and it is an active area of research, so this will not provide a full description of possible data encodings. Instead, some ideas on main types of data encodings used are given. Figure 3.8 A simple self-timed pipeline

12 Bundled Data Bundled data encoding which is also known as single rail in a simple and effective approach. One wire represents exactly each data bit, with an additional wire for the request bit. When a block of logic within the stage processes the data bits, some matched delay is undergone by the request bit, the outgoing request is slowed by a set of gates and so it stays coherent in time with the data. Though it does not take advantage of function blocks that have variable delays, this style is simple and practical Dual-rail encoding The request signal is essentially built in to the encoding by using two wires per data bit in Dual-rail data encoding. Though detecting this completion can add extra overhead, as soon as it is finished, this encoding scheme allows the stage to indicate completion Asynchronous Handshaking Protocols Two-phase protocols Handshaking cycles made up of two events are present in two phase protocols. To complete the handshake, the value of the request changes once and then the value of the acknowledge changes accordingly. As a result, transition based encodings are used in 2-phase protocols, an event is indicated by a transition on a line rather than the value of the line.

13 Four-phase protocols Handshaking cycles made up of four events are present in four phase protocols. The acknowledge goes high as a response of the request going high. Then the acknowledge resets to a low value and the request also goes low to a reset value. More number of events are present in this protocol than a two-phase protocol, but as level-based logic is a simpler design style than transition-based logic, the logic implementations are often simpler. 3.6 ASYNCHRONOUS TO SYNCHRONOUS CONVERSION Figure 3.9 The asynchronous-synchronous controller diagram is denoted in Figure 3.9 Asynchronous-synchronous controller The asynchronous circuit fails during the instability of guards. Due to the fall of sv- & phi 0, The transition is cut off prematurely, by careful examination & elaborate implementation of asynchronous-synchronous interface controllers- cannot be determined and it is left at an level below

14 97 logic 0 and logic 1. At the end staticizer (S) will drive the value of sv- to a proper zero or one.even though this system has a metastable state that continues for randomly long time., once the outputs x and y of the combinational logic blocks is yet to reach legal logic levels then their values are inconsistent or the time falls(the x value states that sv was false and y value states that sv was true).this clearly throws light about the failure of the system, perhaps in a disastrous and unrecoverable way. Based on the resolution time of the staticizer on sv, the probability of failure can be calculated. By the addition of clock latches on sv connection along with the combinational logic, probability of failure can be reduced. And as a result, communication latency and increased resolution time, provided with milliwatts of power consumption. Figure 3.10 Asynchronous-synchronous controller using D-Latch There are a few remarks about the staticizer. Omitting the staticizer is the most common error in synchronous design. Naturally when a design technique omits the staticizer, it clearly depicts that it would like to get an

15 98 output with many errors with varying orders of magnitude. Moreover its equivalent to use an infinite resolution time staticizer. Next to it, a normal SR latch replaces the node sv and staticizer equation. Comparitively the resolution time is increased than the weak feedback staticizer. Finally the power consumption is very much reduced, when D latch is used in place of staticizer rather than using SR latch as shown in Figure3.10 Obviously communication latency and resolution time is drastically increased. The design does not add any circuits to the asynchronoussynchronous controller, instead of that replacing SR latch to D-Latch, Achieved low power due to introducing staticizer circuit. The performance analysis of different parameters are shown in Table 3.1.The performance level of varied parameters depicts that the proposed method was comparatively best than the conventional GALS method. Table 3.1 Performance analysis of various parameters Parameters Conventional gals Proposed Observation method method Throughput 98Mbps 102 Mbps 4 % increased Delay 2.5ns 1.8ns 28 % reduced Power Consumption 0.137mWatts 31.23µWatts 77 % Saved

16 99

17 100

18 101

19 102

20 103 The performances of throughput, power consumption and delay can be clearly depicted in Figure 3.15, Figure 3.16 and Figure The proposed method performance is better than the asynchronous-synchronous controller. Figure 3.15 Performance in terms of Throughput (Mbps) Figure 3.16 Performance in terms of delay

21 mw W Figure 3.17 Performance in terms of power of consumption 3.7 RESULTS AND DISCUSSIONS The GALS based asynchronous and synchronous interface controller was investigated by (Alain Martin et al 2006). When a pipeline controller is used by a staticizer, defects were identified and the power obtained is 0.137mwatts, throughput is 98 Mbps and dynamic stack is 15.7 with CMOS 65nm general purpose 8 met al copper-strain-sio (1.00v, 2.5v), time scale 10ns and delay in 2.5ns as in shown in Figure 3.9, Figure 3.13 and Figure Using micro wind back end HDL tool, the proposed method was being tested and compared with the existing pipeline controller. By replacing the D-Latch with the staticizer in pipeline controller, a few changes take place. Reduced delay is 1.8ns, the increased throughput is 102 Mbps, dynamic stack of 13.4 and drastic reduction in power consumption is achieved as 0.031m watts. The outline of the corresponding result is denoted in figure 3.11, figure 3.12, figure 3.13, figure 3.14, states CMOS 32nm-8 met al copper-double gate (0.80v, 1.20v) and timescale 50ns.

22 SUMMARY In this chapter, the comparative study has been done on the performance analysis of asynchronous and synchronous interface controller is carried out and found the reduced in power consumption. This work can be extended and SR latch is replaced with D-latch to obtain comparatively more reduction in power consumption. Still when the complexity of the circuit is increased for both methods, reduction in power consumption is not appreciable. Limitation of this approach pipeline controller is staticizer.