ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
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1 ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1
2 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7 Binary number, Boolean algebra, CMOS, combinational logic, sequential logic, and Verilog Closed book, closed notes, closed Internet An old prelim exam will be posted early next week Review session(s) will be scheduled soon Lecture 7: 2
3 S-R Latch R S (RESET) (SET) Q Suppose the S-R latch is initialized with Q=0, write down the next state given the following input sequence S=0, R=1 à Q next = 0 S=0, R=0 à Q next = 0 S=1, R=0 à Q next = 1 Lecture 7: 3
4 S-bar-R-bar latch Built from NAND gates S-R Latch Inputs are active low rather than active high When both inputs are active, Q = QN = 1 (avoid!) S Q S R Q QN S Q R QN R 1 1 Last Q Last QN Lecture 7: 4
5 D Latch and Flip-Flop Latch: level sensitive Captures the input when enable signal asserted D Q C Flip-Flop (FF): edge sensitive Captures the input at the triggering clock edges (e.g., LàH) A single FF is also called a one-bit register D Q CLK Lecture 7: 5
6 DFF Timing Example CLK A B A B Y Z Y Z CLK Circuit diagram Waveform (assuming Y & Z are initialized with 0s) Lecture 7: 6
7 Another Example CLK A B A B Y CLK Y Circuit diagram Z Z Waveform (assuming Y & Z are initialized with 0s) Lecture 7: 7
8 T (Toggle) Flip-Flop Output toggles only if T=1 Output does not change if T=0 Useful for building counters Q: 0, 1, 0, 1, 0, 1, 0,... T CLK Q T? D CLK Q Lecture 7: 8
9 T (Toggle) Flip-Flop Output toggles only if T=1 Output does not change if T=0 Useful for building counters Q: 0, 1, 0, 1, 0, 1, 0,... T CLK Q T D CLK Q Qnext = T Q + T Q Lecture 7: 9
10 Binary Counters Counts in binary in a particular sequence Advances at every tick of the clock Many types Up Down Divideby-n n n-to-m n n+1 n+2.. m-1 m n n+1.. Lecture 7: 10
11 Up Counter Sequence Toggles every clock tick that two right bits = 11 Toggles every clock tick Toggles every clock tick that right bit = 1 Lecture 7: 11
12 CLK Free Running Binary Up Counter 1 Q0 toggles at every rising edge T T T Q Q Q Q0 Q1 Q2 Q1 toggles at the rising edge when Q0=1 Q2 toggles at the rising edge when Q0=Q1=1 Q 2 Q 1 Q Lecture 7: 12
13 Up Counter Timing Diagram CLK Q0 Q1 Q2 Count Lecture 7: 13
14 Evolution of Design Abstractions Results (design productivity)? HDL (Verilog, VHDL) Gate-level entry Transistor-level entry McKinsey S-Curve [source: Keutzer] Effort (CAD tool effort) Lecture 7: 14
15 Hardware Description Languages Hardware Description Language (HDL): a language for describing hardware Efficiently code large, complex designs Programming at a more abstract level than schematics CAD tools can automatically synthesize circuits Industry standards: Verilog: We will use it from Lab 3 SystemVerilog: Successor to Verilog, gaining popularity VHDL (Very High Speed Integrated Circuit HDL) Lecture 7: 15
16 Verilog Developed in the early 1980s by Gateway Design Automation (later bought by Cadence) Supports modeling, simulation, and synthesis We will use a (synthesizable) subset of the language features Major language features (in contrast to software programming languages) Structure and instantiation Concurrency Bit-level behavior Lecture 7: 16
17 Values Verilog signals can take 4 values 0 Logical 0, or false 1 Logical 1, or true x Unknown logical value z High impedance (Hi-Z), floating x might be a 0, 1, z, or in transition, or don t cares Sometimes useful debugging and often exploited by CAD tools during optimization Lecture 7: 17
18 Bit Vectors Multi-bit values are represented by bit vectors (i.e., grouping of 1-bit signals) Right-most bit is always least significant Example input[7:0] byte1, byte2, byte3; /* three 8-bit inputs */ Constants 4 b1001 Base format (b,d,h,o) Decimal number representing bit width Binary Constants 8 b b0xx01xx1 Decimal Constants 4 d10 32 d65536 Lecture 7: 18
19 Operators Bitwise Boolean operators ~ NOT & AND ^ Exclusive OR OR Arithmetic operators + Addition Subtraction * Multiplication / Division % Modulus << Shift left >> Shift right Lecture 7: 19
20 Verilog Program Structure System is a collection of modules Module corresponds to a single piece of hardware declarations statements module Declarations Describe names and types of inputs and outputs Describe local signals, variables, constants, etc. Statements specify what the module does Lecture 7: 20
21 Verilog Program Structure module M_2_1 (x, y, select, out); input x, y; input select; Declarations output out; wire tx, ty; AND and0 (x, ~select, tx); AND and1 (y, select, ty); OR or0 (tx, ty, out); Statements endmodule Lecture 7: 21
22 Verilog Hierarchy module A declarations statements module C declarations module D declarations statements statements A module can instantiate other modules forming a module hierarchy module F declarations statements Lecture 7: 22
23 Verilog Programming Styles Structural Shows how a module is built from other modules via instance statements Textual equivalent of drawing a schematic Behavioral Specify what a module does in high-level description Use procedural code (e.g., in always block) and continuous assignment (i.e., assign) constructs to indicate what actions to take We can mix the structural and behavioral styles in a Verilog design Lecture 7: 23
24 Structural Style module M_2_1 (x, y, sel, out); input x, y; input sel; output out; wire tx, ty; AND and0 (x, ~sel, tx); AND and1 (y, sel, ty); OR or0 (tx, ty, out); endmodule The order of the module instantiation does not matter Essentially describing the schematic textually x y sel tx ty out Lecture 7: 24
25 An assign statement represents continuously executing combinational logic module MUX2_1 (x, y, sel, out); input x, y; input sel; output out; assign out = (~sel & x) (sel & y); endmodule Behavioral Style with Continuous Assignments Multiple continuous assignments happen in parallel; the order does not matter Lecture 7: 25
26 (Behavioral Style) Combinational Logic with Always Blocks module MUX2_1 (x, y, select, out); input x, y; input select; output reg out; y, select) begin out <= (~select & x) (select & y); end An always block is reevaluated whenever a signal in its sensitivity list changes Formed by procedural assignment statements reg needed on the LHS of a procedural assignment endmodule Lecture 7: 26
27 Sequential Logic in Always Blocks reg Q; clk, D ) begin if ( clk ) Q <= D; end posedge clk ) begin Q <= D; end D Q C D latch D Q CLK DFF Sequential logic can only be modeled using always blocks Q must be declared as a reg Lecture 7: 27
28 Blocking Assignments Blocking assignments ( = ) Simulation behavior: Right-hand side (RHS) evaluated sequentially; assignment to LHS is immediate reg Y, Z; (posedge clk) begin Y = A & B; Z = ~Y; end Blocking assignments Y and Z are flip-flops in actual hardware Simulator interpretation Y next = A & B Z next = ~(A & B) Resulting circuit (post synthesis) A B Y Z Lecture 7: 28
29 Nonblocking Assignments Nonblocking assignment ( <= ) Simulation behavior: RHS evaluated in parallel (order doesn t matter); Assignment to LHS is delayed until end of always block Simulator interpretation reg Y, Z; (posedge clk) begin Y <= A & B; Z <= ~Y; end Z next = ~Y // reading the old Y Y next = A & B Nonblocking assignments A B Y and Z are flip-flops in actual hardware Resulting circuit (post synthesis) Y Z Lecture 7: 29
30 Assignments in Verilog Continuous assignments apply to combinational logic only Always blocks contain a set of procedural assignments (blocking or nonblocking) Can be used to model either combinational or sequential logic Always blocks execute concurrently with other always blocks, instance statements, and continuous assignment statements in a module Lecture 7: 30
31 H&H 3.4, 4.6 Before Next Class Next Time Finite State Machines Lecture 7: 31
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