OUTLINE Introduction Power Components Dynamic Power Optimization Conclusions

Transcription

1 OUTLINE Introduction Power Components Dynamic Power Optimization Conclusions 04/15/14 1

2 Introduction: Low Power Technology Process Hardware Architecture Software Multi VTH Low-power circuits Parallelism Power aware OS SOI Operand isolation Memory architecture Compilers Material Clock-gating Cache partitioning Memory Access Multi-gate (FinFet, ) Voltage and frequency scaling Thermal monitor Asynchronous design Power gating Body bias Stacked transistors 04/15/14 2

3 Challenges in CMOS Scaling The number of transistors on a silicon chip doubles every 12, 18, 24 months The density doubles between 2 generations every 2 or 3 years 1,4 1,2 1 0,8 0,6 0,4 0, Technology node (nm) Supply voltage (V DD ) Threshold voltage (V TH ) [ITRS 2006] Year 04/15/14 4

4 OUTLINE Introduction Power Components Dynamic Power Dynamic Power Optimization Conclusions 04/15/14 5

5 Dynamic Power V DD E=QV DD Q=C L V S C L -> C L V DD V S energy consumption per cycle P = α C L V S V DD F CLK The switching activity α is the average percentage of the nodes that actually toggles 0->1 in the total chip The switching activity includes glitches spurious activity The switching activity increases dramatically with pipelining C L is the total equivalent Capacitance C L includes both gate and wire capacitance C L is an average capacitance (Caps vary with biasing, Xtalk, ) 04/15/14 6

6 Dynamic Power Reduction Lowering switching probability (α) Gated clock, Conditional F/F Low transition coding Lowering load capacitance (C L ) Embedded memory, Gate sizing Low-k Lowering supply voltage (V S,V DD ) Most effective ( V DD2 ) and popular, but at the cost of speed degradation V TH should also be lowered for high-speed circuit operation Lowering operating frequency (f CLK ) Better algorithm, parallelism 04/15/14 7

7 Clock Gating Most effective power optimization technique Supported by most of the EDA tools Effective at register level as well as at clock network level Different approaches: Functional approach Activity-driven Observability Don t Care-Driven 04/15/14 8

8 Clock Gating Principle Goal Disable or suppress transitions from propagating to parts of the clock path (FFs, clock network and logic) under a given IDLE condition. Principle To each sequential functional unit is associated a block CG which inhibits the clock signal when the IDLE condition is true. The IDLE condition is computed by function F cg 04/15/14 9

9 Clock Gating Implementation Flip-Flop-Based Design Simplest way to implement block CG but subject to spikes. When CLK is low, spikes are filtered by the AND When CLK is high, spikes are filtered by the Latch When CLK is high, spikes are filtered by the NOR When CLK is low, spikes are filtered by the Latch 04/15/14 10

10 Flip-Flop-Based Design: Example 04/15/14 11

11 How effective is Clock-gating? Without clock gating 30.6mW With clock gating 8.5mW VDE DEU Power [mw] MIF 896Kb SRAM DSP/ HIF 90% of F/F s were clock-gated. 70% power reduction by clock-gating alone. M. Ohashi, Matsushita, ISSCC /15/14 12 MPEG4 decoder

12 Gating the Clock Network 04/15/14 13

13 FSM State Encoding: Example 1 States from RESET to S29: sequentially chained with 100% probability of transition Gray encoding is the best choice If C0 has much lower probability than C1 Gray code should not be Incremented from S30 and S31 04/15/14 14

14 Data Path: Guarded Evaluation Applicable to combin. Blocks emb. within logic If Y is idle, transparent latches are inserted to all inputs Control circuitry is added to determine the IDLE condition The IDLE condition is used to disable the latches. 04/15/14 17

15 Operand Isolation Example Design without Operand Isolation 04/15/14 18

16 Automatic Operand Isolation Stops data feeding into DesignWare arithmetic components, unless output is required AS. DATA_2 Automatically inserts isolation logic. + Add_0 SEL_0 DATA_1 0 mux_0 1 SEL_1 Automatically inserts activation logic. 0 1 mux_1 D reg_0 04/15/14 19

17 Bus Coding Advanced SoC characterized by: Long buses with high capacitance and a significant switching activity. Techniques proposed: Low swing bus Charge recycling bus Bus pipelining Bus multiplexing Bus encoding 04/15/14 20

18 Bus Coding: RTL approach Bus coding is more suitable for: Long wires (To/From) memories Memory buses Issues: Limited budget for Encoder/Decoder Chose simple implementations 04/15/14 21

19 Bus Coding Sender b(t) Receiver Sender b(t) Encoder B(t) Decoder b(t) Receiver Less switching activity b(t): Source word B(t): Code word 04/15/14 22

20 Bus Coding Different approaches: Bus-Invert Coding and its variants (four) Transition Signaling Code Offset Code T0 Code and its variants (four) Limited-Weight Code (ie. One-hot code) Codebook based code Etc 04/15/14 23

21 Bus Invert Coding The encoding depends on Hamming distance between the present bus value B(t) and the next bus value B(t+1) (B(t), INV(t)) = (b(t), 0) if H <= N/2 (b (t), 1) Otherwise N: number of bus lines, H: Hamming Distance 04/15/14 24

22 Bus Invert Coding Binary (31 Trs) BIC (19 Trs) /15/14 25

23 Bus Invert Coding Characteristics: Redundant bit consumes power Switching activity on highly capacitive buses is reduced at the expense of additional switching activity in the decoder/encoder Effective when the data to be transmitted is randomly distributed in time ( µp cache) Not efficient for address bus encoding 04/15/14 26

24 T0 Code Exploit the sequentially of the address buses Redundant line INC is added to the bus When two addresses to be transmitted are sequential, the address bus is frozen and INC is set to 1 Zero-Transition for ideally consecutive addresses 04/15/14 28

25 T0 Code: Principle Encoder (B(t), INC(t)) (B(t-1), 1) (b(t), 0) If b(t) = b(t-1) + S Otherwise Decoder b(t) (B(t-1) + S) If INC = 1 B(t) If INC = 0 S may be known by the encoder and the decoder or send on the bus 04/15/14 29

26 T0 Code: example Binary encoding: T0 encoding: 16 Transitions 4 Transitions 04/15/14 30

27 T0 Code: Implementation Encoder Decoder 04/15/14 31

28 T0 Code: Implementation 04/15/14 32

29 T0 Code Suitable for address bus encoding when sequential addresses transmitted on the bus dominate. The encoder inserts one clock cycle delay Extra area and delay Power saving achieved if the probability of sequential addresses appearing in the bus is higher than a technology dependent threshold 04/15/14 33

30 Dynamic Voltage Scaling (DVS) Application Operating System Control Signals Controller Controller Load prediction Speed setting Normalized power Variable Vdd Fixed Vdd Required speed Software V DD Hardware Processor Normalized workload 04/15/14 34 S. Lee et al, DAC, June 2000

31 Dynamic Voltage and Frequency Scaling (DVFS) Application Operating System Control Signals Load prediction Speed setting Tune Both Fclk and V DD : DVFS Workload-Based Technique: Software-Hardware cooperation Controller Controller Required speed Clock, V DD Processor Software Hardware 04/15/14 35 S. Lee et al, DAC, June 2000

32 Dynamic Voltage and Frequency Scaling (DVFS) Hurry-up-and-wait P 2 PAC = Ceff VDD f Power V 2 f Busy cycles Idle cycles P Frequency scaling (f/2) Power V 2 2 f P Voltage and frequency scaling (f/2, V DD /2) Power V 2 2 f 2 Time Deadline 04/15/14 36

33 Dynamic Voltage and Frequency Scaling (DVFS): Open-Loop System First, the desired operating frequency is set by the OS to respect the deadline Then it requests the corresponding VDD in the (VDD, f) table to the companion power supply It waits for the voltage to be stabilized and switches itself to the new frequency The supply voltage value used for each operating frequency is the worst-case value needed over all silicon process and temperature variations All these operations are generally done in an Adaptive Power Control (APC) module which can be controlled by the OS 04/15/14 37

34 Dynamic Voltage and Frequency Scaling (DVFS): Closed-Loop System τ V β DD (1) ( V V ) α DD T th Vdd at a given frequency and temperature can be derived from equation (1) VDD is not limited to discrete values: it is set automatically by measuring the system s performance margin and adjusting the supply voltage adaptively The margin between expected and actual operating conditions is monitored with the Hardware Performance Monitor (HPM), The voltage level of the processor can be reduced without sacrificing operational stability due to process and temperature variations. 04/15/14 38

35 OUTLINE Introduction Power Components Dynamic Power Optimization Conclusions 04/15/14 39

36 Conclusion: Low Power Technology Process Hardware Architecture Software Multi VTH Low-power circuits Parallelism Power aware OS FD-SOI Operand isolation Memory architecture Power Aware Compilers Material Clock-gating Cache partitioning Memory Access Multi-gate (FinFet, ) Voltage and frequency scaling Asynchronous design Power gating Body bias Stacked transistors Thermal monitor 04/15/14 40