ISSN Vol.06,Issue.09, October-2014, Pages:

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1 ISSN Vol.06,Issue.09, October-2014, Pages: VLSI Implementation of Area Efficient and Delay Reduced Soft Output Digital Signal Detector for MIMO Systems S. SOUJANYA 1, S. BHARGAV KUMAR 2, K.DEEPIKA 3 1 PG Scholar, Dept ECE, Sridevi Women s Engineering College, JNTUH, Telangana, India, soujanya.meg@gmail.com. 2 Asst Prof, Dept ECE, Sridevi Women s Engineering College, JNTUH, Telangana, India, sbhk.kumar@gmail.com. 3 Asst Prof, Dept ECE, Sridevi Women s Engineering College, JNTUH, Telangana, India, onda.deepika27@gmail.com. Abstract: Multiple-Input-Multiple-Output (MIMO) plays important role in wireless communication receiver. Like any communication receiver, the goal of a MIMO receiver is to recover original data from the transmit sequence. This paper proposed the VLSI architecture of soft-output detector which is able to deal with 4x4 MIMO configurations. Soft output detection based algorithm is used in this paper and I have compared the results of proposed work with numeric values of existing work, in terms of area (number. of slices, number of 4 input flip flops, number of slice flip-flops), delay time (ns) and memory usage. Keywords: MIMO, Soft Output Detector, VLSI, Area.. I. INTROCUTION In recent years the telecommunications industry has experiencing a tremendous growth in the area of wireless communication. This growth has been ignited the widespread popularity of mobile telephones and wireless computer networking. To meet the growing demands for better user experience, the International Telecommunication Union has released its requirements for next-generation wireless networks, where much higher spectral efficiency, higher coverage, and lower latencies are expected [7]. It has been a broad agreement that enhanced multiple-input multiple-output (MIMO) technologies play an essential role in emerging wireless standards, e.g., IEEE m (WiMAX Profile 2.0) [9] to achieve or exceed the International Mobile Telecommunications Advanced target. Cellular systems experience highly dynamic channel conditions, where the signal-to-noise ratio (SNR) and fading properties vary within huge ranges. To guarantee the quality of service for users, as in the digital communication system, error detection and error correction is important for reliable communication with a specified error rate and data throughput, it is necessary that the system is equipped with multiple MIMO technologies. The performance of MIMO technology critically depends on the employed data-detection algorithm and corresponding high-performance methods usually entail very high complexity. In particular, a straightforward implementation of hard-output maximum-likelihood (ML) 2014 IJATIR. All rights reserved. detection and soft-output a-posteriori probability (APP) detection both providing error-rate performance requires to exhaustively testing all possible transmit symbols, which results in prohibitive complexity, for moderate data rates and in deep submicron technologies. To meet the requirement of very high data rates for wireless Internet and multimedia services, multiple transmitting and multiple receiving antennas have been proposed for fourth generation wireless systems. In cellular systems, performance is limited by fading and co-channel interference from other users. This paper presents a low-complexity MIMO symbol detector The VLSI implementation is based on a novel MIMO detection algorithm called soft output detection, which achieves a good trade-off between performance and implementation cost. The flexibility allows adaptive detection to minimize area utilization, power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that MIMO detection with reasonable silicon cost. In this dissertation I focus on receiver design for high data rate communication systems utilizing physically colocated arrays. When antenna arrays are found at both the transmitter and the receiver, i.e. more than one antenna at both locations, a multiple-input multiple-output (MIMO) channel is formed. Requirement of today's communication system when being implemented with VLSI technology is efficient hardware utilization and reduce the silicon area by using low power and work with high speed. Motivation for area efficient has been derived from needs to decrease the silicon area to reduce the cost. MIMO detection algorithms are used in wireless communication and satellite communication. The various examples are cellular phone i.e. GSM, IS-54 digital cellular phone standards, modems and video and audio broadcasting. II. LITERATURE SURVEY In this survey, we will discuss about the information found by study and research that is critical and have an important value in the contribution of the whole paper. It also gives some basic knowledge or theoretical base and is used as a foundation to successfully achieve the main objectives. Most of the literatures are from the related articles, journals, books and previous works of the same

2 fields. These literatures are then compiled and use as a guidance to the work of this paper. In algorithm used in[4] increases the implementation area the reasons for it also stated in [4]the problem of visiting the nodes per each state are more which is reduced in this paper using soft output detection algorithm which compares the path metrics of each state and trace back to the minimum value path only. The computational complexity of [5] which is implemented in Xilinx vfx600 [8] is more than the proposed work in terms of device utilization which uses more than 50% of the available hardware resources. The frequency with which the FPGA [6] works is less when compared to the proposed work. [6] Is implemented by the k best algorithm. The frequency is increased by 10%in the present work. Computational complexity of such systems can be reduced by using the algorithm which is done in this paper. It is important to develop a high-speed and area efficient decoder [1] to meet the increasing data rates of wireless systems such as the IEEE [9] as wireless local area network (WLAN) and 3GPP [10] LTE advanced. The past search algorithms will consume enormous computing power and require tremendous silicon resources on the chip. To reduce the exponentially algorithmic complexity soft-output MIMO detection algorithm is used in this paper which is based on K best detection algorithm with few modifications and their VLSI architectures have been proposed in this paper. Background on data detection algorithms for MIMO systems is first reviewed in past studies. Single-input multiple-output systems (SIMO) which is given in [2] a well known that receiver diversity can combat fading for the multiple users. As the channel information capacity can be greatly increased by employing multiple transmitting antennas, we move to describe MIMO systems. I present algorithm of data detection for multiple antennas at transmitter also. Mobile wireless connectivity is a key feature of a growing range of devices from laptops and cell phones to digital homes and portable devices. Many applications, such as digital video, are driving the creation of new high data rate multiple antenna wireless algorithms with challenges in the creation of area - time-power efficient architectures. As the algorithm used in this paper satisfy all the challenges. I have used an algorithm to design the detector to overcome the limitation implement its VLSI architecture using an FSD based soft output detector algorithm which is a fixed complexity soft output detection algorithm which reduces the area and delay time. This algorithm modifies the original sphere decoding concept for MIMO systems to make it more amenable to efficient, high speed hardware implementation. In this paper, with the aid of more realistic LTE and WiMAX simulation chains and different channel models, several MIMO detection algorithms are applied to LTE [7] and WiMAX systems and with their performance quantitatively evaluated. Second, although the detection algorithm proposed by the authors in [2] has a very low detection complexity, Note those most commercial terminals are limited by cost and power consumption, S. SOUJANYA, S. BHARGAV KUMAR, K.DEEPIKA especially the power consumption of the analog part of each antenna chain. According to the LTE and WiMAX standards, 4x2 and 2x2 MIMO schemes are included as a good trade-off between performance gain and complexity (or power consumption). A. Problems and Objective Of The Proposed Work While designing VLSI circuits for very efficient implementations the designer should consider algorithmic and hardware architectures trade-offs. Rapid prototyping for such applications will imply the short designs satisfying all the design constraints, such as timing and silicon area as the existing work occupies more area comparatively than the proposed work, the main goal is to reduce the area. The wireless systems are operated under harsh and challenging channel conditions. A 4x4 MIMO system for detection is been designed, simulated, implemented and synthesized. The aim of this work is VLSI implementation soft-output detection architecture [3] for 4 4 MIMO system. The design specifications are verified using Xilinx The RTL schematic is carried for the design to be implemented on Xilinx. The main Objectives of the present work on MIMO Systems are To implement and optimize soft output detector of MIMO system on FPGA. To verify area and timing delay the soft-output detection algorithm. Compare the numeric values with the existing work. III. FORMULATION OF AREA EFFICIENT AND DELAY REDUCED SOFT-OUTPUT DETECTION FOR MIMO SYSTEMS The soft-output detector is often the critical determining factor in both the performance and the complexity of the overall system. The significant impact of soft detection on the performance and complexity of MIMO systems makes an efficient and accurate soft-output detector essential for modern communication systems. While many efficient softoutput detection algorithms with low-error-rate performance exist, gaps in the research on this important topic remain. In particular, there is a lack of soft-output detection algorithms that approach with low and fixed computational complexity. This dissertation constructs soft-output detection algorithm to fill this gap. A detector that quantizes each posteriori probability to two or more bits of precision is an example of soft-output detector, while the exact posteriori probability detector is the ultimate soft-output detector. The optimal hard-output detector, known as the maximum likelihood (JML) detector [11], finds the best symbol vector from all possible transmission vectors and has a worst-case computational complexity that grows exponentially in the number of transmitters. The soft output detector has more challenging problems, where due to the presence of errorcontrol coding and signal-to-noise ratio, it has lower error rates than those obtained via hard-output detection. The soft output detector used in WIMax receiver. Due to the practical importance, the very large scale integration (VLSI) design of soft out detector has received a lot of attention.

3 VLSI Implementation of Area Efficient and Delay Reduced Soft Output Digital Signal Detector for MIMO Systems A. VLSI Implementation of Soft Output Detector to "roll over", to use this method it is necessary to make sure Architecture the path metric accumulators contain enough bits to prevent The algorithm used in this paper is soft output detection the "best" and "worst" values from coming within 2 (n-1) of algorithm which is a combination of Viterbi algorithm and each other. The compare circuit is essentially unchanged. k-best search algorithm. Viterbi detection algorithm is used to calculate branch metrics by using which the k-best search traces back by following the k-best detection search algorithm which is a depth first search algorithm. The VLSI implementation of architecture is shown in the figure 1, the major block are path metric block, add-compare-select block and trace back block and SMC block. Fig 1: VLSI architecture for soft output detector for MIMO. B. Path Metric Calculates the path metrics of a stage by adding the branch metrics, associated with a received symbol, to the path metrics from the previous stage of the trellis. The addcompare-select unit is the heart of the soft output detection algorithm and calculates the state metrics. These state metrics accumulate the minimum cost of arriving' in a specific state. The branch metrics are added to state metrics from the previous time instant and the smaller sum is selected as the new state metric: Fig 2: Implementation of a Path Metric Unit. C. Branch Metric Unit The first unit is called branch metric unit. Here the received data symbols are compared to the ideal outputs of the encoder from the transmitter and branch metric is calculated (fig 3). Hamming distance or the Euclidean distance is used for branch metric computation. The branch metric unit takes the fuzzy bit and calculates the cost for each branch of the trellis. sm1 n = min (sm1n -1 + bm 1, sm2 n-1 + bm 3 ) (1) sm2 n = min (sm1n -1 + bm 2, sm2 n-1 + bm 4 ) (2) A path metric unit summarizes branch metrics to get metrics for paths, where K is the constraint length of the code, one of which can eventually be chosen as optimal. Every clock it makes decisions, throwing off wittingly on optimal paths (fig 2). The results of these decisions are written to the memory of a trace back unit. The core elements of a PMU are ACS (Add-Compare-Select) units. The way in which they are connected between themselves is defined by a specific code's trellis diagram. Since branch metrics are always, there must be an additional circuit preventing metric counters from overflow (it isn't shown on the image). An alternate method that eliminates the need to monitor the path metric growth is to allow the path metrics Fig 3: Branch metric unit. The branch metric uses the Euclidean distance in proposed work for the four possible paths. First we initial four different received Euclidean distance lookup table. Then each time with check the input symbol, we get the four possible distances. The BMU perform simple check and select operations on the decision bits to generate the output.

4 D. Trace Back In the TB method, the storage can be implemented as RAM and is called the path memory. Comparisons in the ACS unit and not the actual survivors are stored. After at least L branches have been processed, the trellis connections are recalled in the reverse order and the path is traced back through the trellis diagram. The TB method extracts the decoded bits, beginning from the state with the minimum PM. Beginning at this state and tracing backward in time by following the survivor path that is by comparing the branch metric of each state and choosing the minimum branch metric path in the first stage of the trace back and in the second stage selecting path not just by following the survivor path stored in memory but choosing the branch metrics again on comparison bases and placing in the 3 bit register in memory which originally contributed to the current PM, a unique path is identified. While tracing back through the trellis, the decoded output sequence, corresponding to the traced branches, is generated in the reverse order (fig 4). Fig 4: Implementation of a Trace back Unit. Trace back architecture has a limited memory bandwidth in nature, and thus limits the decoding speed. When the trellis diagram is finished, the trace-back module will search the ML path from the final state which is state0 to the beginning state which is state0. Each time, the trace-back block just left shifts one bit of the binary state number and add one bit from the survivor path metric to compute the previous state. By doing this, the most likelihood path is found. All the modules are mapped in this module. The structured programming is used in this module. The input signals are clk, start_out. The output signals are data _out and term out. The output data will be a serial 12 bit data. The trace back unit output gives the final output without any errors, since the errors are corrected during the trace back path as the output of the encoder which is encoded data of S. SOUJANYA, S. BHARGAV KUMAR, K.DEEPIKA original one is given as input for the soft output detection by using the algorithm proposed here we can detect whether the original data is detected or not i.e output of the detector should be same as the output of the encoder, if not same as the algorithm used here will produce same output. But practical implementation results approximate values. On the other hand, breadth-first search, such as the K-Best algorithm outlined in [4], traverses the tree in a level-bylevel fashion, thus lending itself to fixed throughput and complexity at the price of visiting more nodes on average as well as deviating from the ML solution. E. State Machine Control Unit The control unit receives external instructions or commands which it converts into a sequence of control signals that the control unit applies to data path to implement a sequence of register-transfer level operations. Finite-state machines can model a large number of problems, among which are electronic design automation, protocol design, parsing and other engineering applications. The final unit is the trace back process where the minimum path using branch metric values and output data is identified. The trace back is the method for the path history management. Trace back method less area to compare. The routing cost is less when compared with the other register method to recover the original data. The SMu unit store the branch metric of each state and minimum value among that branch metrics. F. Algorithm for Proposed Work Step1: Initially, the branch metric for stage0 is zero Step2: Recursively calculate the path metric values of the stages for each state to find the minimum path and at this stage decisions are used to recursively update the minimum path. Step3: Recursively find the minimum path leading to each trellis state using decision from Step2 and the minimum path is called the survivor path for that state. Step 4: Repeatedly, calculate branch metric by adding path metric of present state and previous state of their respective branches. Step 5: Repeat steps 2,3,4 and then trace back starts from the final minimum, i.e final branch metric minimum value of the final stage.(n=6) Step 6: As the trace back position reaches to the stage n-1 selecting the minimum path by comparing the branch metrics and finding minimum branch metric for each stage trace back the original value from minimum branch metric state and finally as trace back reaches stage 0 the original data is detected. Tracing back in done based on the comparison not by following the survivor path obtained in the Viterbi algorithm. The soft output detection algorithm follows Viterbi algorithm for calculating the branch metrics and while detection during trace back follows the k best algorithm the breadth first search (fig 5). By using both algorithms and implementing it in the vlsi we can verify the hardware resources used by the detector of the MIMO system. The

5 VLSI Implementation of Area Efficient and Delay Reduced Soft Output Digital Signal Detector for MIMO Systems design methodology carried to meet the objectives is as The RTL schematic of top module decoder of proposed follows. The flowchart is shown in III section, shows the work is given below in Figure6 whose inputs are design methodology followed for developing MIMO. dn,clk,ena,rst and outputs are DR0 to DR5. Simulation report of the proposed work is given below in figure7. Fig 7: Simulation Report of the Proposed Work. B. Synthesis Results 1. Synthesis report of decoder Device utilization summary: Number of Slices: 238 out of % Number of Slice Flip Flops: 304 out of % Number of 4 input LUTs: 402 out of % Number of IOs: 17 Number of bonded IOBs: 17 out of 376 4% Number of GCLKs: 1 out of 24 4% Fig 5: Flowchart of the proposed detection algorithm. IV. RESULTS A. Simulation Results 2. Timing Summary: Speed Grade: -5 Minimum period: 5.568ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 4.432ns Maximum output required time after clock: 4.063ns Maximum combinational path delay: No path found Total memory usage is kilobytes The number of IOs used in the detector only 17. Fig 6: RTL schematic of decoder. The results of existing work and proposed work were performed are seen in Xilinx. The hardware resources were estimated for the module and compared. The comparison is presented in Table 1.It can be clearly inferred from the table that there has been a significant reduction in the resource utilization in the proposed work compared to the existing work. The number of slices and 4 input LUTs used in the proposed work are only 3% when compared with the existing system indicating that a considerable percentage of slices are only used partially and number of Flip flops are 11% of that used in existing system comparatively number of IO s used 60% and number of IOB's used 9% o in proposed work as shown in the table 1.

6 S. SOUJANYA, S. BHARGAV KUMAR, K.DEEPIKA TABLE I: Comparison Results TABLE II: Timing Summary Function Minimum period Minimum input arrival time before clock Existing work MHz ns (LTE -advanced)", stanford res. inst, stanford, CA Tech Rep dec [8]Xilinx, Inc., [9]System Requirements (2010)[ONLINE] available: 07_002r4. pdf. [10] Overview of 3GPP Release10V0.0.8.(2010) Available: tion_releases/rel10_description_ zip. [11] Yang Sun, Member, IEEE, and Joseph R. Cavallaro, Senior Member, IEEE Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture ieee transactions on signal processing, vol. 60, no. 5, may Proposed work 5.568(Maximum frequency: mhz) 4.432ns Minimum time period in terms of frequency (MHz) increased by 25% and time delay is reduced by 19% as shown in table 4.2. The frequency increased in the proposed system when compared to the existing work and delay time for input to arrival also reduced. V. CONCLUSION & FUTURE SCOPE The proposed MIMO detector architecture based on the soft output detection algorithm was done successfully. The VLSI architecture has simpler code and flexible configuration when compared with the existing architecture and it saves silicon area through efficient device utilization and we compare the results in terms of area and delay, the proposed work is more efficient. Future scope of this paper is to work on frequency so that the detector works with much high speed. VI. REFERENCES [1]M.Sheeba, IIK.Monisha M.E. VLSI DESIGN, "FPGA Design of a Reduced Complexity Sphere Decoder for Wireless Applications",International Journal of Advanced Research in Computer Science & Technology (IJARCST 2014) Vol. 2, Issue 2, Ver. 3 (April - June 2014) ISSN [2]Ruchi sawal, B.B.S Kalyan,P.Vijay kumar,"fpga Implementation for Minimum Differential Feedback of MIMO-OFDM Transreceiver System",2013. [3]Christoph Studer and Helmut Bölcskei, Fellow,"Soft- Input Soft-Output Single Tree-Search Sphere Decoding", [4]Chung-An Shen, Ahmed M. Eltawil, Sudip Mondal and Khaled N. Salama "A Best-First Tree-Searching Approach for ML Decoding in MIMO System". [5] Nils Heidmann, Till Wiegand, Steffen Paul, "Architecture and FPGA-Implementation of a High Throughput K+-Best Detector"2011. [6]ShirlyEdward, alarvizhi,s2,anjana.r,aishwaryar, "Low Power Detection Architecture for MIMO Systems, International Journal of Engineering and Technology (IJET",2011). [7] T.Nakamura,"Requirements for further advancements for evolved universal terrestrial radio access (E-UTRA)