Clock and Timing ICs.

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1 Clock and Timing ICs Analog Devices offers innovative clock and timing solutions designed to improve system performance, enable new architectures, and lower development and manufacturing costs. Products feature low jitter and low phase noise for clock cleanup, synchronization, generation, delay, and distribution.

2 High Speed Clock Buffers Part Number Voltage Supply (V) Data Rate (Gbps) Slew Rate (V/ns) 20% to 80% Number of Outputs Output Logic Random Jitter (fs rms) Input Termination Resistors ADCLK to CML 75 Both inputs 16-lead LFCSP ADCLK to CML 150 Both inputs 16-lead LFCSP ADCLK to ECL 75 Both inputs 16-lead LFCSP ADCLK to ECL 150 Both inputs 16-lead LFCSP ADCLK to LVDS 100 Both inputs 16-lead LFCSP ADCLK to LVDS 200 Both inputs 16-lead LFCSP ADCLK V 100 Both inputs 16-lead LFCSP ADCLK to CML 75 Both inputs 16-lead LFCSP ADCLK to CML 150 Both inputs 16-lead LFCSP ADCLK to ECL 75 Both inputs 16-lead LFCSP ADCLK to ECL 150 Both inputs 16-lead LFCSP ADCLK to LVDS 100 Both inputs 16-lead LFCSP ADCLK to LVDS 200 Both inputs 16-lead LFCSP High Speed Comparators Part Number Voltage Supply (V) Input Range (V) Prop Delay (ns) Number per Output Logic Random Jitter (ps rms) Features: Latch Hysteresis, Shutdown ADCMP565/ADCMP566/ ADCMP567 ADCMP561/ADCMP562/ ADCMP563/ADCMP564 +5, 5.2 2, PECL and ECL 0.5 L +5, 5.2 2, PECL and ECL 1 L, H 20-lead PLCC/ 16-lead QSOP/ 20-lead QSOP ADCMP572/ADCMP to to SiGe CML and PECL 0.2 L, H 16-lead LFCSP ADCMP580/ADCMP581/ ADCMP582 ADCMP600/ADCMP601/ ADCMP602/ADCMP603 ADCMP604/ADCMP605/ ADCMP606/ADCMP607 +5, 5.2 2, SiGe CML, PECL, and ECL 0.2 L, H 16-lead LFCSP 2.5 to 5.5 Rail-to-rail 3 1 Low glitch TTL/CMOS L, H, S 2.5 to 5.5 Rail-to-rail LVDS and CML <1.5 L, H, S 5-lead SC70/6-lead SC70/ 8-lead MSOP/12-lead LFCSP 6-lead SC70/ 12-lead LFCSP ADCMP608/ADCMP to 5.5 Rail-to-rail 30 1 Low glitch TTL/CMOS L, H, S 6-lead SC70/12-lead LFCSP AD790 5, ±15 V S to V S Low glitch TTL/CMOS L, H 8-lead DIP/8-lead SOIC AD8611/AD to 5 0 to , 2 TTL/CMOS L 8-lead SOIC/14-lead TSSOP AD8561/AD , 5 5 to , 4 TTL/CMOS L 8-lead SO/16-lead SO AD96685/AD , to , 4 ECL L CMP401/CMP402 3, ±5 5 to and 65 4 TTL/CMOS Direct Digital Synthesizers for Clock/Timing Applications 16-lead SOIC/16-lead DIP/ 20-lead PLCC 16-lead SOIC/ 16-lead TSSOP Part Number Master Clock (MHz) DAC Resolution (Bits) Tuning Word Width (Bits) Nominal Supply (V) Additional Features I/O Interface AD , 5.0 Low power, low cost Parallel 48-lead TQFP AD , 5.0 Small package size Serial 16-lead TSSOP AD to 5.5 Low power, programmable waveform generator Serial 10-lead MSOP AD Low cost Parallel 48-lead TQFP AD to 5.5 Low power, low cost with integrated comparator Serial 20-lead TSSOP AD Low cost, small package size Serial 16-lead TSSOP AD , 5.0 Integrated comparator Both 28-lead SSOP AD , 5.0 Integrated comparator, clock multiplier Both 28-lead SSOP AD9852/AD Integrated comparator, clock multiplier, chirp mode, quadrature outputs Both 80-lead LQFP AD , 3.3 Low power with integrated clock multiplier Serial 48-lead TQFP/EP AD , 3.3 Integrated 2.7 GHz PLL Serial 48-lead MLF AD9951/ AD9952/ AD9953/ AD , 3.3 Low power family offering RAM, linear sweep, comparator, clock multiplier Serial 48-lead TQFP/EP AD , 3.3 Integrated clock multiplier, spur reduction Both 56-lead LFCSP AD9958/ AD , 3.3 Low power, low phase noise, multichannel (dual, quad) DDS with clock multiplier Both 56-lead LFCSP AD , 5.0 Integrated charge pump, phase frequency detector, mixer Both 100-lead TQFP/EP Programmable Delay Generator Part Number Voltage Supply (V) Max Input (MHz) Max Output (MHz) Number of Outputs Additive Jitter (ps rms) Interface ADF to wire serial 24-lead LFCSP

3 Clock Distribution for SERDES The AD9511 provides three critical clock and timing functions for a SERDES transceiver: jitter cleanup, frequency multiplication and division, and timing adjust on the clock output. The on-chip, external VCXO, and filter form a loop that locks to the incoming reference clock. The input reference clock is often noisy, containing large amounts of time jitter. Using a free software tool from Analog Devices, ADIsimCLK, the designer may optimize PLL loop bandwidth and oscillator selection to generate a clean, low jitter output at a frequency much higher than the original reference clock. The AD9511 then routes the PLL output to a flexible clock distribution section. Here, the clock frequency may be divided down to the frequency required by the SERDES transmit clock. In this example, the transmit clock must be aligned to the incoming transmit data in such a way as to minimize data uncertainty by clocking in the middle of a data period. The AD9511 includes an on-chip adjustable delay line for applications such as this, which require accurate edge placement. This AD9511 programmable delay may be set to a full scale between 1.5 ns and 10 ns. The user then has 32 programmable delay steps to optimize the clock output edge placement. Low Jitter Clock Buffers Improve ADC Performance High speed, high performance analog-to-digital converters (ADCs) are now able to sample very high frequency signals with great accuracy. To do so reliably, however, requires an extremely low jitter clock source at the ADC encode pins. This example shows how the new 1:2 ECL clock buffer, ADCLK925, may be used to deliver a low jitter encode clock to two ADCs, such as the recently introduced AD9445/AD9446. Because the ADCLK925 features random rms jitter less than 100 femtoseconds (fs), the resulting ADC signal-to-noise ratio (SNR) typically improves by 12 db over circuits with 400 fs of clock jitter. Also, having two clock buffers on a single chip ensures that the delay skew between clock A and clock B will be negligible. Note that any extra SNR realized in the ADC stage is passed on to digital processing chips, such as digital downconverters (DDCs). These digital filters are more accurate and predictable than their analog equivalents. The overall benefit to the system designer is a smaller, lower cost, and higher performing digitizer circuit. DDS-Based Clocking Application Circuit High speed, high performance digital-to-analog converters (DACs) require clean, low jitter, low phase noise clocks, especially when the DAC is generating a high intermediate frequency, IF, output. Time jitter on the DAC clock translates to noise in the output spectrum and can limit the overall performance of the transmit path. Fortunately, new low phase noise, direct digital synthesis (DDS) products are now available to build flexible converter clocks. Combined with clock distribution chips, a DDS-based clock generator offers ultrafine frequency resolution: a 32-bit DDS tuning word results in millihertz resolution on the output clock. In this example, the DDS is followed by an AD9515, which generates an LVPECL clock for the transmit DAC and an LVDS/CMOS clock for the digital upconverter, DUC.

4 Integrated Clock Generation, Cleanup, Synchronization, and Distribution Part Number Max Clock Input (GHz) Max Clock Output (MHz) Number of Outputs Wideband Random Jitter (ps rms) On-Chip Multiplier Max PLL Reference Input (MHz) Additional Features AD (LVPECL) additive 1.6 GHz 250 Two programmable delay lines, serial port for control, excellent channel isolation 64-lead LFCSP AD (LVPECL) additive 1.6 GHz 250 One programmable delay line, serial port for control, excellent channel isolation 48-lead LFCSP AD (LVPECL) additive One programmable delay line, serial port for control, two high speed clock inputs 48-lead LFCSP AD additive One programmable delay line, pin select for programming, low jitter CMOS clock distribution AD (LVPECL) additive One programmable delay line, pin select for programming AD (LVPECL) additive One programmable delay line, pin select for programming AD , (LVPECL) 10/ total 3 GHz PLL/VCO 250 Four programmable delay lines, A and B reference inputs, serial port for control, low skew outputs 64-lead LFCSP AD (CML) 160 (analog) total 2.7 GHz bit frequency resolution, 14-bit phase resolution, PLL/DDS for clock generation 48-lead LFCSP AD (HSTL) 50 (CMOS) total Digital PLL 725 A and B reference inputs, automatic reference switching, frequency holdover, programmable digital loop filter to <1 Hz 64-lead LFCSP Clock and Data Recovery/Retiming Part Number Data Rates Supported Description Power (mw) Sensitivity (mv) Jitter Generation (rms/p-p) Jitter Transfer BW (khz) Jitter Tolerance 1 (UI p-p) ADN Mbps Single rate PA and CDR /0.026 max 130 max 250 khz ADN Mbps Single rate CDR /0.026 max 130 max 250 khz ADN Mbps to 2.7 Gbps Continuous rate PA and CDR /0.037 max 670 max 1 MHz ADN Mbps to 1.25 Gbps Continuous rate PA and CDR /0.026 max 130 max 637 khz ADN Mbps to 675 Mbps Continuous rate PA and CDR /0.026 max 130 max 250 khz ADN Mbps to 1.25 Gbps Continuous rate CDR /0.026 max 130 max 250 khz ADN Mbps to 675 Mbps Continuous rate CDR /0.026 max 130 max 250 khz ADN2817 ADN Mbps to 2.7 Gbps 10 Mbps to 2.7 Gbps Single RF PLLs for Clock/Timing Applications 2 Continuous rate PA and CDR with LVDS outputs Continuous rate PA and CDR with LVDS outputs / MHz / MHz ADN Mbps to 2.7 Gbps Multirate PA and CDR /0.09 max 880 max 1 MHz 48-lead LFCSP ADN Mbps to 2.7 Gbps Continuous rate CDR with loop timed SERDES / MHz 56-lead LFCSP ADN Gbps to 11.3 Gbps Single 10G/PA and CDR / MHz 24-lead LFCSP ADN Gbps to 11.3 Gbps Single 10G/EQ and CDR / MHz 24-lead LFCSP ADN Gbps to 11.3 Gbps Dual 10G/PA, EQ, and CDR / MHz 49-ball CSPBGA Part Number PLL Type Min RF Input (MHz) Max RF Input (MHz) Normalized Phase Noise (dbc/hz) Current Typ (ma) Application Recommendations ADF4001 Int-N High speed clocking applications 16-lead TSSOP/20-lead CSP ADF4002 Int-N High speed clocking applications 16-lead TSSOP/20-lead CSP ADF4112 Int-N General-purpose operation 16-lead TSSOP/20-lead CSP ADF4106 Int-N Best integer-n PLL phase noise 16-lead TSSOP/20-lead CSP ADF4153 Frac-N General-purpose fractional-n PLL 16-lead TSSOP/20-lead CSP ADF4193 Frac-N Ultrafast settling PLL 32-lead CSP Single RF Synthesizers with VCO for Clock/Timing Applications 2 Part Number PLL Type Frequency Range (MHz) Jitter Typ (deg rms) Phase 1 khz Offset, 200 khz Channel Spacing (dbc/hz) Programmable Power Consumption (ma) Output Power (dbm) Application Recommendations ADF Int-N 350 to to to 4 ADF Int-N 65 to to to 4 High frequency clock generation/cleanup High frequency clock generation/cleanup 24-lead CSP 24-lead CSP AD809 Int-N V p-p SONET/SDH/fiber systems 24-lead CSP 1 Jitter tolerance measurements are equipment limited. 2 For a complete listing of ADI PLL products, please visit

5 Product Highlights Single, Low Cost Clocking PLL ADF4002 Pin-Programmable Clock Distribution ICs AD9513, AD9514, AD9515 Up to 400 MHz bandwidth 1.6 GHz differential clock input Programmable charge pump currents Integrated dividers (1 to 32), phase offset, delay Ultralow phase noise Selectable LVPECL/LVDS/ CMOS outputs 3-wire serial interface Analog and digital lock detect Hardware and software powerdown mode Maximum PFD frequency: 200 MHz Additive output jitter, <300 femtoseconds rms 4-level logic, pin-programmable Space-saving 20-lead CSP, 16-lead TSSOP Multichannel Direct Digital Synthesizers AD9958, AD9959 Rail-to-Rail Comparators ADCMP600 to ADCMP609 Family 2/4 synchronized 500 MSPS DDS channels, each with 10-bit DACs Industry s first LVDS comparator Independent frequency/phase/ amplitude control between all channels Excellent channel to channel isolation Frequency resolution <120 mhz Phase resolution <0.022 degrees 10-bit output amplitude scaling Space-saving 56-lead LFCSP LVDS, CML, and TTL/CMOS outputs Fully specified rail-to-rail at Vcc = 2.5 V to 5.5 V Input voltage range 0.5 V beyond the rails Power dissipation as low as 1 mw Ideal for level translation and clock/data distribution Tiny SC70 and LFCSP packages Integrated Clock Cleanup and Distribution ICs AD9510, AD9511 Continuous Rate CDR IC with Loop-Timed SERDES ADN2865 Integrated low phase noise Optimized for PON ONT Programmable dividers (1 to 32, all integers) Serial data input: 10.0 Mbps to 2.7 Gbps Phase offsets and delay adjust Exceeds ITU-T jitter requirements in all categories Additive output jitter, 225 femtoseconds rms Integrated limiting amp: 6 mv sensitivity Two 1.6 GHz differential clock inputs Patented dual-loop clock recovery architecture 8/5 selectable LVPECL/ LVDS/CMOS outputs Programmable LOS detect and slice level Low power: 1.0 W

6 Online Virtual Simulation, Evaluation, and Optimization Design Tools ADIsimPLL : PLL Synthesizer Circuit Design, Simulation, and Evaluation Tool Analog Devices ADIsimPLL development tool continues to be the industry standard in PLL circuit design and evaluation software. Since its introduction in early 2002, the patented and award-winning ADIsimPLL has been used by more than 15,000 RF design engineers worldwide. The tool is frequently utilized by design engineers in selecting and optimizing circuits for clock recovery and clock cleanup applications. With this tool, PLL circuits can be quickly designed and optimized for clocking applications, thereby reducing design iterations and time to market. For a free download of the complete software package, please visit adisimpll. ADIsimCLK: Clock Circuit Simulation and Evaluation Tool ADIsimCLK is the design tool developed specifically for Analog Devices range of ultralow jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, broadband, ATE, or other areas demanding subpicosecond jitter performance, ADIsimCLK will enable you to rapidly develop your design, evaluate, and optimize performance. Based on the highly successful ADIsimPLL tool, ADIsimCLK models the ultralow jitter clock products by using an extremely easy to use graphical user interface (GUI). The ADIsimCLK wizard enables the designer to observe detailed performance data for a simulated clock distribution design within minutes. Optimization of the clock circuit can be accomplished in this interactive environment with spreadsheet-like simplicity and interactivity. Contrary to traditional methods where designing, building, and measuring parameters take days, ADIsimCLK enables the user to change the circuit design and observe immediate performance changes. For a free download of the complete software package, please visit All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Printed in the U.S.A. BR /06 Worldwide Headquarters One Technology Way P.O. Box 9106 Norwood, MA U.S.A. Tel: ( , U.S.A. only) Fax: Europe Headquarters Wilhelm-Wagenfeld-Str Munich Germany Tel: Fax: Japan Headquarters Analog Devices, KK New Pier Takeshiba South Tower Building Kaigan, Minato-ku, Tokyo, Japan Tel: Fax: Southeast Asia Headquarters Analog Devices 22/F One Corporate Avenue 222 Hu Bin Road Shanghai, China Tel: Fax: