Two-Wire Serial EEPROM 512K (8-bit wide)

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1 Fremont Micro Devices wo-ire erial EEPOM 512 (8-bit wide) F24512 FEUE Low voltage and low power operations: F24512: V = 1.8V to 5.5V Maximum tandby current < 1µ (typically 0.02µ and 1.8V and 5.5V respectively). 128 bytes page write mode. Partial page write operation allowed. Internally organized: 65,536 8 (512). tandard 2-wire bi-directional serial interface. chmitt trigger, filtered inputs for noise protection. elf-timed write cycle (5ms maximum). 1 MHz (5V), 400 khz (1.8V, 2.5V, 2.7V) compatibility. utomatic erase before write operation. rite protect pin for hardware data protection. High reliability: typically 1,000,000 cycles endurance. 100 years data retention. Industrial temperature range (-40 o to 85 o ). tandard 8-pin DIP/OP/OP/MOP/OP Pb-free packages. DEIPION he F24512 series are 524,288 bits of serial Electrical Erasable and Programmable ead Only Memory, commonly known as EEPOM. hey are organized as 65,536 words of 8 bits (one byte) each. he devices are fabricated with proprietary advanced MO process for low power and low voltage applications. hese devices are available in standard 8-lead DIP, 8-lead OP/OP/MOP and 8-lead OP packages. standard 2-wire serial interface is used to address all read and write functions. Our extended V range (1.8V to 5.5V) devices enables wide spectrum of applications. PIN ONFIGUION Pin Name Pin Function 2, 1, 0 Device ddress Inputs D erial Data Input / Open Drain Output L erial lock Input P rite Protect N No-onnect able Fremont Micro Devices Inc. D3009E-page1

2 F24512 ll three packaging types come in Pb-free certified. F GND V P L D 8L DIP 8L OP 8L OP 8L MOP 8L OP Figure 1: Package ype OLUE MXIMUM ING Industrial operating temperature: -40 o to 85 o torage temperature: -50 o to 125 o Input voltage on any pin relative to ground: -0.3V to V + 0.3V Maximum voltage: 8V ED Protection on all pins: >2000V * tresses exceed those listed under bsolute Maximum ating may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality. Figure 2: lock Diagram D3009E-page Fremont Micro Devices Inc.

3 F24512 PIN DEIPION () EIL LO (L) he rising edge of this L input is to latch data into the EEPOM device while the falling edge of this clock is to clock data out of the EEPOM device. () DEVIE / HIP ELE DDEE (2, 1, 0) hese are the chip select input signals for the serial EEPOM devices. ypically, these signals are hardwired to either V IH or V IL. If left unconnected, they are internally recognized as V IL. () EIL D LINE (D) D data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-o with other open-drain output devices. (D) IE POE (P) he F24512 device has a P pin to protect the whole EEPOM array from programming. Programming operations are allowed if P pin is left un-connected or input to V IL. onversely all programming functions are disabled if P pin is connected to V IH or V. ead operations is not affected by the P pin s input level. MEMOY OGNIZION he F24512 devices have 512 pages respectively. ince each page has 128 bytes, random word addressing to F24512 will require 16 bits data word addresses. DEVIE OPEION () EIL LO ND D NIION he D pin is typically pulled to high by an external resistor. Data is allowed to change only when erial clock L is at V IL. ny D signal transition may interpret as either a or OP condition as described below. () ONDIION ith L V IH, a D transition from high to low is interpreted as a condition. ll valid commands must begin with a condition. () OP ONDIION ith L V IH, a D transition from low to high is interpreted as a OP condition. ll valid read or write commands end with a OP condition. he device goes into the NDY mode if it is after a read command. OP condition after page or byte write command will trigger the chip into the NDY mode after the self-timed internal programming finish (see Figure 3) Fremont Micro Devices Inc. D3009E-page3

4 F24512/ (D) NOLEDGE he 2-wire protocol transmits address and data to and from the EEPOM in 8 bit words. he EEPOM acknowledges the data or address by outputting a "0" after receiving each word. he NOLEDGE signal occurs on the 9th serial clock after each word. (E) NDY MODE he EEPOM goes into low power NDY mode after a fresh power up, after receiving a OP bit in read mode, or after completing a self-time internal programming operation. L D ondition Data Valid Data ransition OP ondition Figure 3: iming diagram for and OP conditions ondition L Data in Data out Figure 4: iming diagram for output NOLEDGE D3009E-page Fremont Micro Devices Inc.

5 F24512 DEVIE DDEING he 2-wire serial bus protocol mandates an 8 bits device address word after a bit condition to invoke a valid read or write command. he first four most significant bits of the device address must be 1010, which is common to all serial EEPOM devices. he next three bits are device address bits. hese three device address bits (5 th, 6 th and 7 th ) are to match with the external chip select/address pin states. If a match is made, the EEPOM device outputs an NOLEDGE signal after the 8 th read/write bit, otherwise the chip will go into NDY mode. However, matching may not be needed for some or all device address bits (5 th, 6 th and 7 th ) as noted below. he last or 8th bit is a read/write command bit. If the 8 th bit is at VIH then the chip goes into read mode. If a 0 is detected, the device enters programming mode. IE OPEION () YE IE write operation requires two 8-bit data word address following the device address word and NOLEDGE signal. Upon receipt of this address, the EEPOM will respond with a 0 and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPOM will again output a 0. he addressing device, such as a microcontroller, must terminate the write sequence with a OP condition. t this time the EEPOM enters into an internally-timed write cycle state. ll inputs are disabled during this write cycle and the EEPOM will not respond until the writing is completed (figure 5). () PGE IE he 512 EEPOM are capable of 128-byte page write. page write is initiated the same way as a byte write, but the microcontroller does not send a OP condition after the first data word is clocked in. he microcontroller can transmit up to 127 more data words after the EEPOM acknowledges receipt of the first data word. he EEPOM will respond with a 0 after each data word is received. he microcontroller must terminate the page write sequence with a OP condition (see Figure 6). he lower 7 bits of the data word address are internally incremented following the receipt of each data word. he higher data word address bits are not incremented, retaining the memory page row location. If more than 128 data words are transmitted to the EEPOM, the data word address will roll over and the previous data will be overwritten. () NOLEDGE POLLING NOLEDGE polling may be used to poll the programming status during a self-timed internal programming. y issuing a valid read or write address command, the EEPOM will not acknowledge at the 9 th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the NDY mode, the device will return a valid NOLEDGE signal at the 9 th clock cycle Fremont Micro Devices Inc. D3009E-page5

6 F24512/ ED OPEION he read command is similar to the write command except the 8 th read/write bit in address word is set to 1. he three read operation modes are described as follows: () UEN DDE ED he EEPOM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. o initiate a current address read operation, the micro-controller issues a bit and a valid device address word with the read/write bit (8 th ) set to 1. he EEPOM will response with an NOLEDGE signal on the 9 th serial clock cycle. n 8- bit data word will then be serially clocked out. he internal address word counter will then automatically increase by one. For current address read the micro-controller will not issue an NOLEDGE signal on the 18 th clock cycle. he micro-controller issues a valid OP bit after the 18 th clock cycle to terminate the read operation. he device then returns to NDY mode (see Figure 7). () EQUENIL ED he sequential read is very similar to current address read. he micro-controller issues a bit and a valid device address word with read/write bit (8 th ) set to 1. he EEPOM will response with an NOLEDGE signal on the 9 th serial clock cycle. n 8-bit data word will then be serially clocked out. Meanwhile the internally address word counter will then automatically increase by one. Unlike current address read, the micro-controller sends an NOLEDGE signal on the 18th clock cycle signaling the EEPOM device that it wants another byte of data. Upon receiving the NOLEDGE signal, the EEPOM will serially clocked out an 8-bit data word based on the incremented internal address counter. If the micro-controller needs another data, it sends out an NOLEDGE signal on the 27 th clock cycle. nother 8-bit data word will then be serially clocked out. his sequential read continues as long as the micro-controller sends an NOLEDGE signal after receiving a new data word. hen the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. imilar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a OP bit afterwards instead (figure 8). () NDOM ED andom read is a two-steps process. he first step is to initialize the internal address counter with a target read address using a dummy write instruction. he second step is a current address read. o initialize the internal address counter with a target read address, the micro-controller issues a bit first, follows by a valid device address with the read/write bit (8 th ) set to 0. he EEPOM will then acknowledge. he micro-controller will then send two address words. gain the EEPOM will acknowledge. Instead of sending a valid written data to the EEPOM, the micro-controller performs a current address read instruction to read the data. Note that once a bit is issued, the EEPOM will reset the internal programming process and continue to execute the new instruction - which is to read the current address (figure 9). D3009E-page Fremont Micro Devices Inc.

7 F Fremont Micro Devices Inc. D3009E-page7 D LINE M DEVIE DDE L / I E FI OD DDE M L EOND OD DDE O P D Figure 5: yte rite D LINE M DEVIE DDE L / I E FI OD DDE(N) M L EOND OD DDE(N) O P D(N) D(N+X)... Figure 6: Page rite D LINE M DEVIE DDE L / E D N O O P D Figure 7: urrent ddress ead D LINE DEVIE DDE / E D N O O P D (N) D (N+1) D (N+2) D (N+3) Figure 8: equential ead

8 F24512/ DEVIE DDE I E FI OD DDE(N) EOND OD DDE(N) DEVIE DDE E D D (N) O P D LINE M L Figure 9: andom ead / M L M L / N O L t F LO t t HIGH t LO t t U, t HD. t HD.D t U.D t U.O D IN t tdh tuf D OU Figure 10: L and D us iming D3009E-page Fremont Micro Devices Inc.

9 F24512 HEII ymbol Parameter 1.8V V Unit Min Max Min Max f L lock frequency, L khz t LO lock pulse width low µs t HIGH lock pulse width high µs t I Noise suppression time (1) ns t lock low to data out valid µs t UF ime the bus must be free before a new transmission µs can start (1) t HD. hold time µs t U. set-up time µs t HD.D Data in hold time 0 0 µs t U.D Data in set-up time ns t Input rise time (1) µs t F Input fall time (1) ns t U.O OP set-up time µs t DH Date out hold time ns t rite cycle time 5 5 ms Endurance (1) 25 o, Page Mode, 3.3V 1,000,000 rite ycles Notes: 1. his Parameter is expected by characterization but are not fully screened by test. 2. Measurement conditions: L (onnects to Vcc): 1.3Ω Input Pulse Voltages: 0.3Vcc to 0.7Vcc Input and output timing reference Voltages: 0.5Vcc 2009 Fremont Micro Devices Inc. D3009E-page9

10 F24512/ D HEII ymbol Parameter est onditions Min ypical Max Units V 1 24 supply V V I upply read current 5.0V L = 100 khz m I upply write current 5.0V L = 100 khz m I 1 upply current 1.8V, V IN = V or V µ I 2 upply current 2.5V, V IN = V or V 1.0 µ I 3 upply current 5.0V, V IN = V or V µ I IL Input leakage current V IN = V or V 3.0 µ I LO Output leakage current V IN = V or V 3.0 µ V IL Input low level -0.6 V 0.3 V V IH Input high level V 0.7 V +0.5 V V OL2 Output low level 3.0V, I OL = 2.1 m 0.4 V V OL1 Output low level 1.8V, I OL = 0.15 m 0.4 V ODE ODE: F24XX XXX - X emperature ange U: -40 to 85? Package D: DIP : OP : OP M: MOP : OP Packaging : ube : ape and eel Option G: Green Package oh ompliant : oh ompliant D3009E-page Fremont Micro Devices Inc.

11 F24512 ODE INFOMION Order code Vcc emperature ange Package Option Packaging F24512-UD- oh ube DIP8 F24512-UDG- Green Package ube F24512-U- oh ube F24512-U- oh / OP8 F24512-UG- Green Package ube F24512-UG- Green Package / F24512-U- oh ube F24512-U- oh / OP8 F24512-UG- Green Package ube F24512-UG V Green Package / F24512-UM- oh ube F24512-UM- oh / MOP8 F24512-UMG- Green Package ube F24512-UMG- Green Package / F24512-U- oh ube F24512-U- oh / OP8 F24512-UG- Green Package ube F24512-UG- Green Package / 2009 Fremont Micro Devices Inc. D3009E-page11

12 F24512/ DIP8 PGE OULINE DIMENION ymbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max () 0.060() D E E e () 0.100() L E D3009E-page Fremont Micro Devices Inc.

13 F24512 OP8 PGE OULINE DIMENION (150mil) ymbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max b c D E E e () 0.050() L θ Fremont Micro Devices Inc. D3009E-page13

14 F24512/ OP8 PGE OULINE DIMENION (208 mil) ymbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max b c D E E e () 0.050() L θ D3009E-page Fremont Micro Devices Inc.

15 F24512 OP8 PGE OULINE DIMENION ymbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max D E b c E e 0.65 () () L H 0.25 (YP) 0.01 (YP) θ Fremont Micro Devices Inc. D3009E-page15

16 F24512/ MOP8 PGE OULINE DIMENION ymbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max b c D e 0.65 () () E E L D3009E-page Fremont Micro Devices Inc.

17 F24512 PPENDIX :EVIION HIOY Version : Original data sheet for F24512/. * Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (VI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices, Incorporated (VI). pecifications mentioned in this publication are subject to change without notice. his publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (VI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (VI). he FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (VI). ll other names are the property of their respective owners Fremont Micro Devices Inc. D3009E-page17

Two-Wire Serial EEPROM 32K, 64K (8-bit wide)

Two-Wire Serial EEPROM 32K, 64K (8-bit wide) wo-wire erial EEPOM 32, 64 (8-bit wide) FEUE Low voltage and low power operations: F2432/64: V = 1.8V to 5.5V Maximum tandby current < 1µ (typically 0.02µ and 0.06µ @ 1.8V and 5.5V respectively). 32 bytes