VCC TEST/WP SCL SDA. Figure 1. Table 1. Function

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1 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 he -24X is a series of 2-wired, low power 1/2/4-bit EEPOMs with a wide operating range. hey are organized as 128-word 8-bit, 256-word 8-bit, and 512-word 8-bit, respectively. Each is capable of page write, and sequential read. he time for byte write and page write is the same, i. e., 1 msec. (max.) during operation at 5 V ± 1%. Features Low power consumption tandby: µ Max. (V =5.5 V) Operating:.4 m Max. (V =5.5 V).3 m Max. (V =3.3 V) Wide operating voltage range Write: 2.5 to 5.5 V ead: 1.8 to 5.5 V Page write 8 bytes (-241, -242) 16 bytes (-244) Package 8-pin DIP (PG drawing code : DP8-,DP8-) 8-pin OP (PG drawing code : FJ8-D,FJ8-E) Endurance: Data retention: Write protection: -241: -242: -244: 1 6 cycles/word 1 years -242, kbits 2 kbits 4 kbits Pin ssignment 8-pin DIP op view 8-pin OP op view Pin Functions GND DPx-uu -242DPx-uu -244DPx-uu V E/WP L D Figure 1 able GND V E/WP L D -241FJ-zz-uuw -242FJ-zz-uuw -244FJ-zz-uuw * Lower-case letters x, uu, zz and w differ depending on the packing form. ee Ordering Information and Dimensions. Name Pin Number DIP OP Function 1 1 ddress input (no connection in the -244*) ddress input ddress input GND 4 4 Ground D 5 5 erial data input/output L 6 6 erial clock input E/WP 7 7 E pin (-241): onnected to GND. WP (Write Protection) pin (-242, -244): * onnected to Vcc: Protection valid * onnected to GND: Protection invalid V 8 8 Power supply * When in use, connect to GND or Vcc. eiko Instruments Inc. 1

2 MO 2-WIE EIL EEPOM -241/2/4 ev. 2.2_3 Block Diagram L D tart/top Detector E/WP* V GND erial lock ontroller High-Voltage Generator LOD 2 1 Device ddress omparator / W OMP LOD IN ddress ounter X Decoder Data egister EEPOM Y Decoder elector D IN Data Output Output ontroller D OU * -242 or -244 Figure 2 bsolute Maximum atings able 2 Parameter ymbol atings Unit Power supply voltage V -.3 to +7. V Input voltage V IN -.3 to V +.3 V Output voltage V OU -.3 to V V torage temperature under bias bias -5 to +95 torage temperature stg -65 to eiko Instruments Inc.

3 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 ecommended Operating onditions able 3 Parameter ymbol onditions Min. yp. Max. Unit ead Operation V Power supply voltage V Write Operation V V =2.5 to 5.5V.7 V V V High level input voltage V IH V =1.8 to 2.5V.8 V V V V =2.5 to 5.5V..3 V V Low level input voltage V IL V =1.8 to 2.5V..2 V V Operating temperature opr Pin apacitance able 4 (a=25, f= MHz, V =5 V) Parameter ymbol onditions Min. yp. Max. Unit Input capacitance IN V IN = V (L,, 1, 2, WP) 1 pf Input/output capacitance I / O V I / O = V (D) 1 pf Endurance able 5 Parameter ymbol Min. yp. Max. Unit Endurance N W 1 6 cycles/word eiko Instruments Inc. 3

4 MO 2-WIED EIL EEPOM -241/2/4 ev. 2.2_3 D Electrical haracteristics able 6 V =4.5 V to 5.5 V V =2.5 to 4.5 V V =1.8 to 2.5 V Parameter ymbol onditions Unit Min. yp. Max. Min. yp. Max. Min. yp. Max. urrent consumption (ED) urrent consumption (POGM) I 1 f=1 khz m I 2 f=1 khz m able 7 Parameter ymbol onditions V =4.5 V to 5.5 V V =2.5 to 4.5 V V =1.8 to 2.5 V Min. yp. Max. Min. yp. Max. Min. yp. Max. Unit tandby current consumption Input leakage current Output leakage current I B V IN =V or GND.6.4 µ I LI V IN =GND to V µ I LO V OU =GND to V µ Low level output I OL =3.2 m.4.4 V voltage V OL I OL =1.5 m V I OL=1 µ V urrent address retention voltage V H V 4 eiko Instruments Inc.

5 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 Electrical haracteristics V able 8 Measurement onditions Input pulse voltage.1 V to.9 V Input pulse rising/falling time 2 ns D =k Output judgment voltage.5 V =1pF Output load 1 pf+ Pullup resistance kω Figure 3 Output Load ircuit able 9 Parameter ymbol V =1.8V to 5.5V Min. yp. Max. Unit L clock frequency f L 1 khz L clock time "L" t LOW 4.7 µs L clock time"h" t HIGH 4. µs D output delay time t µs D output hold time t DH.3 µs tart condition setup time t U. 4.7 µs tart condition hold time t HD. 4. µs Data input setup time t U.D 5 ns Data input hold time t HD.D ns top condition setup time t U.O 4.7 µs L D rising time t µs L D falling time t F.3 µs Bus release time t BUF 4.7 µs Noise suppression time t I 1 ns t F t HIGH t LOW t L t U. t HD. t HD.D t U.D t U.O D IN t t DH t BUF D OU invalid valid Figure 4 Bus iming eiko Instruments Inc. 5

6 MO 2-WIED EIL EEPOM -241/2/4 ev. 2.2_3 able 1 Item ymbol V =4.5 to 5.5V V =2.5 to 4.5V Min. yp. Max. Min. yp. Max. Unit Write time t W ms t W L D D Write data cknowledge top condition tart condition Figure 5 Write ycle Pin Functions 1. ddress Input Pins (, 1, and 2) onnect pins, 1, and 2 to the GND or the V, respectively, to assign slave addresses. here are 8 different ways to assign slave addresses in the -241 and -242 through a combination of pins, 1, and 2, and 4 ways to assign them in the -244 through a combination of pins 1 and 2. When the input slave address coincides with the slave address transmitted from the master device, 1 device can be selected from among multiple devices connected to the bus. lways connect the address input pin to GND or V and leave it unchanged. 2. D (erial Data Input/Output) Pin he D pin is used for bilateral transmission of serial data. It consists of a signal input pin and an Nch open-drain transistor output pin. Usually pull up the D line via resistance to the V, and use it with other open-drain or open-collector output devices connected in a wired O configuration. 3. L (erial lock Input) Pin he L pin is used for serial clock input. It is capable of processing signals at the rising and falling edges of the L clock input signal. Make sure the rising time and falling time conform to the specifications. 4. E/WP Pin he -241 does not have a write protection (WP) function. he pin serves as a E pin and shoud always be connect to the GND. In the -242 and -244, this pin is used for write protection. When there is no need for write protection, connect the pin to the GND; when there is a need for write protection, connect the pin to the Vcc. 6 eiko Instruments Inc.

7 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 Operation 1. tart ondition When the L line is "H," the D line changes from "H" to "L." his allows the device to go to the start condition. ll operations begin from the start condition. 2. top ondition When the L line is "H," the D line changes from "L" to "H." his allows the device to go to the stop condition. When the device receives the stop condition signal during a read sequence, the read operation is interrupted, and the device goes to standby mode. When the device receives the stop condition signal during write sequence, the retrieval of write data is halted, and the EEPOM initiates rewrite. t U. t HD. t U.O L D tart ondition top ondition Figure 6 tart/top onditions 3. Data ransmission hanging the D line while the L line is "L" allows the data to be transmitted. start or stop condition is recognized when the D line changes while the L line is "H." t U.D t HD.D L D Figure 7 Data ransmission iming eiko Instruments Inc. 7

8 MO 2-WIED EIL EEPOM -241/2/4 ev. 2.2_3 4. cknowledgment he unit of data transmission is 8 bits. By turning the D line "L," the slave device mounted on the system bus which receives the data during the 9th clock cycle outputs the acknowledgment signal verifying the data reception. When the EEPOM is rewriting, the device does not output the acknowledgment signal. L (EEPOM Input) D (Master Output) D (EEPOM Output) tart ondition cknowledgment Output t t DH 5. Device ddressing Figure 8 cknowledgment Output iming o perform data communications, the master device mounted on the system outputs the start condition signal to the slave device. Next, the master device outputs 7-bit length device address and a 1-bit length read/write instruction code onto the D bus. Upper 4 bits of the device address are called the "Device ode," and set to "11." uccessive 3 bits are called the "lave ddress." It is used to select a device on the system bus, and compared to the predetermined address value at the address input pin (2, 1, or ). When the comparison results match, the slave device outputs the acknowledgment signal during the 9th clock cycle. Device ode lave ddress /W /W MB Device ode lave ddress Page ddress LB P /W MB LB Figure 9 Device ddress In the -244, "" does not exist in the slave addresses. o, "" becomes "P." "P" is a page address bit and is equivalent to an additional uppermost bit of the word address. ccordingly, when P="," the former half area corresponding to 2 kbits (addresses from h to FFh) in the entire memory are selected; when P="1," the latter half area corresponding to 2 kbits (addresses from 1h to 1FFh) in all areas of the memory are selected. 8 eiko Instruments Inc.

9 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 6. Write 6.1 Byte Write When the EEPOM receives a 7-bit length device address and a 1-bit read/write instruction code "," following the start condition signal, it outputs the acknowledgment signal. Next, when the EEPOM receives an 8-bit length word address, it outputs the acknowledgment signal. fter the EEPOM receives 8-bit write data and outputs the acknowledgment signal, it receives the stop condition signal. Next, the EEPOM at the specified memory address starts to rewrite. When the EEPOM is rewriting, all operations are prohibited and the acknowledgment signal is not output. W I DEVIE DDE E WOD DDE D O P D W7W6W5W4W3W2W1W D7 D6 D5 D4 D3 D2 D1 D M B L B / W W7 is optional in the is P in the D IN (DDE INEMEN) Figure 1 Byte Write 6.2 Page Write Up to 8 bytes per page can be written in the -241 and Up to 16 bytes per page can be written in the Basic data transmission procedures are the same as those in the "Byte Write." However, when the EEPOM receives 8-bit write data which corresponds to the page size, the page can be written. When the EEPOM receives a 7-bit length device address and a 1-bit read/write instruction code "," following the start condition signal, it outputs the acknowledgment signal. When the EEPOM receives an 8-bit length word address, it outputs the acknowledgment signal. fter the EEPOM receives 8-bit write data and outputs the acknowledgment signal, it receives 8- bit write data corresponding to the next word address, and outputs the acknowledgment signal. he EEPOM repeats reception of 8-bit write data and output of the acknowledgment signal in succession. It is capable of receiving write data corresponding to the maximum page size. When the EEPOM receives the stop condition signal, it starts to rewrite, corresponding to the size of the page, on which write data, starting from the specified memory address, is received. eiko Instruments Inc. 9

10 MO 2-WIED EIL EEPOM -241/2/4 ev. 2.2_3 W I DEVIE DDE E WOD DDE (n) D (n) D (n+1) D (n+x) O P D LINE W7W6W5W4W3W2W1W D7 D6 D5 D4 D3 D2 D1 D D7 D D7 D M B L B / W W7 is optional in the is P in the D IN D IN D IN Figure 11 Page Write In the -241 or -242, the lower 3 bits of the word address are automatically incremented each when the EEPOM receives 8-bit write data. Even if the write data exceeds 8 bytes, the upper 5 bits at the word address remain unchanged, the lower 3 bits are rolled over and overwritten. In the -244, the lower 4 bits at the word address are automatically incremented each when the EEPOM receives 8 bit write data. Even when the write data exceeds 16 bytes, the upper 4 bits of the word address and page address P remain unchanged, and the lower 4 bits are rolled over and overwritten. 6.3 cknowledgment Polling cknowledgment polling is used to know when the rewriting of the EEPOM is finished. fter the EEPOM receives the stop condition signal and once it starts to rewrite, all operations are prohibited. lso, the EEPOM cannot respond to the signal transmitted by the master device. ccordingly, the master device transmits the start condition signal and the device address read/write instruction code to the EEPOM (namely, the slave device) to detect the response of the slave device. his allows users to know when the rewriting of the EEPOM is finished. hat is, if the slave device does not output the acknowledgment signal, it means that the EEPOM is rewriting; when the slave device outputs the acknowledgment signal, you can know that rewriting has been completed. It is recommended to use read instruction "1" for the read/write instruction code transmitted by the master device. 6.4 Write Protection he -242 and the -244 are capable of protecting the memory. When the WP pin is connected to V, writing to 5% of the latter half of all memory area (8h to FFh in the -242; 1h to 1FFh in the -244) is prohibited. Even when writing is prohibited, since the controller inside the I is operating, the response to the signal transmitted by the master device is not available during the time of writing (t W ). When the WP pin is connected to GND, the write protection becomes invalid, and writing in all memory area becomes available. However, when there is no need for using write protection, always connect the WP pin to GND. 1 eiko Instruments Inc.

11 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 7. ead 7.1 urrent ddress ead he EEPOM is capable of storing the last accessed memory address during both writing and reading. he memory address is stored as long as the power voltage is more than the retention voltage V H. ccordingly, when the master device recognizes the position of the address pointer inside the EEPOM, data can be read from the memory address of the current address pointer without assigning a word address. his is called "urrent ddress ead." "urrent ddress ead" is explained for when the address counter inside the EEPOM is an "n" address. When the EEPOM receives a 7-bit length device address and a 1-bit read/write instruction code "1," following the start condition signal, it outputs the acknowledgment signal. However, in the - 244, page address P becomes invalid, and the memory address of the current address pointer becomes valid. Next, 8-bit length data at an "n" address is output from the EEPOM, in synchronization with the L clock. he address counter is incremented at the falling edge of the L clock by which the 8th bit of data is output, and the address counter goes to address n+1. he master device does not output the acknowledgment signal and transmits the stop condition signal to finish reading. DEVIE DDE E D NO from Master Device O P D LINE D7 D6 D5 D4 D3 D2 D1 D M B L B / W D ( is P in the -244) D IN Figure 12 urrent ddress ead For recognition of the address pointer inside the EEPOM, take into consideration the following: he memory address counter inside the EEPOM is automatically incremented for every falling edge of the L clock by which the 8th bit of data is output during the time of reading. During the time of writing, upper bits of the memory address (upper 5 bits of the word address in the -241 and -242; upper 4 bits of the word address and page address P in the -244) are left unchanged and are not incremented. eiko Instruments Inc. 11

12 MO 2-WIED EIL EEPOM -241/2/4 ev. 2.2_3 7.2 andom ead andom read is a mode used when the data is read from arbitrary memory addresses. o load a memory address into the address counter inside the EEPOM, first perform a dummy write according to the following procedures: When the EEPOM receives a 7-bit length device address and a 1-bit read/write instruction code "," following the start condition signal, it outputs the acknowledgment signal. Next, the EEPOM receives an 8-bit length word address and outputs the acknowledgment signal. Last, the memory address is loaded into the address counter of the EEPOM. the EEPOM receives the write data during byte or page writing. However, data reception is not performed during dummy write. he memory address is loaded into the memory address counter inside the EEPOM during dummy write. fter that, the master device can read the data starting from the arbitrary memory address by transmitting a new start condition signal and performing the same operation as that in the "urrent ead." hat is, when the EEPOM receives a 7-bit length device address and a 1-bit read/write instruction code "1," following the start condition signal, it outputs the acknowledgment signal. Next, 8-bit length data is output from the EEPOM, in synchronization with the L clock. he master device does not output an acknowledgment signal and transmits the stop condition signal to finish reading. DEVIE DDE W I E WOD DDE (n) DEVIE DDE E D NO from Master Device O P D LINE W7W6W5W4W3W2W1W D7 D6 D5 D4 D3 D2 D1 D M B L B / W D (n) DUMMY WIE D IN W7 is optional in the is P in the Figure 13 andom ead 12 eiko Instruments Inc.

13 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 7.3 equential ead When the EEPOM receives a 7-bit length device address and a 1-bit read/write instruction code "1" in both current and random read operations, following the start condition signal, it outputs the acknowledgment signal When 8-bit length data is output from the EEPOM, in synchronization with the L clock, the memory address counter inside the EEPOM is automatically incremented at the falling edge of the L clock, by which the 8th data is output. When the master device transmits the acknowledgment signal, the next memory address data is output. When the master device transmits the acknowledgment signal, the memory address counter inside the EEPOM is incremented and read data in succession. his is called "equential ead." When the master device does not output an acknowledgement signal and transmits the stop condition signal, the read operation is finished. Data can be read in the "equential ead" mode in succession. When the memory address counter reaches the last word address, it rolls over to the first memory address. DEVIE DDE E D NO from Master Device O P D LINE 1 D7 D D7 D D7 D D7 D / W D (n) D (n+1) D (n+2) D (n+x) D IN D IN D IN D IN Figure 14 equential ead eiko Instruments Inc. 13

14 MO 2-WIED EIL EEPOM -241/2/4 ev. 2.2_3 8. ddress Increment iming he address increment timing is as follows. ee Figures 15 and 16. During reading operation, the memory address counter is automatically incremented at the falling edge of the L clock (the 8th read data is output). During writing operation, the memory address counter is also automatically incremented at the falling edge of the L clock when the 8th bit write data is fetched. L D / W=1 Output D7 Output D Output ddress Increment Figure 15 ddress Increment iming During eading L D / W= Output D7 Input D Input Output ddress Increment Figure 16 ddress Increment iming During Writing Purchase of I 2 components of eiko Instruments Inc. conveys a license under the Philips I 2 Patent ights to use these components in an I 2 system, provided that the system conforms to the I 2 tandard pecification as defined by Philips. Please note that any product or system incorporating this I may infringe upon the Philips I 2 Bus Patent ights depending upon its configuration. In the event that such product or system incorporating the I 2 Bus infringes upon the Philips Patent ights, eiko Instruments Inc. shall not bear any responsibility for any matters with regard to and arising from such patent infringement. 14 eiko Instruments Inc.

15 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 Ordering Information -24x yyy - zz - uuw P code (Distincion for package process) None 1 Endurance code 11 : 1 6 cycles aping specification None for DIP and OP in magazine B Package code DP : DIP DP : DIP FJ : OP Product name -241 : 1k bits -242 : 2k bits -244 : 4k bits Ordering names for DIP Product name Package code aping specification Endurance code P code Package/ape/eel drawings DP None None 1 DP8- DP None 11 None DP8- Note he endurarance of -24xDP-1 is 1 6 cycles, though the ordering name does not have the endurance code. Ordering names for OP Product name Package code aping specification FJ FJ FJ B (None for magazine) B (None for magazine) B (None for magazine) Endurance code P code Package/ape/eel drawings 11 None FJ8-D 11 None FJ8-D FJ8-D FJ8-E 11 None FJ8-D Note 1) Package dimensions of OPs whose package code is FJ are the same in the range of deviation. 2) Please contact an II local office or a local representative for details. eiko Instruments Inc. 15

16 MO 2-WIED EIL EEPOM -241/2/4 ev. 2.2_3 haracteristics 1. D haracteristics 1.1 urrent consumption (ED) I 1 mbient temperature a 1.2 urrent consumption (ED) I 1 mbient temperature a 2 V =5.5 V fscl=1 Hz D=11 2 V =3.3 V fscl=1 Hz D=11 I 1 (µ) 1 I 1 (µ) urrent consumption (ED) I 1 mbient temperature a 1.4 urrent consumption (ED) I 1 Power supply voltage V 4 V =1.8 V fscl=1 Hz D=11 1 a=25 fscl=1 Hz D=11 I 1 (µ) 2 I 1 (µ) V (V) 1.5 urrent consumption (ED) I urrent consumption (ED) I 1 Power supply voltage V lock frequency fscl 1 a=25 fscl=4 Hz D=11 1 V =5. V a=25 I 1 (µ) 5 I 1 (µ) V (V) fscl(hz) 1.7 urrent consumption (POGM) I 2 mbient temperature a V =5.5 V 1.8 urrent consumption (POGM) I 2 mbient temperature a V =3.3 V I 2 (m).5 I 2 (m).5 16 eiko Instruments Inc.

17 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 1.9 urrent consumption (POGM) I 2 mbient temperature a V =2.5 V 1.1 urrent consumption (POGM) I 2 Power supply voltage V a=25 I 2 (m).5 I 2 (m) V (V) 1.11 tandby current consumption I B mbient temperature a 1.12 Input leakage current I LI mbient temperature a I B () V =5.5 V I LI (µ).5 V =5.5 V, 1, 2, D L,E/WP=V 1.13 Input leakage current I LI mbient temperature a 1.14 Output leakage current I LO mbient temperature a V =5.5 V, 1, 2, D L, E/WP=5.5V V =5.5 V D=V I LI (µ).5 I LO (µ) Output leakage current I LO mbient temperature a V =5.5 V D=5.5 V I LO (µ).5 eiko Instruments Inc. 17

18 MO 2-WIED EIL EEPOM -241/2/4 ev. 2.2_ Low level output voltage V OL mbient temperature a 1.17 Low level output voltage V OL mbient temperature a.3 V =4.5 V I OL =2.3 m.3 V =1.8 V I OL =1 µ V OL (V).2 V OL (V) Low level output current I OL mbient temperature a 2 V =4.5 V V OL =.45 V 1.19 Low level output current I OL mbient temperature a V =1.8 V V OL =.1 V I OL (m) 1 I OL (m) High input inversion voltage VIH Power supply voltagev 1.21 High input inversion voltage VIH mbient temperature a 3. a=25, 1, 2, D L, E/WP 3. V =5. V, 1, 2, D L, E/WP VIH (V) 2. VIH (V) V (V) 1.22 Low input inversion voltage VIL 1.23 Low input inversion voltage VIL Power supply voltagev mbient temperature a 3. a=25, 1, 2, D L, E/WP 3. a=5.v, 1, 2, D L, E/WP VIL (V) 2. VIL (V) V (V) 18 eiko Instruments Inc.

19 ev. 2.2_3 MO 2-WIE EIL EEPOM -241/2/4 2. haracteristics 2.1 Maximum operating frequency fmax Power supply voltage V 2.2 Write time t W Power supply voltage V a=25 a=25 f max 1M (Hz) 1 1 t W (ms) V (V) V (V) 2.3 Write time t W mbient temperature a 2.4 Write time t W mbient temperature a V =4.5 V V =2.5 V t W (ms) t W (ms) D output delay time t PD mbient temperature a 2.6 D output delay time t PD mbient temperature a t PD (µs) 1.5 V =4.5 V t PD (µs) 1.5 V =2.7 V Data output delay time t PD mbient temperature a t PD (µs) V =1.8 V eiko Instruments Inc. 19

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23 he information described herein is subject to change without notice. eiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. he application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar rrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of eiko Instruments Inc. is strictly prohibited. he products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of eiko Instruments Inc. lthough eiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. he user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.