MR44V100A GENERAL DESCRIPTION FEATURES 1/18. FEDR44V100A-01 Issue Date: Sep. 04, 2017

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1 1M Bit(131,2-ord -ord 8-Bit) FeM (Ferroelectric andom ccess Memory) I2 Issue ate: ep. 4, 21 GENEL EIPION he is a nonvolatile 131,2-word x 8-bit ferroelectric random access memory (FeM) developed in the ferroelectric process and silicon-gate MO technology. he is accessed using wo-wire erial Interface ( I2 BU ).Unlike Ms, this device, whose cells are nonvolatile, eliminates battery backup required to hold data. his device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPOMs. herefore, the write cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. he can be used in various applications, because the device is guaranteed for the write/read tolerance of 1 12 cycles per bit and the rewrite count can be extended significantly. FEUE 131,2-word 8-bit configuration I2 BU Interface single 3.3 V typ. (1.8V to 3.6V) power supply Operating frequency: 3.4MHz(Max) H-mode 1MHz(Max) F/-mode Plus ead/write tolerance 1 12 cycles/bit ata retention 1 years Guaranteed operating temperature range 4 to 85 Low power consumption Power supply current (@3.4MHz) 1.1m(Max.) tandby mode supply current 1μ(yp.), 5μ(Max.) leep mode supply current.1μ(yp.), 2μ(Max.) Package options: 8-pin plastic OP (P-OP ) oh (estriction of hazardous substances) compliant 1/18

2 PIN ONFIGUION 8-pin plastic OP N 1 2 V V P L PIN EIPION Pin Name escription N 1 2 L P V, V Not onnected Pin (open) It should always be left open or connected to any potential (ground, power supply) ddress ( input ) ddress pin indicates device address. hen ddress value is match the device address code from, the device will be selected. he address pins are pulled down internally. erial data input serial data output ( input / output ) is a bi-directional line for I2 interface. he output driver is open-drain. pull-up resistor is required. erial lock ( input ) erial lock is the clock input pin for setting for serial data timing. Inputs are latched on the rising edge and outputs occur on the falling edge. rite protect ( input ) rite Protect pin controls write-operation to the memory. hen P is high, all address in the memory will be protected. hen P is low, all address in the memory will be written. P pin is pulled down internally. Power supply pply the specified voltage to V. onnect V to ground. 2/18

3 I2 BU he employs a bi-directional two-wire I2 BU interface, works as a slave device. n example of I2 interface system with L Pull-up resistor L I2 BU master L (slave) 2 1 L (slave) I2 BU OMUNIION I2 BU data communication starts by start condition input, and ends by stop condition input. ata is always 8bit long, acknowledge is always required after each byte. I2 BU carries out data transmission with plural devices connected by 2 communication lines of serial data ( ) and serial clock ( L ). L condition E / OP condition ONIION Before executing each command, start condition ( start bit ) where goes from HIGH down to LO when L is HIGH is necessary. always detects whether and L are in start condition ( start bit ) or not, therefore, unless this condition is satisfied, any command is not executed. OP ONIION Each command can be ended by rising from LO to HIGH when stop condition ( stop bit ), namely, L is HIGH. 3/18

4 NOLEGE ( ) IGNL his acknowledge ( ) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (μ-om at slave address input of write command, read command, and this I at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. he device (this I at slave address input of write command, read command, and μ-om at data output of read command) at the receiver (receiving) side sets LO during 9 clock cycles, and outputs acknowledge signal ( signal) showing that it has received the 8bit data. his I, after recognizing start condition and slave address (8bit), outputs acknowledge signal ( signal) LO. Each write action outputs acknowledge signal ( signal ) LO, at receiving 8bit data ( word address and write data ). Each read action outputs 8bit data ( read data ), and detects acknowledge signal ( signal ) LO. hen acknowledge signal ( signal ) is detect, and stop condition is not sent from the master (μ-om) side, this I continues data output. hen acknowledge signal ( signal ) is not detected, this I stops data transfer, and recognizes stop condition ( stop bit ), and ends read action. nd this I gets in status. LVE E Output a slave address after start condition from master. he significant 4 bits of slave address are used for recognizing a device type. he device code of this I is fixed to 11. Next slave addresses (2 1 device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses, and next comes most significant bit (16). he most insignificant bit (/ E/IE) of slave address is used for designating write or read action, and is as shown below. etting / to write (setting to word address setting of random read) etting / to 1 read L / condition IE POE hen P terminal is set Vcc(H level), data rewrite of all addresses is prohibited. hen it is set Vss(L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or Vss, or control it to H level or L level. Because this terminal is pulled down internally, in the case of Open the terminal will be recognized as L level uring write cycle P terminal must be always L level. P terminal must be fixed from start condition to stop condition. 4/18

5 OMMN BYE IE YLE rbitrary data is written to FeM. hen to write only 1 byte, byte write is normally used. start condition slave address with LB is (write) 1 st and 2 nd word address byte of write data. stop condition lave address I E 1 st O address 2 nd O address 15 8 rite data O P PGE IE YLE hen to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. he address reaches the final address, the address will be rolled over to the first address. By page write cycle, up to 128 bytes data can be written. hen data above the maximum bytes are sent, data from the first byte will be overwritten. I lave address E 1 st O address 2 nd O address rite data rite data O P NOM E YLE andom read cycle is a command to read data by designating address. andom read sequence 1. Next to tart condition, slave address with LB is (write) 2. 1 st and 2 nd word address 3. Next to tart condition, slave address with LB is 1 (read) he bit of equivalent to 16 is ignored. 4. read out byte of data. 5. to H 6. end top condition and finish the sequence. I lave address E 1 st O address 2 nd O address lave address X E ead data N O P 5/18

6 EQUENIL E YLE hen signal L after is detected, and stop condition is not sent from master side, the next address data can be read in succession. he address reaches the final address, the address will be rolled over to the first address. I lave address E 1 st O address 2 nd O address UEN E E YLE urrent address read cycle is a command to read data of internal address register without designating address. hen the last read or write address is (n)-th address just before current read cycle, the current address read command outputs data of (n+1)-th address. he previous read or write sequence should be complete up to stop condition. Just after POE ON or after recovering from LEEP mode, the internal address resister is unstable. lave address X E ead data O P lave address X E ead data N O P N H-MOE he support a maximum 3.4MHz high speed mode. hen H-mode operation is needed, the H-mode command is required before any command. fter the H-mode command is issued, will be the H-mode, until stop condition is issued. UEN E E YLE ( H-MOE ) H-mode command lave address E ead data O P 1 X X X X N H mode N BYE IE YLE ( H-MOE ) H-mode command 1 X X X N I lave address E 1 st O address 2 nd O address H mode rite data O P 6/18

7 EVIE I he device I can be read out. he I is constructed with 12bit Manufacture I and 12bit evice type. evice I ead equence 1. Next to tart condition, send xf8. responds signal. 2. end the lave address (16 and / are on t care ). responds signal. 3. gain next to tart condition, send xf9. responds signal, then outputs 3 bytes of evice I. 4. end top condition and finish the sequence. 1 st Byte 2 nd Byte 3 rd Byte x1 xb x Manufacture I ( LPI ) evice ype ( ) xf8 lave address xf9 ead data ead data ead data O P X X Manufacture I evice type N LEEP can provide LEEP Mode which suppresses the current consumption more than tandby status. ransition to LEEP Mode and eturn from LEEP mode are the following sequences. ransition to LEEP Mode 1. Next to tart condition, send xf8. responds signal. 2. end the lave address (16 and / are on t care ). responds signal. 3. gain Next to tart condition, send xf8. responds signal and transits to LEEP Mode. 4. end top condition, finish the sequence. xf lave address x X X O P eturn from LEEP Mode 1. Next to tart condition, send the lave address (16 and / are on t care. 2. hen the device address is matched, tart the operation of returning from LEEP Mode at the falling edge of 6th clocks of L after tart condition. hen the device address is not matched, LEEP mode will continue.. 3. eturn to standby after the eturning time from LEEP. fter that, as sending the lave address and responding signal, is returning from LEEP. lave address X X X eturning tart returning lave address / 16 aution : hen to input lave address for returning from LEEP mode, top condition is not recognized. /18

8 oftware eset oftware reset is executed to avoid malfunction after power ON, and during command input. L tart condition x 9 Normal command 8/18

9 ELEIL HEII BOLUE MXIMUM ING he application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. herefore, do not allow actual characteristics to exceed any one parameter ratings PIN VOLGE Parameter ymbol Min. ating Max. Unit Note Pin Voltage (Input ignal) V IN.5 V +.5 V Pin Voltage (Input/Output Voltage) V INQ, V OUQ.5 V +.5 V Power upply Voltage V.5 4. V EMPEUE NGE Parameter ymbol Min. ating Max. Unit Note torage emperature stg Operating emperature opr 4 85 OHE Parameter ymbol ating Note Power issipation P 1,m a=25 9/18

10 EOMMENE OPEING ONIION POE UPPLY VOLGE Parameter ymbol Min. yp. Max. Unit Note Power upply Voltage V V Ground Voltage V V INPU VOLGE Parameter ymbol Min. Max. Unit Note Input High Voltage V IH V x. V +.3 V Input Low Voltage V IL.3 V x.3 V 1/18

11 HEII INPU/OUPU HEII Parameter ymbol ondition Min. Max. Unit Note Output Low Voltage V OL I OL =3m.4 V Input Leakage urrent I LI 1 1 µ Output Leakage urrent I LO 1 1 µ POE UPPLY UEN V =Max.to Min, a=opr Parameter ymbol ondition yp.* Max. Unit Note Power upply urrent (tandby) Power upply urrent (leep) I I ZZ L,= V, 2,1= V or V L,= V, 2,1,P= V or V Power upply urrent (Operating) I V IN =.3V or V -.3V, fl=3.4mhz fl=1mhz Note: ypical condition Vcc=3.3V, a=oom temperature. 1 5 µ.1 2 µ m µ 11/18

12 HEII Parameter ymbol F/-mode F/-mode Plus V =Max. to Min., a=opr. H-mode Min. Max. Min. Max. Min. Max. Unit Note lock frequency f L Hz lock Low time tlo ns lock High time thigh ns Output ata delay time t ns BU release time before transfer start tbuf ns tart condition hold time th: ns tart condition setup time tu: ns Input data hold time th: ns Input data setup time tu: ns, L rise time t ns 1, L fall time tf ns 1 top condition setup time tu:o ns Output data hold time th ns Noise removal time (, L) tp ns leep mode recovery time te µs Note: 1. Not 1% tested Equivalent Load ircuit 3.3V 1kΩ Output 1pF 12/18

13 IMING 1/fL L (input) (output) t tf VIH t tf thigh VIH VIH VIH VIH tu: tlo VIH VIH tbuf t th VIH VIH th: tp VIH VIH tp L VIH VIH VIH (input) tu: th: tu:o VIH BI OP BI 13/18

14 POE-ON N POE-OFF HEII (Under recommended operating conditions) Parameter ymbol Min. Max. Unit Note Power-On L, High Hold ime t VHEL 1 ns 1, 2 Power-Off L, High Hold ime t EHVL ns 1 Power-On Interval ime t VLVH μs 2 V Power-On ramp rate tr 3 μs/v V Power-Off ramp rate tf 3 μs/v Notes: 1. o prevent an erroneous operation, be sure to maintain L=="H", and set the FeM in an inactive state (standby mode) before and after power-on and power-off. 2. Powering on at the intermediate voltage level will cause an erroneous operation; thus, be sure to power up from V. 3. Enter all signals at the same time as power-on or enter all signals after power-on. Power-On and Power-Off equences t EHVL t VHEL V V V Min. V Min. V IH Min. t f t r V IH Min. t VLVH V IL Max. L, V V IL Max. L, V fter Power-Off, terminal state hen only goes power-off while the other I s on I2 bus are active, all the input pins including I/O pin of must be GN level. (hen to reduce stand-by current while L or bus are active, recommend the use of LEEP mode.) 14/18

15 E/IE YLE N EENION a=opr (Under recommended operating conditions) Parameter Min. Max. Unit Note ead/rite ycle 1 12 ycle ata etention 1 Year PINE V =3.3V, V IN = V OU = GN, f = 1MHz, and a = 25 ignal ymbol Min. Max. Unit Note Input apacitance IN 1 pf 1 Input/Output apacitance OU 1 pf 1 Note1: ampling value. 15/18

16 PGE IMENION (Unit: mm) Notes for Mounting the urface Mount ype Package he surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. herefore, before you perform reflow mounting, contact a OHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/18

17 EVIION HIOY ocument No. ate Previous Edition Page urrent Edition escription ep. 4, 21 Final edition 1 1/18

18 Notes 1) he information contained herein is subject to change without notice. 2) lthough LPI emiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. herefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LPI emiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LPI emiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products. he peripheral conditions must be taken into account when designing circuits for mass production. 4) he technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LPI emiconductor or any third party with respect to the information contained in this document; therefore LPI emiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) he Products are intended for use in general electronic equipment (i.e. V/O devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) he Products specified in this document are not designed to be radiation tolerant. ) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LPI emiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) o not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) LPI emiconductor shall have no responsibility for any damages or injury arising from non-compliance with the recommended usage conditions and specifications contained herein. 1) LPI emiconductor has used reasonable care to ensure the accuracy of the information contained in this document. However, LPI emiconductor does not warrant that such information is error-free and LPI emiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the oh irective. For more details, including oh compatibility, please contact a OHM sales office. LPI emiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) hen providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the U Export dministration egulations and the Foreign Exchange and Foreign rade ct. 13) his document, in part or in whole, may not be reprinted or reproduced without prior consent of LPI emiconductor. opyright 21 LPI emiconductor o., Ltd hinyokohama, ouhoku-ku, Yokohama , Japan 18/18

MR44V064B GENERAL DESCRIPTION FEATURES 1/16. FEDR44V064B-01 Issue Date: Jan. 08, 2016

MR44V064B GENERAL DESCRIPTION FEATURES 1/16. FEDR44V064B-01 Issue Date: Jan. 08, 2016 M44V64B 64k(8,192-ord 8-Bit) FeM (Ferroelectric andom ccess Memory) I2 FE44V64B-1 Issue ate: Jan. 8, 216 GENEL EIPION he M44V64B is a nonvolatile 8,192-word x 8-bit ferroelectric random access memory (FeM)