Marking side (top view)

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1 BL24C64 64Kbits (8,192 8) Features Compatible with all I 2 C bidirectional data transfer protocol Memory array: 64 Kbits (8 Kbytes) of EEPOM Page size: 32 bytes ingle supply voltage and high speed: 1 MHz andom and sequential ead modes Write: Byte Write within 3 ms Page Write within 3 ms Partial Page Writes llowed chmitt rigger, Filtered Inputs for Noise uppression High-reliability Endurance: 1 Million Write Cycles Data etention: 100 Years Enhanced ED/Latch-up protection HBM 8000V WLCP4 packages Description he BL24C64 provides bits of serial electrically erasable and programmable readonly memory (EEPOM), organized as 8192 words of 8 bits each. he device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. Pin Configuration WLCP4 1 2 Vcc Vss B CL D Marking side (top view) Pin Descriptions BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

2 X DECODE BL24C64 64Kbits (8,192 8) Block Diagram Pin Name ype Functions 1 Vcc P Power upply 2 Vss P Groung B1 CL I erial Clock Input B2 D I/O erial Data able 1 Vcc GND CL D OP LOGIC EIL CONOL LOGIC EN HIGH VOLGE PUMP/IMING DEVICE DDE COMPO LOD CCMP LOD INC D ECOVEY D WOD DE COUNE EEPOM Y DECODE EIL MUX DIN DOU/CKNOWLEDGE DOU Figure 1 EIL D (D): he D pin is bi-directional for serial data transfer. his pin is open-drain driven and may be wire-oed with any number of other open-drain or open- collector devices. EIL CLOCK (CL): he CL input is used to positive edge clock data into each EEPOM device and negative edge clock data out of each device. BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

3 BL24C64 64Kbits (8,192 8) Functional Description 1. Memory Organization BL24C64, 64K EIL EEPOM: Internally organized with 256 pages of 32 bytes each, the 64K requires a 13-bit data word address for random word addressing. 2. Device Operation CLOCK and D NIION: he D pin is normally pulled high with an external device. Data on the D pin may change only during CL low time periods (see Figure 2). Data changes during CL high periods will indicate a start or stop condition as defined below. CONDIION: high-to-low transition of D with CL high is a start condition which must precede any other command (see Figure 3). OP CONDIION: low-to-high transition of D with CL high is a stop condition. fter a read sequence, the stop command will place the EEPOM in a standby power mode (see Figure 3). CKNOWLEDGE: ll addresses and data words are serially transmitted to and from the EEPOM in 8-bit words. he EEPOM sends a "0" to acknowledge that it has received each word. his happens during the ninth clock cycle. NDBY MODE: he BL24C64 features a low-power standby mode which is enabled: (a) upon powerup and (b) after the receipt of the OP bit and the completion of any internal operations. MEMOY EE: fter an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for D high in each cycle while CL is high. 3. Create a start condition. ILLEGL INUCION : he EEPOM maybe sends a "0" to acknowledge that it has received any one of the following two instruction as write/read instructions. 1.Device address= b. 2.Device address= b If device address= b,next step need 9 cycles Clock to stop the instruction. BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

4 BL24C64 64Kbits (8,192 8) Figure 2. Data Validity D CL D BLE D CHNGE D BLE Figure 3. tart and top Definition D CL OP Figure 4. Output cknowledge CL D IN D OU CKNOWLEDGE BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

5 BL24C64 64Kbits (8,192 8) 3. Device ddressing he 64K EEPOM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5) he device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. his is common to all the erial EEPOM devices. he four most significant bits of the slave address are fixed (1010). he next three bits are default to 0. he eighth bit of the device address is the read/write operation select bit. read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPOM will output a "0". If a compare is not made, the chip will return to a standby state. Figure 5. Device ddress MB LB /W 4. Write Operations BYE WIE: write operation requires two 8-bit data word address, as able2&able3, following the device address word and acknowledgment. Upon receipt of this address, the EEPOM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPOM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. t this time the EEPOM enters an internally timed write cycle, tw, to the nonvolatile memory. ll inputs are disabled during this write cycle and the EEPOM will not respond until the write is complete (see Figure 6). PGE WIE: write operation requires two 8-bit data word address, as able2&able3, following the device address word and acknowledgment. Upon receipt of this address, the EEPOM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPOM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. t this time the EEPOM enters an internally timed write cycle, tw, to the nonvolatile memory. ll inputs are disabled during this write cycle and the EEPOM will not respond until the write is complete (see Figure 7). he data word address lower five bits are internally incremented following the receipt of each data word. he higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPOM, the data word address will "roll over" and previous data will be overwritten. BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

6 BL24C64 64Kbits (8,192 8) able 2. FI WOD DDE B12 B11 B10 B9 B8 able 3. ECOND WOD DDE B7 B6 B5 B4 B3 B2 B1 B0 CKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPOM inputs are disabled, acknowledge polling can be initiated. his involves sending a start condition followed by the device address word. he read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPOM respond with a "0", allowing the read or write sequence to continue. 5. ead Operations ead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". here are three read operations: current address read, random address read and sequential read. CUEN DDE ED: he internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. his address stays valid between operations as long as the chip power is maintained. he address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. he address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPOM, the current address data word is serially clocked out. he microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 8). NDOM ED: random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPOM, the microcontroller must generate another start condition. he microcontroller now initiates a current address read by sending a device address with the read/write select bit high. he EEPOM acknowledges the device address and serially clocks out the data word. he microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9) EQUENIL ED: equential reads are initiated by either a current address read or a random address read. fter the microcontroller receives a data word, it responds with an acknowledge. s long as the EEPOM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. he sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 10). BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

7 BL24C64 64Kbits (8,192 8) Figure 6. Byte Write D LINE DEVICE DDE W I E FI WOD DDE ECOND WOD DDE D O P M B L / C B W K L C B K L C B K L C B K Note.1*=DON' CE bits Figure 7. Page Write DEVICE DDE W I E FI WOD DDE ECOND WOD DDE D(n) D(n+1) D(n+1) O P D LINE M B L / C B W K L C B K L C B K C K C K C K Note.1*=DON' CE bits Figure 8. Current ddress ead DEVICE DDE E D D O P D LINE M B L / C B W K NO CK Figure 9. andom ead DEVICE DDE W I E 1st,2nd WOD DDE DEVICE DDE E D D(n) O P D LINE M B L / C B W K L C B K C K NO CK DUMMY WIE Note.1*=DON' CE bits BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

8 BL24C64 64Kbits (8,192 8) Figure 10. equential ead DEVICE DDE E D D(n) D(n+1) D(n+2) D(n+x) O P D LINE / C W K C K C K C K NO CK BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

9 BL24C64 64Kbits (8,192 8) Electrical Characteristics bsolute Maximum tress atings: DC upply Voltage V to +6.5V Input / Output Voltage GND-0.3V to VCC+0.3V Operating mbient emperature to +85 torage emperature to +150 Electrostatic pulse (Human Body model) V Note1. Compliant with JEDEC standard J-D-020D (for small-body, n-pb or Pb free assembly). Comments: tresses above those listed under "bsolute Maximum atings" may cause permanent damage to this device. hese are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics pplicable over recommended operating range from: = -40 to +85, VCC = +1.7V to +5.5V (unless otherwise noted) Parameter ymbol Min yp Max Unit Condition upply Voltage VCC V - upply Current VCC=5.0V ICC m ED at 400KHZ upply Current VCC=5.0V ICC m WIE at 400KHZ upply Current VCC=5.0V IB μ VIN=VCC or V Input Leakage Current IL μ VIN=VCC or V Output Leakage Current ILO μ VOU=VCC or V Input Low Level VIL VCC 0.3 V VCC=1.7V to 5.5V Input High Level VIH1 VCC VCC+0.3 V VCC=1.7V to 5.5V Output Low Level VCC=1.7V VOL V IOL=2.1m Output Low Level VCC=5.0V VOL V IOL=3.0m able 4 Pin Capacitance pplicable over recommended operating range from = 25, f = 1.0 MHz, VCC = +1.7V Parameter ymbol Min yp Max Unit Condition Input/Output Capacitance(D) CI/O pf VIO=0V Input Capacitance(CL) CIN pf VIN=0V able 5 BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

10 BL24C64 64Kbits (8,192 8) C Electrical Characteristics pplicable over recommended operating range from = -40 to +85, VCC = +1.7V to +5.5V, CL = 1 L Gate and 100 pf (unless otherwise noted) Min yp Max Min yp Max Clock Frequency,CL fcl khz Clock Pulse Width Low tlow μs Clock Pulse Width High thigh μs Noise uppression ime ti ns Clock Low to Data Out Valid t μs ime the bus must be free before a new transmission can tbuf μs start tart Hold ime thd: μs tart etup ime tu: μs Data In Hold ime thd:d μs Data in etup ime tu:d ns Input ise ime(1) t μs Input Fall ime(1) tf μs top etup ime tu:o μs Data Out Hold ime tdh ns Write Cycle ime tw ms 5.0V,25,Byte Mode(1) Endurance 1M - - 1M - - Write Cycle Notes: Parameter ymbol 1.7V VCC < 2.5V 2.5V VCC < 5.5V able 6 1. his parameter is characterized and is not 100% tested. 2. C measurement conditions: L (connects to VCC): 1.3 k Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 ns Input and output timing reference voltages: 0.5 VCC he value of L should be concerned according to the actual loading on the user's system. Units BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

11 BL24C64 64Kbits (8,192 8) Bus iming Figure 11. CL: erial Clock, D: erial Data I/O tf thigh tlow t CL tlow tu. thd. thd.d tu.d tu.o D_IN t tdh t BUF D_OU Write Cycle iming Figure 12. CL: erial Clock, D: erial Data I/O CL CK D Word n tw(1) OP CONDIION CONDIION Notes: he write cycle time tw is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

12 BL24C64 64Kbits (8,192 8) Package Information WLCP E X1 E1 X2 Y1 b D PIN1 D1 Y2 OP VIEW (MK IDE) BOOM VIEW (BLL IDE) 1 IDE VIEW 2 COMMON DIMENION (UNI OF MEUE=MILLIMEE) YMBOL MIN NOM MX D D1 E BC E1 b BC x1 x2 y1 y EF EF EF EF Notes: ll wafer orientation notch down BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

13 BL24C64 64Kbits (8,192 8) Marking Diagram 6YW 1 PIN MK Y:he last digits of the year W:week code. Y Year W Y Z a y z Week Ordering Information BL24C Code Description 1 Package type C: WLCP-4 2 Packing type : ape and eel BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

14 BL24C64 64Kbits (8,192 8) Device Package hipping(qty/packing) BL24C64-C- WLCP-4, 0.688*0.758 (Pb-Free/Halogen Free) 5000/ape &eel 2.0± ±0.1 B +0.1 Φ ± ± ±0.1 B Φ0.2± ± ± MX 0.44± MX ection ±0.05 ection B-B BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

15 BL24C64 64Kbits (8,192 8) evision History Version 1.0 BL24C64-C- Initial version Version 1.1 BL24C64-C- add marking diagram Update ordering information Version 1.2 BL24C64-C- 7/21/2017 Update DC electrical characteristics information Modify the format Version 1.21 BL24C64-C- 7/26/2017 Update ordering information Version 1.22 BL24C64-C- 7/26/2017 Update Figure 6. Byte Write Version 1.23 BL24C64-C- 2/27/2018 Update the C characteristics Version 1.23 BL24C64-C- 3/13/2018 Update the C characteristics Update the absolute maximum stress ratings note1. BL24C64 64Kbits (8,192 8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 2016 Belling ll ights eserved

The BL24C128A provides 131,072 bits of serial electrically erasable and programmable read-only

The BL24C128A provides 131,072 bits of serial electrically erasable and programmable read-only Features Compatible with all data transfer protocol 1 MHz 400 khz 100 khz Memory array: 128 Kbit (16 Kbytes) of POM Page size: 64 bytes dditional Write lockable page ingle supply voltage and high speed: