AEC-Q100G Qualification Summary

Transcription

1 AEC-Q100G Qualification Summary Objective: Pictus 256k New Product Introduction Qualification 100ld LQFP Freescale PN: MPC5602P Part Name: Pictus 256k Technology: 0.09um CMOS90 Z3 core Package: LQFP x14 x 1.4 Pitch 0.5 Fab / Assembly / FSL-ATMC / FSL-KLM-FM Final Test Sites: FSL-TJN-FM Maskset#: M22Y Rev#: 0 Die Size (in mm) x x W x L x T Part Operating Temp. Grade: 125 C Ta Grade 1 Customer Name(s): General Market PN(s): Design Engr: Christoph Patzelt Phone #: Product Engr: Moyra Peterson Phone #: Chris Sanderson Prod. Package Jin-Quan Wang Phone #: NPI PRQE: Douglas Blackwood Phone #: Trace/DateCode LOT 1 DD82200 QZAD1111A LOT 2 DD82482 QZAE1111A LOT 3 DD82756 QZAF1112A Summary Revision # Date: 1.3 8th March 2013 QUARTZ Tracking #: (Signature/Date shown below may be electronic) PPE Approval N/A Signature & Date: NPI PRQE Plan Approval Douglas Blackwood Signature & Date: 8th November 2011 CAB Approval M Signature & Date: Neil Ross 10th November 2011 STRESS TEST PC HAST Reference J=JESD22 Test Conditions (Surface Mount Devices Only - PC required for THB, HAST, AC, UHST, TC, PC+PTC) Preconditioning : A113 MSL 260 C, +5/-0 C J-STD-020 Pre and Post CSAM SS=11 units per lot per stress test A110 PC before HAST required for SMDs. Highly Accelerated Stress Test, Biased: HAST = 130 C/85%RH for 96 hrs. Bias = 5.5V TESTS HIGHLIGHTED IN YELLOW WERE PERFORMED FOR THIS STUDY This testing is performed by Freescale FSL-EKB, FSL-KLM, and FSL-TJN where noted in the GROUP A - ACCELERATED ENVIRONMENTAL STRESS TESTS End Point NA=Not Applicable RHC All surface mount devices prior to THB, HAST, AC, Pass by similarity UHST, TC, PC+PTC Generic Data Performed in TJN : Lot 1 0/231 Bolero 256k 100ld : Lot 2 0/231 Bolero 256k 100ld : Lot 3 0/231 Bolero 256k 100ld RH Pass by similarity Generic Data Performed in TJN : Lot 1 0/77 Bolero 256k 100ld : Lot 2 0/77 Bolero 256k 100ld : Lot 3 1/77 Bolero 256k 100ld [1] : Lot 3 0/77 Bolero 256k 100ld re-run AC TC PTC HTSL A102 PC before AC required for SMDs. Autoclave: AC = 121 C/100%RH/15 psig for 96 hrs PC before TC required for SMDs A104 Temperature Cycle: AEC Q100- TC = -65 C to 150 C for 500 cycles. Appendix 3 WBP after TC on 5 devices from 1 lot; 2 bonds per corner and one mid-bond per side on each device. Record which pins were used. A105 A105 A103 For SMD devices only. Preconditioning plus Power Temperture Cycle: Power Temperature Cycle: PTC =? C to? C for 1000 cycles; Bias =? High Temperature Storage Life: 150 C for 1008 hrs [1] see 8D, 1 fail for EOS R Pass by similarity Generic Data : Lot 1 0/77 Bolero 256k 100ld : Lot 2 0/77 Bolero 256k 100ld : Lot 3 0/77 Bolero 256k 100ld HC WBP =/> 3 grams Pass by similarity Generic Data : Lot 1 0/77 Bolero 256k 100ld : Lot 2 0/77 Bolero 256k 100ld : Lot 3 0/77 Bolero 256k 100ld All Post 500TC wirepulls >3g Low power device, not required. RH RH RHC Pass by similarity Generic Data See EDR data to cover this item TEST GROUP B - ACCELERATED LIFETIME SIMULATION TESTS HTOL A108 High Temperature Operating Life: Ta= 125 C for 1008, 2016hrs FIO Bias: Vdd = 5.0V nom : 6.0V Stress Vin, Vdd_bv = 3.3V nom : 3.6V Stress NVM C, as shown in EDR below, is required NVM in Checkerboard RHC Lot1: 0/77 (4048hrs) Lot2: 0/77 (1008hrs) Lot3: 0/77 (1008hrs) Generic Data Performed in TJN : Lot 1 0/77 Bolero 256k 100ld (1008hrs) NBTI Identify the speed pattern that drifts the most and create guardband if needed. (Two readpoints - Time zero and at final NBTI readpoint). Serialised units. RHC Lot1: 0/77 Lot2: 0/77 Lot3: 0/77 Performed in EKB ELFR AEC Q EDR AEC Q Early Life Failure Rate: Ta = 125 C for 48 hrs; Bias: Vdd = 5.0V nom : 6.0V Stress Vin, Vdd_bv = 3.3V nom : 3.6V Stress 10% of NVM C, as shown in EDR below, is required NVM in Checkerboard NVM Endurance, Data Retention, C-Flash: 256k 125 C (2x16k, 3x32k, 1x128k) 100K W/E for 16k block size 10K W/E for 32k block size 1K W/E for 128k block size D-Flash: 64Kb 125 C 100K W/E for 16k block size NVM in Checkerboard 504, 1008hrs, 2016hrs 150 C RHC Lot1: 0/400 Lot2: 0/400 RHC Lot1: 0/77 Lot2: 0/77 Lot3: 0/77 Generic Data Performed in EKB : Lot 1 0/800 Bolero 256k 100ld : Lot 1 0/787 Bolero 1.5M 176ld : Lot 1 0/813 Bolero 1.5M 144ld Performed in EKB NVM Endurance, Data Retention, C-Flash 0: 256k -40 C (2x16k, 3x32k, 1x128k) 100K W/E for 16k block size 10K W/E for 32k block size 1K W/E for 128k block size D-Flash: 64Kb -40 C 100K W/E for 16k block size NVM in Checkerboard 504, 1008hrs, 2016hrs 150 C RHC Lot1: 0/77 Lot2: 0/77 Lot3: 0/77 Performed in EKB FORMPPAP004XLS 1 of 3 Freescale Rev U

2 Freescale PN: MPC5602P Part Name: Pictus 256k Customer Name(s): General Market PN(s): Summary Revision # Date: 1.3 8th March 2013 TEST GROUP C - PACKAGE ASSEMBLY INTEGRITY TESTS WBS AEC Q Wire Bond shear Cpk = or > bonds from minimum 5 units 0 0 Pass by similarity Generic Data : Lot1 Cpk= 3.56 Bolero 256k performed on 100ld WBP MilStd Wire Bond Pull Cond. C or D Cpk = or > bonds from minimum 5 units 0 0 Pass by similarity Generic Data : Lot1 Cpk= 3.33 Bolero 256k performed on 100ld SD PD SBS B102 B100 AEC-Q Solderability; 8hr. Steam age (1 hr. for Au-plated leads) prior to test. If production burn-in is done, samples must also undergo burn-in. Physical Dimensions - PD per 98A drawing Solder Ball Shear; Performed on all solder ball mounted packages e.g. PBGA, Chip Scale, Micro Lead Frame (but NOT Flip Chip). Two 260 C reflow cycles before shear. >95% lead coverage of critical areas Pass by similarity Generic Data : Lot1 0/15 Bolero 256k performed on 100ld Cpk = or > Pass by similarity Generic Data : Bolero 256k performed on 100ld (w) (l) (h) Lot1: Cpk= Lot2: Cpk= Lot3: Cpk= Cpk = or > N/A, not required for leaded devices. (5 balls from a min. of 10 devices) LI B105 Lead Integrity Not required for surface mount devices; Only required for through-hole devices. No lead breakage or cracks (10 leads from each of 5 parts) N/A, not required for SM devices. TEST GROUP D - DIE FABRICATION RELIABILITY TESTS EM Electro Migration Derivative Device on qualified NBTI Negative Bias Temperature Instability Derivative Device on qualified TDDB Time Dependent Dielectric Breakdown Derivative Device on qualified HCI Hot Carrier Injection Derivative Device on qualified SM Stress Migration Derivative Device on qualified TEST GROUP E - ELECTRICAL VERIFICATION TESTS TEST Freescale 48A Pre- and Post Functional / Parametrics Test software shall meet requirements of AEC-Q Testing performed to the limits of device specification in temperature and limit value. 0 Fails All All All Lot1: DD82200 Lot2: DD82482 Lot3: DD82756 ESD AEC-Q100- ElectroStatic Discharge/ (HBM) CLASSIFICATION 002 Human Body Model Classification: 500 / 1000 / 1500 / 2000Volts See AEC-Q for classification levels. ESD AEC-Q100- ElectroStatic Discharge/ (MM) CLASSIFICATION 003 Machine Model Classification: 50 / 100 / 150 / 200Volts See AEC-Q for classification levels. ESD AEC-Q100- ElectroStatic Discharge/ (CDM) CLASSIFICATION 011 Charged Device Model Classification: 250 / 500 / 750 Volts See AEC-Q for classification levels. LU JESD78 Latch-up: plus Test per JEDEC JESD78 with the AEC-Q AEC-Q100- requirements. 004 Ta= Operating Temperature Maximum ED AEC-Q100- Electrical Distribution 009, Freescale FG AEC-Q CHAR AEC-Q003 Characterization: Performed on new technologies and part families. RH 2KV min. RH 250V min. RH Corner pins =/> 750V; All other pins =/> 500V 3 units per Voltage level 3 units per Voltage level 3 units per Voltage level 1 12 Lot1: 500V 0/3 1000V 0/3 1500V 0/3 2000V 0/ Lot1: 50V 0/3 100V 0/3 150V 0/3 200V 0/3 1 9 Lot1: 250V 0/3 500V 0/3 750V 0/3 RH Lot1: 0/6 RHC Cpk = or > 1.67 Fault Grading FG shall be = or > 90% for qual units Lot1: Pass Lot2: Pass Lot3: Pass Y 99% Y Pass Performed in EKB GL AEC-Q Electro-Thermally Induced Gate Leakage; 155 C, 2.0 min, +400/-400 V R Lot1: 0/6 FORMPPAP004XLS 2 of 3 Freescale Rev U

3 Freescale PN: MPC5602P Part Name: Pictus 256k EMC SAE Electromagnetic Compatibility J1752/3 - (see AEC Q100 Appendix 5 for test applicability; done on Radiated case-by-case basis per customer/freescale agreement) Emissions SC AEC Q SER Short Circuit Characterization Applicable to all smart power devices. This test and statistical evaluation (see section 4 of Q ) shall be performed per agreement between user and supplier on a case-by-case basis. JEDEC Unaccelerated: Applicable to devices with memory sizes 1Mbit SRAM or Soft Error Rate JESD89-1 DRAM based cells. Either test option (un-accelerated or or accelerated) can be performed, in accordance to the Accelerated: referenced specifications. This test and its accept criteria is JESD89-2 & performed per agreement between user and supplier on a JESD89-3 case-by-case basis. Final test report shall include detailed test facility location and altitude data. Customer Name(s): General Market PN(s): Summary Revision # Date: 1.3 8th March 2013 <40dBuV Pass Performed in ATX 150kHz - 1GHz Not applicable to microcontroller Not applicable to microcontroller with RAM < 1Mbit TEST GROUP F - DEFECT SCREENING TESTS PAT AEC Q001 Part Average Testing Has PAT been established for this part? SBA AEC Q002 Statistical Bin Analysis Has SBYA been established for this part? Implemented Implemented Generic Data: Quartz Device Mask Title Fab Assembly Mould Die Size CAB MPC5602P 1M18Y Bolero 256k 100ld NPI Qualification FSL-ATMC FSL-KLM SUMITOMO EME-G700E 3.778x3.411x0.33mm M MPC6507B 0M03Y Bolero 1.5M 176ld Qualification FSL-ATMC ASE-CL HITACHI CEL x5.301x0.33mm M MPC6507B 0M03Y Boler0 1.5M 144ld Qualification FSL-ATMC FSL-KLM SUMITOMO EME-G700E 5.082x5.301x0.33mm M Revision Revision Date Description th May 2009 Original issue Douglas Blackwood th April 2011 Updated Spec cycling requirements Douglas Blackwood 1.2 8th November 2011 Added results Douglas Blackwood 1.3 8th March 2013 Updated format for Web publishing Douglas Blackwood FORMPPAP004XLS 3 of 3 Freescale Rev U

4 Freescale 8D Report 8D Header 8D Title 8D Abstract SPC5602D (Bolero 256K 100ld Package qualification ) Post HAST Short Circuit fail One unit from lot (DD86284) of Bolero 256K 100ld package submitted to HAST has failed at post stress testing on J750 ATE. The unit showed to have pins P10 (PE9) and P11 (PE10) shorted together and to Pin15 (Vdd_HV). Corrective action # C.A. Status CLOSED Creation Date 21-OCT-2011 Incident # a ICAP FIUO Point of Failure HAST Freescale Part# SPC5602DMLL4 Part Common Name BOLERO 256K D1 Team Description Name Location Function Role Bruce Robertson East Kilbride Product Engineering Manager Team Member Douglas Blackwood East Kilbride NPI Quality Team Leader Allan Scott East Kilbride Product/Test Engineering Team Member Elton Osmani East Kilbride Product Engineering Team Member Jason Goertz Austin Product Analysis Engineer Team Member Navin Kumar KLM Reliability Engineer Team Member

5 D2 Problem Description Problem Description During the 100ld package qualification one unit failed continuity on the J750 test system during post HAST stress testing. Further testing showed that the fail was a short circuit between Pins 10 and 11 of the 100ld package. The failure was verified using the J750 test system interfaced with the 100ld Final Test hardware and using the Final Test qualification test program, testing was confirmed at ambient temperature using both handler and hand test sockets. Further verification was carried out on the bench using a standard multi-meter set on resistance measurement. Dut 1 recorded as : ECID W8X29Y33 Further analysis by Product analysis confirmed that there was a low ohmic reading between the two pins and VDD_HV. Full details of finding and subsequent findings listed below. D3 Containment (Interim Containment Action ICA) Containment Final Test results showed that there was a short circuit between Pin 9 and Pin 10 of the 100ld package and VDD_HV. As continuity is at the very start of the test flow and is included in every insertion then this fail was detected at the first test insertion. QRA Test data log of failing device showed fail to a group of pins in continuity then subsequent fail to specific pins in continuity, JVT, and DPS checks FAIL Cont_Fct_Vdd cont_func_vdd_no_oscin FAIL Cont_Fct_Vdd cont_func_vdd_no_oscout FAIL Cont_Fct_Sh_Vdd cont_func_vdd_short_no_oscin FAIL Cont_Fct_Sh_Vdd cont_func_vdd_short_no_oscout FAIL Cont_Sh_Dc_Vdd PAD_ FAIL Cont_Sh_Dc_Vdd PAD_ FAIL DPS_HV_Chk VDD_HV_Main ua FAIL JVT_SLOW_POS PAD_ FAIL JVT_SLOW_POS PAD_ FAIL JVT_SLOW_NEG PAD_ FAIL JVT_SLOW_NEG PAD_74 Post Stress testing has contained and highlighted these as fails therefore containment is part of the existing test flow and no changes are necessary. This product is in qualification with no production parts shipped that require to be contained.

6 D4 Root Cause and Escape Point Root Cause Root cause for this failing unit is very difficult to ascertain, Product Analysis has concluded that an EOS event took place but the actual source and cause of EOS has not been established. Trace history of the part shows that it has been through all test flows and only fails at the test insertion immediately following HAST. QRA Testing of device at T0 completed in Final Test in TJN shows that the part was a bin 1 and therefore has passed continuity and relevant JVT DPS tests PASS Cont_Fct_Vdd cont_func_vdd_no_oscin PASS Cont_Fct_Vdd cont_func_vdd_no_oscout PASS DPS_HV_Chk PASS JVT_SLOW_POS PAD_ PASS JVT_SLOW_POS PAD_ PASS JVT_SLOW_NEG PAD_ PASS JVT_SLOW_NEG PAD_74 Parts completed HAST in KLM and subsequently failed continuity at the first final test (QRA) insertion. Product Analysis confirmed leakage between the pins 10, 11, & 15 and VSS as reported by test. PA carried out an x-ray looking for possible internal shorts but this did not show any defects. CSAM was carried out on the part to highlight any voiding in the mould compound that could provide a path for moisture ingression, no anomalies were detected The part was flat-sectioned from the top of the package until the wires were severed to just above the ball bonds. It was confirmed that the short is on the die side only and not the package side. The unit was then deprocessed and evidence of EOS was observed at the pins which showed the failing condition: The images below show EOS around the failing pins. Fig1: Low magnification image of pad damage

7 Fig2: SEM image showing EOS damage Fig3: SEM image showing cross section through EOS damage PA provided multiple cross sections through the damage area; however, no root cause was identifiable in the analysis. Occur Point Hardware: HAST Board used to stress the units were inspected prior to use for signs of wear and poor socket condition, following stress the same inspection was performed looking for degradation of the boards no issues were detected. Human Error: To rule out the possibility of an orientation issues during loading of the HAST boards an experiment was performed to rotate units in the board through all combinations; this was repeated twice. Although the positioning of the devices in the sockets meant incorrect voltages on the pins, PE were not able to replicate the EOS damage and all units passed full production test afterwards.

8 Design: A review, performed by both Freescale and ST Design Engineers, did not show any concerns on either the port pins damaged in terms of weakness, design fault, or with the Bias used during stress. The pads in question are identical to those used in Bolero 1.5M. Currently there are in excess of 229k units in the field with no returns for EOS on these 2 pins; Device Qty BOLERO_1.5M Escape Point As the part was proven to be a pass unit post preconditioning, the unit in question was found to fail at the first read point following the stress in which the EOS occurred, and as such, did not escape the test/stress flow. D5 Permanent Corrective Action Corrective Actions Due to the nature of this failure, corrective actions for this particular event are difficult to define; root cause of the leakage fails has not been established. As such, the team cannot implement corrective actions at this time. D6 Validate Corrective Action Validation A further sample of 77 units from the same lot were processed through the same stress flow (MSL C followed by 96hrs HAST) with each part uniquely identified in the HAST socket however no issues were seen and all units passed full production test program. D7 Prevent Recurrence Prevent Recurrence Action to prevent recurrence at this time cannot be implemented as root cause of the failure is unknown. D8 Recognise Team Recognition Although no root cause was identified, the team investigating the unit put in a significant effort and were thanked for their time.