SDP Biased Series - SOT23-6

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SDP Biased Series - SOT23-6 RoHS Pb e3 Description This new SDP Biased series provides overvoltage protection for applications such as VDSL2, ADSL2, and ADSL2+ with minimal effect on data signals.

1 SDP Biased Series - SOT23-6 RoHS Pb e3 Description This new SDP Biased series provides overvoltage protection for applications such as VDSL2, ADSL2, and ADSL2+ with minimal effect on data signals. This silicon design innovation results in a capacitive loading characteristic that is compatible with these high bandwidth applications. This surface mount SOT23-6 package provides a surge capability that exceeds most worldwide standards and recommendations for lightning surge withstand capability of tertiary protectors. Features & Benefits Agency Approvals Agency Agency File Number E Pinout Designation & Schematic Symbol Compatible with VDSL2 (30MHz Balanced overvoltage protection Low distortion Low insertion loss Low profile Response time under 500ns 2nd level interconnect is Pb-free per IPC/JEDEC J-STD-609A.01 Applicable Global Standards 1 6 ANSI C62.1 IEC IEC level -- 15kV (air discharge IEC , 30A -- 8kV ( contact discharge 2 5 (t P =8/20μs 3 Absolute Maximum Ratings between pin1 and pin 3, Ta= 25ºC (Unless otherwise noted Part Number Marking 1. The device must be in thermal equilibrium at 25ºC Maximum Junction Temperature Storage Temperature Range I pp 8/20µs ºC ºC A Max SDP020T023G6RP P to Electrical Characteristics between pin 1 and pin 3, Ta = 25 C Part Number Marking V DRM =100nA I DRM =19V V I H I S Co@f=1MHz,2V Delta Co@ Line Bias = 1 V to 19 V V min pa typ V max ma typ ma min pf max pf max SDP020T023G6RP P

2 V-I: Characteristics Typical capacitance against line voltage (without external bias 2.0 Capacitance (pf Voltage (Volt Surge Ratings I PP Series 1.2/50µs 1 / 8/20µs 2 A min G 30 1 Voltage waveform in µs 2 Current waveform in µs - Peak pulse current rating (I PP is repetitive and guaranteed for the life of the product. - The device must be in thermal equilibrium at 25 C. Thermal Information Parameter Storage Temperature Range Maximum Junction Temperature Maximum Lead Temperature (Soldering 10s Rating -65 to Units 2

Normalized V S Change vs. Junction Temperature Normalized Holding Current vs. Case Temperature Percent of VS Change % 1.08 1.06 1.0 1.02 1.00 0.98 0.

3 Normalized V S Change vs. Junction Temperature Normalized Holding Current vs. Case Temperature Percent of VS Change % Junction Temperature (TJ C Normalized I H Case Temperature ºC Soldering Parameters Reflow Condition Pb-Free assembly - Temperature Min (T s(min 150 C Pre Heat - Temperature Max (T s(max 200 C - Time (Min to Max (t s secs. Average ramp up rate (Liquidus Temp (T L to peak 3 C/sec. Max. T S(max to T L - Ramp-up Rate 3 C/sec. Max. Reflow - Temperature (T L (Liquidus +217 C - Temperature (t L secs. Peak Temp (T P 250(+0/-5 C Time within 5 C of actual Peak Temp (t p 20-0 secs. Ramp-down Rate 6 C/sec. Max. Time 25 C to Peak Temp (T P 8 min. Max. Do not exceed 260 C 3

4 Physical Specifications Environmental Specifications Lead Plating Lead Material Lead Coplanarity Subsitute Material Body Material Flammability SOT23: Matte Tin Copper Alloy inches (0.102mm Silicon Molded Epoxy UL9-V-0 1. All dimensions are in millimeters. 2. Dimensions include solder plating. 3. Dimensions are exclusive of mold flash & metal burr.. All specifications comply to JEDEC MO Blo is facing up for mold and facing down for trim/form, i.e. reverse trim/form. 6. Package surface matte tine Temp Cycling Bias Humidity Pressure Cooker High Temp Storage HTRB Thermal Shock C-SAM Wet Humidity (Tin only Mil-STD-883F, Method Condition C, -65 C to +150 C JESD 22-A101-B 85 C, 85 CRH. 50V JEDEC 22-A102C No Bias, 121 C, 100%RH 96Hrs/192Hrs. JESD 22-A103C Con B. 150 C, no bias 1000Hrs JESD C Mil-STD-883F, Method Condition A, 0 C to 100 C As per flow, JSTD-020C pre&post preconditioning test. JESD 201A standard: 55 C/85%RH Dimensions - SOT23-6 Recommended Solder Pad Layout M P R O Dimensions Inches Millimeters Min Max Min Max A A A b C D E E e (BSC (BSC e L (note N (note C 10 C 0 C 10 C M O P R Dimensioning and tolearances per ANSI 1.5M Package conforms to EIAJ SC-7 ( Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs.. Foot lenth L measured at reference to seatng plane. 5. L is the length of flat foot surface for soldering to substrate. 6. N is the number of terminal positions. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

5 Part Numbering Part Marking SDP 02 0 T023 G 6 RP Type SIDACtor DSL Protector Nominal Working voltage: Reel Pack Number of pins Surge Ipp rating 6 5 P2 Part Marking Code Construction variable: 0=single chip Package Type Packing Options Package Type Description Quantity SOT23-6 Tape and Reel 3000 Embossed Carrier Tape & Reel Specification - SOT23-6 ACCESS HOLE 1.mm 1.5mm DIA. HOLE.0mm 2.0mm 1.75mm 13mm 8mm C L 180mm 60mm.0mm SOT-23 (8mm POCKET PITCH GENERAL INFORMATION PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-81 REVISION "A" SPECIFICATIONS. 8.mm USER DIRECTION OF FEED PIN 1 COVER TAPE 5

Low Capacitance ESD Protection - SP3002 Series. Description. Features I/O 4 I/O 3. Applications

Low Capacitance ESD Protection - SP3002 Series. Description. Features I/O 4 I/O 3. Applications SP3002 Series 0.85pF Diode Array RoHS Pb GREEN Description The SP3002 has ultra low capacitance rail-to-rail diodes with an additional zener diode fabricated in a proprietary silicon avalanche technology