ESD Protection by Design of Chips and Microcircuits

Transcription

1 AppendixA ESD Protection by Design of Chips and Microcircuits The drastic reduction in area and thickness of the active elements that continuously occur in semiconductor technology makes each new IC family more prone to ESD damage than the former one. Technologies achieving more than 1000 gates/mm 2 and speed-power products much less than a picojoule, with propagation delays inferior to 30 ps, are reaching a gate oxide barrier that is so thin that its theoretical breakdown voltage is in the 15- to 20-V range. Designers of integrated circuits, hybrids, and microelectronics in general can build in a certain level of ESD hardening through layout precautions and integrated protection networks. This hardening will make the wafers, chips, and encapsulated modules safer to handle and will relieve the end user of some of the cost and burden of basic protection. Eventually, if required by especially harsh applications, complementary hardening can be added at PCB or equipment level. The following guidelines are in no way a treatise on the subject, which is amply covered by the abundant literature available throughout the IC community. And whatever the hard-bound volume that would give minute details of on-chip ESD protection networks, it would soon be outdated by the ceaseless progress in the IC technology and manufacturing processes. Construction details that were successful for one technology are not necessarily transferable to the next one. We have tried to mention only the basic protection principles that will probably remain true, whatever the integration scale. Some of the following have been inspired by the remarkable analysis of Beebe (1), Sicard et al. (2), the Military Handbook DOD 263 (3), plus some Application Notes by Texas Instruments or National Semiconductor (4 6). Electrostatic Discharge, Third Edition, by Michel Mardiguian Copyright 2009 the Institute of Electrical and Electronics Engineers, Inc. 240

2 A.1. Functions Provided by On-Chip ESD Protection Strategy 241 A.1. FUNCTIONS PROVIDED BY ON-CHIP ESD PROTECTION STRATEGY These functions are multiple, challenging, and often contradictory, therefore trade-offs have to be made. The protection techniques must: Provide a low-resistance shunting path for preventing the discharge current from reaching the sensitive parts inside the chip (risk of damage by joule effect), yet appear as a high impedance for normal signals. Keep the transient voltage at the stressed pin below the gate oxide damage level of 1 kv/ μm. Be fast acting (<1 ns)andself-resettable. Be able to withstand repeated discharges with both polarities, without significant changes in their protection level and reliability. If damaged, appear as a nonexisting device, thus maintaining the functionality of the IC. Keep their protection characteristics whether the IC is powered or not. Keep their high-impedance off-state when the IC is not powered. This is an important aspect in certain bus-type applications where one subscriber card can be temporarily off, while the rest of the system is active. A protection that would set itself in a conduction state when a signal is coming in, while V cc is turned off, could disturb an entire bus or local area network (LAN). Preserve the signal integrity and all the functional features such as: Input resistance and capacitance Slew rate, signal-to-noise, and distorsion (SINAD), sensitivity threshold for analog inputs Fan-out, V IL max,v OL max,v IH min, and V OH min, noise margin Transient current demand at switching, leakage current Input symmetry with differential drivers/receivers such as LVDS, IEEE1394 Do not create, or aggravate, because of nonlinearity, some undesired, non-esd, EMI problems such as RF detection/demodulation (7), skew, and the like. Do not interfere with voltage translators used for transition between the low-voltage core circuits and the higher voltage I/O circuits of the IC. The above list represents 10 constraints for a protection network, with some of them not easy to reconcile. In addition to these primary considerations, the design should reduce the risk of ESD overstress and damage by applying certain precautions regarding layout, clearances, and current densities. It should also, if possible, ensure, or participate in, latch-up protection.

3 242 Appendix A ESD Protection by Design of Chips and Microcircuits A.2. PRINCIPAL COMPONENTS USED FOR ON-CHIP ESD PROTECTION Most of the following considerations address not only protection performance, but also the ESD survival of the protection device itself. Resistors On-chip series resistors are used, with values ranging from 50 to 2000 depending on the application. Polysilicon resistors, embedded in the Si0 2 can withstand high voltages, but at the expense of a mediocre current handling capability (poor thermal dissipation). On the contrary, diffused N well resistors have better current handling, but mediocre voltage withstanding, with breakdown occurring between N well and P substrate. For input protection, resistances are generally used. For output protection, lesser values are used, if at all, because they rapidly affect the fan-out capability, and the V out LOW (VOL), V out HIGH (VOH) (hence the noise margin). These resistors are often invoked as current-limiting components; however, the HBM model with its source resistance is basically a current source, and it is obvious that hardly cause a current reduction. In fact, resistances can only be current limiters for the MM (machine model) or CDM cases; they essentially serve as voltage dividers between the first clamp at the input pad and the internal core circuits, in case of cascaded protections. They can also slightly increase the ESD pulse rise time, giving more time for a protection diode to react. Diodes Diffused diodes are arranged in several rows of multiple contacts (10 20) for better current handling. They generally have reverse breakdown voltages in the 25- to 60-V range. When forward-biased by a positive pulse with V in >V cc + V d, the upper diode D 1 will derive the input current into the V + line (Fig. A.1). When driven by a negative pulse (V in <V ss V d), lower diode D 2 will allow the current to close out by the V ss /D 2 /input lead loop. When the IC is not connected, D 2 performs by its reverse breakdown. Few disadvantages of the diode solution are associated with its parasitic capacitance and its slow reaction time. In reverse breakdown mode, its clamp voltage can be higher that what the smallest, submicron technologies can withstand. Also, with smaller and smaller technologies, the dynamic resistance of the diode (typically 20 for a μm junction area) is too high for an adequate protection of the most sensitive chip circuits: in μm technology rules, the thin gate oxide cannot stand more than 12 V. Increasing the diode area would be feasible, but at the expense of a capacitance increase, which is rapidly playing against the I/O circuits speed.

4 A.2. Principal Components Used for On-Chip ESD Protection 243 V DD V DD Pad R To gate R To gate (a) Diodes V SS (d) Transistors V SS Distributed V DD R To gate R (b) Distributed diodes To gate V SS V SS (e) Transistor Bilateral Devices R To gate Arc gap R V DD To gate V SS V SS (c) Zener diodes (f) Spark gap and diodes I ΔI ΔV R dyn. = ΔV ΔI ON "Set" voltage Trig. V Figure A.1 Some basic input protection networks. The spark-gap (f) is made by toothed metallization patterns, and usually put up front to evacuate the bulk of the incident energy. Lower sketch shows the crowbar behavior of a MOS transistor above its avalanche point.

5 244 Appendix A ESD Protection by Design of Chips and Microcircuits Transistors as Crowbar Devices With MOS transistors used as triggered short-circuit switches, the interest lies in the fact that these devices already exist in the standard chip-processing library. In normal operation, the protection MOS is off. With an ESD pulse, the drain substrate junction is driven into reverse breakdown and turns the device into a snap-back or crowbar mode (sometimes viewed as the solid-state equivalent of a gas discharge tube), whereas the protection behaves temporarily as a short, making it more efficient and less prone to thermal damage. This snap-back is attributed to the turn-on of the lateral parasitic bipolar transistor formed by the drain/channel/source (1). Another advantage is that the two CMOSs perform equally well against positive or negative pulses, hence making a bidirectional protection. The output protection, based on a similar scheme, consists in simply using the regular output CMOS transistor pair to act as crowbar protection, when needed. Zener Diodes Instead of regular diodes, zener diodes can also be integrated in the I/O area of a chip. They have the advantage of a more precise breakdown voltage, which allows an optimized coordination with other protection components such as resistance + crowbar scheme. Such a combination is used in ICs intended for environments with severe ESD and EFT (electrical fast transients). A.3. TYPICAL ESD PROTECTION NETWORKS Various assemblies of the resistor, diode, and transistor components are used. The protection afforded by these specific circuits is limited to a maximum current/voltage/pulsewidth combination. ESD pulses beyond these limits can degrade the protected IC, or the protection network itself. It can also result in a noncatastrophic fatigue of the IC or its protection, affecting its lifetime, a problem known as latent failures or walking wounded, since the loss of protection circuit may not be apparent after an ESD. Protection networks aredesigned to faceall realistic discharge configurations, but not to complicate and encumber the layout with improbable occurrences. For instance, although it would not be a totally impossible event, an ESD between two adjacent pins is generally not covered by protection networks. It is assumed, and confirmed by the tests, that in such cases, the discharge will still find a path further inside the device and meet a line-to-ground protection network. Referring to the HBM test, sometimes referred to as human skin model or bare-hand model, which is less severe (100 pf/1500 ), and thanks to the protective networks integrated by IC manufacturers, typical failure thresholds have been raised from 2 kv (i.e., a 1.3-A short-circuit current) in the early 1980s to about 6 kv (4 A) in the late 1990s.

6 A.4. Some Design Precautions to Improve ESD Immunity of ICs 245 Typically, an ESD test will stress: All pins vs. all power and ground pins. Power supply pins vs. ground pins. In addition, I/O pins dedicated to external functions (hence susceptible to being connected to long external cables) may be stressed vs. other I/O pins. Figures A.2 A.5 show some examples of ESD protection networks used by current IC manufacturers. As technologies and fabrication techniques evolve, design philosophies and circuitry are evolving too, bringing more refinements in protection networks. Many elements of these networks are using parasitic transistors and diodes created as a by-product of the process. A.4. SOME DESIGN PRECAUTIONS TO IMPROVE ESD IMMUNITY OF ICS The following is a brief sample of techniques commonly used by IC manufacturers: 1. Avoid as much as possible cross-unders beneath metal leads connected to I/O pins. When cross-unders are diffused during the N + (emitter) diffusion process, the oxide over the diffusion will be thinner, reducing the breakdown voltage in this area. Deep N diffusion should be used for cross unders, if the process has such a phase. 2. Protection circuits should be analyzed to see if the layout permits the protection diodes to be defective or blown without causing the IC to become inoperative. 3. Linear IC capacitors should be paralleled by a PN junction with sufficiently low breakdown voltage. 4. Avoid high-energy density spots in a PN junction depletion region, under ESD conditions. Use parallel elements and multifingered contacts, or enlarge the junction. For instance, Input 120 Ω Poly - Si Failure 120 Ω Poly - Si Figure A.2 Standard HCMOS input protection network. Typical cumulative figures for ESD/HBM failures are: 2050 V (1% defects) to 2700 V (50% defects). More recent processes tend to abandon the poly-si resistors for the less fragile diffused resistors.

7 246 Appendix A ESD Protection by Design of Chips and Microcircuits Input pin To gates D1 D3 Output pin D2 D1 and D± are parasitic diodes Figure A.3 High-speed CMOS input and output protection used by Texas Instruments and providing a typical ESD/HBM immunity of 4500 V. The input diode becomes forward-biased for positive pulses exceeding V cc V. For negative pulses, the base of the diffused transistor becomes more positive than the input line, turning the transistor ON. IN ALVC OUT Figure A.4 ESD protection circuit in advance low-voltage CMOS (ALVC) used by Texas Instruments. IN Substrate resist. LVTTL OUT Figure A.5 Example of cascaded input protection in bipolar low-voltage IC, using a combination of crowbar transistors and a limiting resistor. The output transistors are powerful enough, so no additional protection components are needed.

8 A.5. The Latch-Up Problem 247 a. When scaling down by a k factor, going down from 1 to 0.1 μm, it is possible to apply a lesser scaling factor, such as k for the chip periphery where I/O pads and protection components are located. b. While keeping the benefits of downscaling for the chip core, the I/O pads and protection components can be arranged in a double ring, with staggered pads such as the occupied real estate is optimized. c. The effective dissipation area and contact area of the protection networkscanbeartificiallyimprovedbyusing slotted traces, multifingered shapes, and multiple contacts for diodes. 5. Avoid pin layout that put critical pins in corners since they are more prone to occasional contact. 6. Avoid as much as possible metallization crossovers because these areas are separated by thinner dielectric layers. In addition, crossovers often impose metallurgical requirements with conflicting constraints and cause ESD weak spots. Although the protection efficiency of these techniques can be tested through the standard HBM, MM, and CDM tests (see Chapter 3), the transmission line pulse (TLP), a more recent design and validation tool can be used: A calibrated square pulse is injected into the tested device via an RF-quality jig, using precision-etched stripline. By varying the pulse amplitude and duration, more insight is obtained for critical failure parameters of each IC pin, including I,V curves and mismatch. It has also the advantage of capturing many critical parameters without overstressing the device. It is also easily simulated by sofware tools such as SPICE, and its results are correlatable to those of a real HBM or CDM pulse with equivalent (current time) area. A.5. THE LATCH-UP PROBLEM Although it is not unique to CMOS circuits, one example of a latch-up situation is shown in Figure A.6. Most CMOS devices have one PNP and one NPN lateral parasitic bipolar transistor, resulting from the embedded ESD protection diodes. Being sufficiently close, they form a parasitic silicon-controlled rectifier (SCR). When one of the PN juction is forward biased, such as with an overvoltage exceeding (V cc V), it supplies enough current to drive the other transistor into saturation. Provided that the product of the two gains is >1, and that the current exceeds the SCR hold current, this onset of a quasi-short circuit between V cc and ground can last indefinitely after the pulse is gone. It may end up in IC destruction, if the current is not limited. Such inadvertent firing can be prevented by: Guard rings alternatively connected to V cc and ground. Increasing the separation between the PN diode and the N well of the active device, thus reducing the gain of the lateral NPN parasitic transistor.

9 248 Appendix A ESD Protection by Design of Chips and Microcircuits Input P channel output Output Ground N channel output Ground P+ P+ N+ P N+ N+ N substrate P well P channel gate output N substrate resistance P well resistance N channel and P channel outputs are connected together N channel gate output Figure A.6 (Top) Cross section of a typical CMOS inverter showing the parasitic bipolar transistors. (Bottom) These parasitic transistors are naturally configured as a SCR. A.6. COMPARING STRESSES OF HUMAN BODY, MACHINE, AND CHARGED DEVICE MODELS, AND IEC 61, DISCHARGE Although the HBM test criteria is the most frequently invoked in the vendors electrical characteristics of ICs, others test models are progressively introduced (see Chapter 3), corresponding to other-than-human events. Some manufacturers have also undertaken the challenge of offering a full IEC test level 4 compliance at the IC level, thus making life easier for the equipment designer, who is released from the need of additional protection components. The latter is especially true for bus drivers/receivers intended for telecommunications and data transmission in severe environments. The following calculations are comparing the respective stresses of the above-mentionned test models, as seen by the protection components integrated

10 Comparing Stresses of Human Body 249 Table A.1 Comparison between Respective Parameters for HBM, MM, CDM, and IEC Test Pulses ESD Test C d Discharge Z dyn RC or Ringing Minimum Network Frequency Requirement HBM 100 pf ns 2 kv (1.33 A) MM 200 pf μh MHz 400 V (7 A) CDM 10 pf nh MHz 500 V (8 A) IEC 150 pf a 50 ns 2 kv (4 A) b a This impedance is due to the RLC circuit of the IEC, whose resistance R d, combined with the self-inductance of the simulator 2-m ground strap is just above the critical damping. b This current correspond to the second hump of the hand/metal discharge IEC waveform, that is, the energetic portion of the pulse (see Chapter 4). The initail ultrashort 7.5 spike has been neglected for this comparison. into the chip. TableA. 1 shows the basic parameters for comparing four standard ESD test pulses. The third column gives the discharge network impedance for each model. For the CDM, a 1- default resistor has been entered since no other resistor than the test jig wiring and contacts is specified, the discharge resistance being simply that of the device under test, pin-to-pin. The fourth column gives the total impedance of the discharging network, in short-circuit condition. For the HBM and the IEC, the source resistance R d is such that it forces a unipolar, overdamped pulse. For the MM and CDM, the L,C values are causing a ringing pulse with a corresponding dynamic impedance Z d, such that the pulser is a voltage source for all loads <Z d. The last column is indicative of a minimum voltage requirement for each test, along with the corresponding short-circuit current. In principle, with a single pulse, it is the energy that is important for a parametric degradation or hard failure. Power is not a relevant figure because it only relates to the instantaneous peak power. For instance, let us assume a CMOS input protected by a 300- series resistance. For an HBM test with 2 kv, the peak current will be 2000 I p = = 1.1 A P(peak) = Ri 2 = 300i 2 = 360 W Energy = P t average = 360(0.5RC) = 360( ns) = 27 μj With one ESD pulse/second, the average power is W F = 27 μw, which is extremely low because the duty cycle is also extremely low. Yet, 27 μj is about 10 times what an IC-embedded component can tolerate. The next comparison, in TableA. 2, is an attempt to evaluate the respective energy threats of the four types of ESD pulses, whose amplitudes have been choosen as having approximately the same risk of occurrence (a relatively common risk, in that case). It was assumed that the full pulse current was delivered

11 250 Appendix A ESD Protection by Design of Chips and Microcircuits Table A.2 Comparison of Energies Delivered by Four Standard ESD Tests for Moderate Severity Level HBM/2 kv MM/400 V CDM/500 V IEC (hand/metal)/2 kv 10 / / / /300 I peak 1.3 A/1.1 A 7 A/1.27 A 7.9 A/1.66 A 4 A/3 A W 1.3 μj/33 μj 8.5 μj/15 μj 1.2 μj/1.2 μj 4 μj/130 μj 1.3 A HBM, 2 kv 1.1 A RC 150 ns M.M., 400 V 7 A 1.1 A 50% 25 ns 180 ns 60 ns 7.7 A 3 ns CDM, 500 V 1.4 A 3 ns 30 ns Into 10 Ω load Into 300 Ω Into 10 Ω load Into 300 Ω Into 10 Ω load Into 300 Ω IEC (2 kv) 4 A 60 ns 3 A 90 ns Into 10 Ω load Into 300 Ω Figure A.7 Discharge current waveforms for the scenarios of TableA. 2. into two sorts of protection components: a 300- series resistor or a 10- shunt resistor, typical of the ON resistance of a clamping diode. Notice that depending on the load, high Z or low Z, the same test may behave as a voltage or a current source. Such extreme load variation also has an impact on the pulse duration, hence on the energy delivered. (See Fig. A.7.) The bottom line of the comparison is that for a 300- protection resistor, the IEC is by far the biggest threat, followed by the HBM. With the 10- load, it is the machine model that causes the highest energy, followed by the IEC. One should notice, however, that the CDM discharge into 10 delivers the highest current of all. Although the duration of this current is extremely short, its impulsive nature corresponds to the highest di/dt derivative, creating a thermal shock that can be more damaging than the other tests. REFERENCES 1. Beebe, S. G. Characterization, Modeling and Design of ESD Protection Circuits. SemiConductor Research Corp. T.R., 94SJ116, 1998.

12 References Sicard, E., and Bendhia, S. Advanced CMOS Cell Design. McGraw-Hill, New York, Military Handbook DOD-263. ESD Control Hand Book for Protection of Electrical & Electronic Equipment. 4. Design Considerations for Logic Products. Texas Instruments Application Notes, National Semiconductor. Application Note AN Diep, T., and Durvury, C. ElectroStatic Discharge. T. I. Application Report SSYA 010, Jan., Chun, J-H., and Murmann, B. Analysis & Measurements of Signal Distorsion Due to ESD Protection Circuits. IEEE Journal on Solid State Circuits, Oct., 2006.