ESD 충북대학교 전자정보대학 김영석

Transcription

1 ESD 충북대학교

2 ElectroStatic Charge Generation When 2 Surfaces in Contact then Separate Some Atom Electrons Move Causing Imbalance One Surface Has Positive Charge & One Surface Has Negative Charge 2

3 ESD Theory Triboelectric( 마찰전기 ) charging happens when 2 materials come in contact and then separated An ESD event occurs when the stored charge is discharged 3

4 Lightning Zap from a Door ESD Examples 4

5 ElectroStatic Discharge Charges Seek Balance Discharge is Rapid Creating Heat 5

6 Two Types of Materials: Conductors Electrical Current Flows Easily So Can be Grounded Can Discharge Examples: Metals and People 6

7 Two Types of Materials: Insulators Electrical Current Does Not Flow Easily Cannot be Grounded Example: Plastics Typically very high h charging 7

8 Static Voltages Walking across a carpet: 1,500-35,000 volts Walking over untreated vinyl floor: ,000 volts Vinyl envelope used for work instructions: 600-7,000 volts Worker at a bench: 700-6,000 volts Unwinding regular tape: 9,000-15,000 volts 8

9 Electronic Component ESD Sensitivity People Discharge Frequently But To feel a Discharge it must be about 3,000 volts Human Body Model(HBM) ESD Class 0: Damage you can t feel: 0 to 199 Volts ESD Class 1: Damage you can t feel: 200 to 1,999 Volts ESD Class 2: Damage you might feel: 2,000 to 3,999 Volts ESD Class 3: Damage you can probably detect as spark with your own body: 4,000 to 15,999 Volts ESD That A Person Can t Feel Can Easily Damage Electronic Components 100 volts or less can damage components 9

10 ESD Test Methods Human Body Model (HBM) Representative of an ESD event between a Human and an Electronic Component Machine Model (MM) Simulates the ESD event when a Charged Machine discharges through a component Charged Device Model(CDM) When the component is charged and then discharges through a Pin. The Substrate becomes charged and discharges through a Pin 10

11 Human Body Model(HBM) Human Body Model (HBM) Human Body Model (HBM) consists of a Capacitor and a series Resistor: C =100pf, R=1500 Ohm (JEDEC JESD 22-A114 [2]) Requirements 2-4 kvolts Positive or negative discharge between any two pins V HBM R = 1.5 KΩ DUT C = 100 pf 9/28/

12 Human Body Model(HBM) Waveform Human Body Model (HBM) Waveform 10ns rise time typically (short) 2-10ns are allowed Peak current: Rule of Thumb: 1kV = 2/3 Ampere i peak = V HBM /1500 1kV i(t) t r = 2-10 nsec time 12

13 Machine Model(MM) Machine Model(MM) Machine Model (MM) consists of a Capacitor and no series Resistor: C=200pF (JEDEC JESD 22-A115 [11]) [Philips Standard: d C=200 pf, R=10-25 Ohm, L= µH 25 H] Requirements Volts Positive or negative discharge between any two pins L = μh V MM R < 8.5 Ω DUT C = 200 pf 9/28/

14 Machine Model(MM) Waveforms Machine Model(MM) Waveform stress is similar to HBM Oscillations due to setup parasitics MM and HBM failure modes are similiar ili Less reproducible than HBM VESD=0.1kV, Ipeak= A VESD=0.2kV, Ipeak= A VESD=0.3kV, Ipeak= A 14

15 Charged Device Model(CDM) Charged Device Model(CDM) Models an ESD event which occurs when a device acquires electrostatic charge and then touches a grounded object 15

16 Charged Device Model(CDM) Waveform CDM Waveform: Highly dependent on die size and package capacitance 500V with 4pF verification module t r <400psec, I p1 ~4.5A (Source: AEC-Q B) 011B) 16

17 ESD Protection Scheme Primary + Isolation + Secondary Element Primary Element(PE) Shunt All of Current during an ESD Event FOD(Field Oxide Device), SCR, NMOS, PN Diode Effectiveness of PE is determined by the SE Isolation Resistive Element Polysilicon, N+ Diffusion, N-well, Zener Diode Secondary Element(SE) Limit the Voltage or Current until the PD is Fully Operational Small Grounded d Gate MOS, Diode 17

18 ESD Protection Devices Non-breakdown Based Diodes BJT(Bipolar Junction Transistor) MOSFET Breakdown Based Area Efficient, But Hard to Design/predict TFO(Thick Field Oxide) SCR(Silicon Controlled Rectifier) PIPE(Punchthrough Induced Protection Element) LVSCR(Low Voltage SCR) Gate SCR(Gate Coupled SCR) GCNMOST(Gate Coupled NMOS) Bimodal SCR Spark Gap 9/28/

19 Two Operations BJT under ESD Conditions 1) Self-Triggering Operation B-C Reverse Bias => Breakdown (Bvcbo)=> Avalanche Generation of Carriers Electrons enter the Collector (Ic) Holes drift to the Base => B-E Forward Bias I-V Curve: Vt1, It1=Snap Trigger Voltage, Current Vsp=Snap Hold Voltage 19

20 BJT under ESD Conditions 2) External Triggering Operation Using External Current Source Low VCB Voltage << Bvcbo Vt1(External trigger) < Vt1(Self trigger): Desirable in ESD protection 20

21 MOSFET under ESD Conditions Thin Gate Oxides => Low Clamping Voltage Triggering by Parasitic Lateral BJT VD Increase => Avalanche, Electron-Hole Pair Generation Electrons go to the Drain (ID) Holes go to the Substrate (Base) (Isub) Isub => Forward Bias of B-E Junction of npn BJT (Vt1, It1) Electron Injection into the Substrate (Base) => VD Decrease, - Res Vsp 이후 : Conduction Modulation of Substrate 21

22 SCR(Silicon Controlled Rectifier) SCR(Silicon Controlled Rectifier) =Thyristor = PNP + NPN BJTs Anode=+, Cathode=GND => Reverse Bias n-well/p-well Junction => Avalanche Breakdown, => Electron to n-well (turn on pnp) Bias, Holes to p-well (turn on npn) Vh ~25V 2-5V, Vt ~ 20V 22

23 SCR Vtrigger (~20v) Reduction Desirable in ESD Protection N+ Diffusion in n-well edge : Vt ~ 15v Gate Oxide at n-well edge: Vt ~ 6-10V 23

24 Field Oxide Device(FOD) Thick Field Device, or FOD Feature Sizes from 3um to 1um Lateral BJT: Breakdown at the Drain Junction Drain Spacing(DS), Channel Length(L): Critical Parameters 24

25 FOD: Vt Reduction Trigger Voltage (Vt) Reduction (a) FOD without Gate (b) FOD with Metal Gate Shorted to the Drain (c) FOD using Polysilicon Gate Vt(a) > Vt(b) > Vt(c) 25

26 FOD: Design Parameters Trigger Voltage(Vt) vs Channel Length(L) Failure Voltage(HBM) vs Drain Spacing(DS) 26

27 FOD: Layout DS/ L: Critical DS /GR: Not Critical 27

28 NMOS (FPD) NMOS or FPD(Field-Plated Diode) or Gated-Diode FPD: Thin Oxide Devices (FOD: Thick Oxide Device) Good for Feature Size < 1um (FOD: 1um<L<3um) Gate Tied to the Ground 28

29 FPD: Performance Feature Size Dependency L>1um: Thick Oxide Device (FOD) is Better L<1um: Thin Oxide Device (FPD) is Better Silicide/Non-Silicidedid id d Non-Silicided is Better DCG(Drain Contact to Gate) Dependency 29

30 FPD: Summary Good for Submicron Device W ~ 200um L ~ Minimum Channel Length Drain Contact t to Gate ~ 6um Finger Length ~ 40 80um Number of Finger ~

31 Gate-Coupled NMOS(GCNMOS) VG>VTH for GCNMOS (VG=0 for FOD/FPD) Merits Lower Trigger Voltage (Vt) Uniform Turn-on of fallfi Fingers (VG=0: Nonuniform Turn-on => >ESD Failure) 31

32 GCNMOS: VG Dependency Gate Coupling : Lower the Avalanche Breakdown Voltage Vbr Vbr Minimum for VG ~ 1-2V 32

33 GCNMOS with FOD Gate of GCNMOS is connected to Ground Through the FOD NPN(GCNMOS) Turn-on, Vpad ~ 8V NPN Snapback, Vpad ~ 15V, I ~ 2A (R ~ 5Ohm) Turn-on FOD Discharge VG=0 Tr ~ 5-10ns: Enough for All the Fingers to Turn-on 33

34 GCNMOS with FOD: Performance Trigger Voltage (Gate Coupled) < Trigger Voltage (VG=0) Failure Voltage (Gate Coupled) > Failure Voltage (VG=0) All the Fingers are Turned-on (See Inset of the Fig) 34

35 Most Efficient/unit Area SCR SCR Action N-well/P-sub is Highly Reverse Biased =>Avalanche Breakdown Electron Current to N-well => E/B (P+ Anode/N-well) Forward Biased. Turn-on PNP in 1ns Holes from Emitter go to P-sub => Turn-on NPN Regenerative PNPN Action Low Impedance State: Vanode-cathode ~ 1-2V => Low Power Dissipation, i Improved ESD Performace 35

36 SCR: Trigger Voltage Main Design Parameter for Vt Spacing bet. Anode and N-well (X) P-sub Resistance (Rp) Typically, Vt ~ V Vt ~ 60-70V/um in Nonsalicided Process Vt ~ 40-50V/um in Salicided Process Higher Rp => Lower Vt 36

37 SCR: VT Reduction 1) MLSCR(Modified Lateral SCR) Include Highly Doped Region near the Surface Vt ~ 25V 37

38 SCR: VT Reduction 2) LVTSCR(Low Voltage Trigger SCR) MOS // SCR Avalanche in Drain Junction of MOS Holes in the Substrate t Turn-on NPN Electron Current (from N+ source) goes to N-well, Turn-on PNP Vt ~

39 References Basic ESD and I/O Design, S. Dabral and T. J. Maloney, Wiley,