ESD AND OVERVOLTAGE PROTECTION ISSUES IN MODERN IC TECHNOLOGY. Master of Science. VLSI and Embedded Systems

Transcription

1 ESD AND OVERVOLTAGE PROTECTION ISSUES IN MODERN IC TECHNOLOGY A Thesis submitted in partial fulfillment for the award of degree of Master of Science in VLSI and Embedded Systems Submitted by, Akshaykumar Salimath Under the Supervision of Prof. Satyam Mandavilli Centre for VLSI and Embedded Systems International Institute of Information Technology Hyderabad, India i

2 CERTIFICATE This is to certify that the thesis entitled ESD and Overvoltage Protection Issues in Modern IC Technology, that is being submitted by Mr. Akshaykumar Salimath ( ) to International Institute of Information Technology, Hyderabad in the partial fulfillment of requirements for the award of degree of Master of Science in VLSI and Embedded Systems is a record of bonafide research work carried out by him under my guidance and supervision. The contents embodied in this thesis have not been submitted to any other university or institute for the award of any degree or diploma. Date: Prof.Satyam Mandavilli Professor Centre for VLSI and Embedded Systems International Institute of Information Technology, Hyderabad India ii

3 ABSTRACT ESD AND OVERVOLTAGE PROTECTION ISSUES IN MODERN IC TECHNOLOGIES Akshaykumar Salimath Supervisor: Prof.Satyam Mandavilli The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more, sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD) and Overvoltage stress-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications performance, ICs still should comply with minimum standards of failure robustness in order to be commercially viable. Although the topic of IC Protection from ESD and Over voltage induced damages has received attention industry-wide, the design of robust protection structures and circuits remains challenging because the failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate protection against IC failures. This dissertation presents comprehensive design methodology for implementing on-chip ESD protection for LNA and a circuit design technique iii

4 to overcome Reliability issues in Mixed Voltage IOs. Firstly the various failure mechanisms in Integrated circuits is revised. In the next chapter, the ESD topic in the semiconductor industry is described, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approach is illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem associated with capacitive loading of ESD protection device in LNAs is addressed next. A better methodology for implementing greater level of ESD protection by making use of ON chip inductors is proposed. The passives used in the design of RF Receiver blocks also influence the ESD robustness of LNA. Inductors and capacitors in RF circuits can be implemented either ON chip or OFF chip. In earlier technologies where the passives used to be OFF chip the ESD immunity of the LNA was totally determined by the robustness of ESD protection device. However in modern RF ICs the focus is on full integration to reduce system cost and area. So the passives appear ON chip. In RF ESD Protection it is common practice where capacitors and inductors in the circuit used for matching and frequency selection, are used to tune out ESD frequencies. In a Cascode LNA with inductive degeneration where ON chip inductors are used they can be used for ESD protection. Two cases are considered. In the first case a common design practice where the ESD device is positioned at the gate of LNA is considered as shown in Figure 1.1 and it is shown that the level of ESD protection is very much limited as the frequency of operation increases. In the second case we shift the ESD device away from the gate of LNA and make use of ON chip inductors to enhance the level of ESD protection. This method also has been shown to that the advantage that the capacitive effects are reduced as we move away from the gate of LNA. iv

5 Consider the topology in Figure 1.1 (a).as the frequency increases the capacitive reactance decreases and the ESD device begin to shunt more signal power to the ground. With this topology around 5GHz frequency of operation the achievable level of ESD protection may be reduced to 500V HBM which leads to early failure of the circuit.the proposed methodology for providing ESD protection for LNA using ON chip inductors is shown in Figure1.1 (b).by shifting the ESD protection device away from the gate of LNA and towards antenna the capacitive effects are reduced which means that the degradation of power gain and noise figure is less for given ESD device size. Also the required matching of 50Ω for maximum power transfer can achieved by varying both gate inductor Lg and source inductor Ls providing higher degree of freedom. Also the presence of gate inductor suppress steep current transients. With the proposed methodology upto 4KV HBM ESD protection is shown to be possible without much degrading the LNA performance parameters where as with the existing approach maximum protection of 2KV HBM was possible at 2.1GHz. The analysis is validated by simulation for 2.1GHz LNA with ON chip Spiral inductors and ESD protection in Cadence Design Suite using IBM CSOI7TF 180nm RF Technology. v

6 The Overvoltage protection issues in Mixed Voltage IOs is addressed next. When two digital logic devices having different power supply levels are coupled an interface is generally required to prevent damage to transistors in the device having the lower power supply level. In the mixed-voltage I/O buffers, that interface the high-vdd signal environment of the old I/O specifications to low-vdd environment for low power consumption of core circuits, the voltages across transistor terminals should be managed carefully to overcome reliability problems, such as gate-oxide overstress, hot-carrier degradation, and the undesired circuit leakage paths (for the conduction of the parasitic drain-to-well pn-junction diode in the main pullup PMOS device). For example in 3.3V PCI-X bus connected to a transceiver with core circuits operating at 1V and peripheral buffers operating at 2.5V these transistors are to be protected from a voltage of 3.3V that may appear on the bus during its operation. A 2.5V device can safely drive its own IO pin during transmit mode. However when IO pin of 2.5V device is being driven by neighboring 3.3V device, the 2.5V device must include protection circuits attached to the IO pin. Various approaches to protect IO Buffer against Overvoltage induced damages in mixed voltage environment have been proposed. These various approaches have several disadvantages in terms of fabrication cost, reliability issues, area considerations etc. When 3.3V appear on the PAD gate tracking and bulk tracking circuits proposed in this work shift the gate voltage and bulk voltage of PMOS to the PAD voltage namely 3.3V.This reduce the gate oxide stress and standby current in PMOS. Further this circuit reduce substrate leakage currents to negligible values. In addition the protection of NMOS against gate oxide overstress is taken care of by transistor stacking. The proposed circuit is validated by HSpice simulation in 130nm CMOS process and the performance is compared with existing circuits. vi

7 TABLE OF CONTENTS Abstract Contents List of Figures List of Tables Acknowledgements iii viii xi xv xvi 1 Introduction The General Problem IC Failure Mechanisms Failure due to Moisture Failure due to Time Dependent Dielectric Breakdown 5 (TDDB) IC Failure due to Mobile Ions Failure due to Hot Carriers Failure due to Electromigration Failures due to Electrostatic Discharge (ESD) Failures due to Latch up 7 2 ESD in Integrated Circuits ESD Protection Network in Integrated Circuits ESD Test Models Human Body Model Machine Model (MM) Charge Device Model Transmission Line Pulsing(TLP) 15 vii

8 2.3 HBM and TLP Correlation ESD Design Window ESD Devices for IO Protection Non Snapback Devices Diode Zener Diode Snapback Devices GGNMOS Silicon Controlled Rectifier (SCR) 20 3 ESD in Radio Frequency Integrated Circuits ESD Protection Design in RF ICs RF ESD Capacitive Loading Requirements RF LNA ESD Co-Design ESD Modeling and LNA Design Parameters Case 1:ESD Protection at the Gate of LNA The effect of ESD Capacitance on the 32 Matching of LNA The affect of ESD Protection Device on 35 Power Gain and Bandwidth The affect of ESD Device on Noise Figure Case 2 : ESD structure at the Antenna Effect of ESD structure on Input Matching Effect of ESD structure on Noise Figure Effect of ESD structure on Power Gain Common Source Narrowband LNA Design Quality Factor of Inductors LNA Performance Parameters Impedance Matching Power Gain Noise Figure Linearity and 1dB Compression Third Order Intermodulation (IIP3) 52 viii

9 GHz LNA for CDMA standard with ESD Diode Protection ESD Diode Diode CV Characterizing ESD Diode by 100ns TLP Simulation Results Conclusion 61 4 Relative Clauses and the Utterance Unit in Centering 4.1 Mixed-Voltage condition in IO Design Prior Art Mixed Voltage Tolerant IO Buffer using Dual-Oxide 65 Process Mixed Voltage Tolerant IO Buffer Using Depletion MOS Mixed Voltage Tolerant IO Buffer Using Stacked Devices Mixed Voltage Tolerant IO Buffer Using Thin Oxide 69 Devices Modified Mixed Voltage Tolerant IO Buffer Using Thin 71 Oxide Devices Modified Mixed Voltage Tolerant IO Buffer Proposed Mixed Voltage Tolerant IO Buffer Simulation Study Conclusion 89 5 Conclusions 90 Bibliography 93 ix

10 LIST OF FIGURES Figure 1.1 a)esd Protection at the Gate of LNA b)esd Protection at the Antenna v Figure 2.1 ESD Protection Design in ICs 11 Figure 2.2 HBM Setup 12 Figure 2.3 Machine Model Setup 13 Figure 2.4 Charged Device Model Setup 14 Figure 2.5 Transmission Line Pulsing(TLP) Setup 16 Figure 2.6 ESD Design Window junction breakdown-type conduction 18 Figure 2.7 ESD Design Window S-type I-V characteristics. 18 Figure 3.1 Receiver Front-End Blocks 22 Figure 3.2 General ESD Protection Network in IC 24 Figure 3.3 ESD Roadmap for HBM 26 Figure 3.4 ESD Roadmap for CDM 26 Figure 3.5 Common Source LNA with inductive degeneration 30 Figure 3.6 ESD Device at the Gate 31 Figure 3.7 Two stage impedance transformation 31 Figure 3.8 Plot of S11 vs Varying Ls 34 Figure 3.9 Plot of Real part of Zin at resonance with varying Ls 34 Figure 3.10 Plot of frequency response of LNA for different ESD Size 36 x

11 Figure 3.11 Plot of Gain of LNA with varying ESD Size 36 Figure 3.12 Plot of Noise Figure with Varying ESD Size 38 Figure 3.13 ESD Device positioned between Antenna and gate inductor Lg 38 Figure 3.14 Two stage Impedance Transformation 39 Figure 3.15 Variation of Real part of Zin with Ls at resonance for different Cp 41 Figure 3.16 Plot of S11 against varying Lg for different Cp 41 Figure 3.17 Plot of S11 against varying Ls for different Cp 42 Figure 3.18 Plot of Noise Figure against varying ESD Capacitance 42 Figure 3.19 Plot of Rseq against Cp 43 Figure 3.20 Plot of Gain against varying Cp 44 Figure 3.21 Plot of Frequency response of LNA for different Cp 44 Figure 3.22 Inductor equivalent model 46 Figure 3.23 Plot of Inductance against varying frequency 47 Figure 3.24 Plot of Q of inductor with varying frequency 48 Figure 3.25 Plot of S11 with varying frequency 49 Figure 3.26 Plot of S21 with varying Frequency 50 Figure 3.27 Plot of Noise Figure with frequency 51 xi

12 Figure 3.28 Plot of LNA 1dB Compression 52 Figure 3.29 Plot of IIP3 for LNA 53 Figure 3.30 N diffusion in P-well diode(esd NDSX) 54 Figure 3.31 Diode CV Characteristics 56 Figure 3.32 ESD Diode 100ns TLP 57 Figure 3.33 LNA ESD Diode Protection 58 Figure 3.34 Plot of S11 against varying CESD 59 Figure 3.35 Plot of NF against varying CESD 59 Figure 3.36 Plot of Gain against varying CESD 60 Figure 4.1 a)gate Oxide Stress b)parasitic PN junction diode Turn ON during Over voltage at the PAD 63 Figure 4.2 Mixed Voltage Tolerant IO Buffer in Dual Oxide Process 65 Figure 4.3 Mixed Voltage Tolerant IO Buffer using Depletion MOS 67 Figure 4.4 Mixed Voltage Tolerant IO Buffer using stacked PMOS 68 Figure 4.5 Mixed Voltage Tolerant IO Buffer using thin oxide devices 69 Figure 4.6 Modified Mixed Voltage Tolerant IO Buffer using thin oxide 71 Devices Figure 4.7 Modified Mixed Voltage Tolerant IO Buffer 72 Figure 4.8 Block Diagrm of the Proposed Circuit 73 xii

13 Figure 4.9 Truth Table for Pre Driver Buffer Design 74 Figure 4.10 Pre Driver Buffer 74 Figure 4.11 Proposed Mixed Voltage Tolerant IO Buffer 76 Figure 4.12 N-Well Bias voltage during Over voltage at PAD 80 Figure 4.13 Main PMOS Gate Voltage during overvoltage at the PAD 81 Figure 4.14 Main PMOS standby current with protection circuit 81 Figure 4.15 N-well bias voltage during transmission mode 82 Figure 4.16 Substrate leakage current without protection circuit 83 Figure 4.17 Substrate leakage current with over voltage protection circuit 84 Figure 4.18 Voltage between Drain and Source of PMOS during over voltage at PAD 84 Figure 4.19 Voltage between Gate and Drain of PMOS during over voltage 85 Figure 4.20 Voltage across Main NMOS during over voltage at PAD 86 Figure 4.21 Glitches at the output of the receiver while receiving 0V/2.5V signal from the mixed voltage tolerant buffer 87 xiii

14 List of Tables Table 2.1 ESD Protection Level Targets 10 Table 3.1 Simulated results for S21 and Noise figure for different ESD Size 37 Table 3.2 Simulated results for S21 and Noise figure for different ESD Size 44 Table 3.3 Simulated Results for LNA 53 Table 3.4 Diode Sizing for HBM ESD Protection 57 Table 3.5 Simulated Results for LNA with ESD Protection 60 Table 4.1 Comparision of average power dissipation of different Mixed voltage tolerant IO Buffer designs during transmission 88 Table 4.2 Comparison of delay times of different mixed voltage Tolerant IO Buffer designs 88 xiv

15 ACKNOWLEDGMENTS I thank my advisor, Prof.Satyam Mandavilli. Besides his support and teachings, he encouraged the development of the concepts presented in this dissertation. I am also grateful to my mentors Dr. R.D.Prabhu, Mr. Shyam Parthasarthy, Mr. Srikanth, Mr. Rahul Nayak at IBM SRDC for their support and discussion while investigating ESD solutions for RF applications. I thank IIIT,Hyderabad for fellowship provided to initiate my MS Research. I acknowledge and thank many valuable teachers and friends I have found along my way, who have shared with me their wisdom and invaluable time. I thank IBM SRDC Compact Modeling Group for supporting my research project and granting me access to state of the art equipment. Finally, I thank my family for their continuous and unconditional support and understanding. xv

16 Chapter 1 Introduction 1.1 The General Problem Electrostatic discharge (ESD) and Over voltage stress are the most important reliability problems in the integrated circuits (ICs). Typically, two-third of all field failures (customer returns) are due to ESD and Over-voltage Stress (EOS) [27,28]. As ESD and Over-voltage stress damage have become more prevalent in newer technologies due to the higher susceptibility of smaller circuit components, there has been a corresponding increase in efforts to understand these failures through modeling and failure analysis. This has resulted in a greater industry-wide knowledge of IC failure mechanisms and thus a greater ability to design robust ICs which sustain fewer field failures. Many of the today s smart power applications combine different technologies such as low frequency and RF frequency, low voltage and high voltage etc on a single IC to reduce area and power and increase the speed. Each of these applications have different protection requirements and has to be addressed separately [32] [34]. For example RF circuits have different concerns in comparison with digital circuits (more stringent ESD requirement as compared with digital circuits). Similarly Mixed Voltage Technologies call for Over-voltage protection circuits and ESD devices cannot address the over-voltage stress issues. 1

17 An electrostatic discharge (ESD) is an event that transfers a finite amount of charge between objects brought into close contact. Depending on the object type, the process can result in a rapid (hundreds of nanoseconds) and high current pulse of several amperes. The presence of electrostatic discharge affects the semiconductor devices considerably, and has become a topic of major interest and discussion [27,28,29]. Due to the small size of today s semiconductor devices, the large electric field induced during an ESD event would likely cause latchup, local melting, soft or hard damage or destructive breakdown in sensitive isolation layers, such as thin gate oxide in CMOS technologies.esd events belong to a class of EOS with stress time ranging between 1ns and 150ns. Designing ESD protection circuits becomes more challenging as device dimensions shrink, particularly in MOS technologies and as the frequency of IC operation reaches RF range. As ICs become smaller and faster, susceptibility of the protection circuits to damage increases due to higher current densities and lower voltage tolerances. As the frequency of operation increases ESD to circuit interactions such as parasitic loading and RF performance degradation increases. Overvoltage stress belong to a class of EOS with stress time greater than 150ns.Unlike ESD which is transient in behavior Overvoltage stress is non transient and continue to damage the device throughout its life time. The device dimension of transistor has been scaled toward the nanometer region and the power-supply voltage of chips in the nanoscale CMOS technology has been also decreased. Obviously, the shrunk device dimension makes the chip area smaller to save silicon cost. The lower power-supply voltage (VDD) results in lower power consumption. Therefore, chip design quickly migrates to the lower voltage level with the advancement of the nanoscale CMOS technology. However, some peripheral components or other integrated circuits 2

18 (ICs) in an electronic system are still operated at higher voltage levels, such as 3.3V or 5 V [13] [14]. In other words, an electronic system could have chips operated at different voltage levels. In order to interface these chips with different voltage levels, the conventional I/O buffer is unsuitable anymore. Several problems arise in the I/O interface between these ICs, such as the gateoxide reliability [10] [14], the hot-carrier degradation, and the undesirable leakage current paths. Now the question is cant t a single protection strategy take care of both ESD and Overvoltage protection problem. The answer is NO. This is because ESD devices are designed to respond to particular kind of ESD waveforms and they may not be triggered at all during Overvoltage conditions. Even the device that is designed for HBM kind of ESD event may not at all respond to CDM kind of ESD event. If the PAD is Bidirectional then ESD diodes cannot be used for the Over-voltage protection since they suppress PAD voltage which is not desirable. Apart from this positioning of ESD device is another problem. If it is a common bus driven by I/O drivers operated at different voltage technologies then ESD device cannot be used. Apart from this latchup of ESD devices is another issue. Since the two voltage levels in mixed voltage technologies in our discussion are in close proximity the latchup of ESD protection device may take place. So each of these protection issues have to be addressed separately. In this dissertation the focus is on the design of Overvoltage protection circuit to address gate oxide reliability and hot carried degradation issues under mixed voltage condition and ESD protection strategies for RF components such as LNAs. Since RF components in IC pose stringent requirements for ESD 3

19 protection we develop analysis that accounts for the effect of standard ESD structures on critical LNA specifications. This chapter is meant to create the context in which the project task is undertaken by introducing different IC Failure Mechanisms and their impact in integrated circuits. 1.2 IC Failure Mechanisms There are a number of physical failure mechanisms that can affect the reliability of a CMOS IC [30,33,34]. Some of the common mechanisms can be mitigated by adhering to foundry design rules (Electromigration, Time Dependent Dielectric Breakdown (TDDB) and Hot Carrier Damage). Certain fabrication steps can cause stress that may lead to latent damage that may later reduce the useful lifetime of IC. Contamination with Mobile Ions (most commonly Sodium) will render transistor characteristics unstable and encourage early TDDB. Process Induced Oxide Charging, caused by injection of charge into gate oxides during certain ion etching processes, will reduce TDDB lifetime and cause some transistor degradation similar to Hot Carrier Damage. Metal Stress Migration, which is caused by large thermal coefficient of expansion difference between metal interconnect and inter-level dielectrics (oxides), can lead to voiding of metal lines similar to damage caused by Electromigration. Human Handling or Machine handling of ICs can cause ESD induced damage.esd damage can also occur due to IC self charging and discharging through grounded object. This section will outline the most common physical failure mechanisms and describe in general terms how a foundry is able to control them with processing design and with design rules. 4

20 1.2.1 Failure due to Moisture The one area most frequently ignored is the impact of humidity on both components and bare boards [30,33]. Moisture trapped within components and PCB s presents a unique problem in the fabrication and assembly process. Too much moisture can lead to board failures during the reflow process when it turns into steam. The resulting pressure can cause packages to erupt damaging lead-frames or wire-bonded connections between the silicon and the outside world. Damage may be visible with an opening in the outer surface of the component or hidden on side and inner layer of a multi-layer PCB. Regardless of the location of the damage, the result is the same, an unusable assembly Failure due to Time Dependent Dielectric Breakdown (TDDB) TDDB is wear-out of the insulating properties of silicon dioxide in the CMOS gate leading to the formation of a conducting path through the oxide to the substrate. With a conducting path between the gate and the substrate, it is no longer possible to control current flow between the drain and source by means of the gate electric field. TDDB lifetime is strongly affected by the number of defects in the gate oxide produced during wafer fabrication. Therefore, foundries strive to produce an ultra-clean oxide in their process to maximize the TDDB lifetime IC Failure due to Mobile Ions Contamination with Mobile Ions (most commonly Sodium) will render transistor characteristics unstable and encourage early TDDB. Process Induced Oxide Charging, caused by injection of charge into gate oxides during certain ion etching processes, will reduce TDDB lifetime and cause some transistor degradation similar to Hot Carrier Damage. Metal Stress Migration, which is 5

21 caused by large thermal coefficient of expansion difference between metal interconnect and inter-level dielectrics (oxides), can lead to voiding of metal lines similar to damage caused by Electromigration Failure due to Hot Carriers Hot carrier damage causes the transistor transconductance to slowly degrade and eventually may cause the transistor threshold to change near the drain edge of the channel such that it cannot form a channel in the drain region [30,33]. This mechanism can be more damaging to digital circuits because it will cause parts of the digital circuit to have longer delay than originally intended, leading to logic race conditions. With minimum channel length transistors, hot carrier damage occurs even when operating voltages are within foundry specification. Mathematical modeling of hot carrier damage rates is very difficult. Most common models are not sufficiently accurate in predicting damage rate at all bias conditions to be useful in a detailed design tradeoff Failure due to Electromigration Electromigration is the diffusion of metal atoms along the conductor in the direction of electron flow. This directional diffusion process occurs because the momentum transfer between the electrons and the metal atoms increases the probability that a metal atom will move in the direction of the electron flow. This diffusion process will preferentially fill metal ion vacancies found in crystal defects, leaving a vacancy in the location from which the metal atom came. Damage only occurs when there is a metal ion flux divergence that causes metal ions to be taken from one part of a wire and deposit them in some other location without replenishing the metal ions from a reservoir. The flux divergence causes vacancies to coalesce in one location to produce a void. 6

22 This void volume grows until there is no metal in a short length of the wire, causing current flow is interrupted leading to circuit failure Failures due to Electrostatic Discharge (ESD) Electrostatic discharge (ESD) is a single, fast, high current transfer of electrostatic charge between two objects at different electrostatic potentials [30,31,33]. If this high current transfer exceeds the maximum rating of the fabrication process, it will damage the IC. Protection from ESD must be part of the circuit design and the manufacturing environment Failures due to Latch up Latch-up can be caused by the parasitic bipolar transistors inherent to a CMOS design. These parasitic transistors can be activated in various ways and can dominate the CMOS circuit behavior thus creating electrical overstress failures. The arrangement of individual circuit elements within the design plays a critical role in determining a product s ability to withstand transient currents (latch-up) or voltages (ESD) without incurring damage. CMOS foundries are strongly motivated to mitigate any physical mechanism that may cause an IC to fail due to some known physical failure mechanism within a specific reliability target. Once the wafer processing is optimized for maximum lifetime set by each physical mechanism, the foundry develops design rules intended to prevent IC designers from over-stressing the devices and cause the expected lifetime to fall below foundry targets. These design rules will be embodied in the form of maximum operating voltage, transistor channel length constraints for service under certain bias conditions, maximum current per unit line width in metal interconnect, maximum current per contact 7

23 or via and certain constraints upon interconnect layout of very wide metal lines. Failure to comply with the reliability design rules may lead to unpredictably shorter IC lifetime. Of all the IC failure mechanisms discussed above nearly 50%- 60% IC failures are due to ESD and Overvoltage Stress issues, while remaining are due to Electromigration, Hot carrier damage and TDDB. The focus of this dissertation will be on ESD and Overvoltage Protection issues from circuit design point. The dissertation is arranged as follows. In Chapter 2 the basics of ESD in ICs, Various ESD Models available for characterizing ESD device for protection, ESD design window limitations with technology node shrinking to 0.18um and below are discussed. In Chapter 3 ESD protection consideration for LNA which form the most ESD sensitive block in most of the RF Receivers is discussed. As the frequency increases the limit upon the size of ESD device used for protection decreases which ultimately reduce the level of ESD protection and the time to failure. In this section we propose new methodology for LNA protection which is valid when ON chip inductors are used and gives greater freedom upon the size of ESD protection device while keeping the performance degradation of LNA within acceptable limits. In Chapter 4, Over-voltage reliability issues in Mixed-Voltage IOs is discussed in detail. Various approaches at process level, device level and circuit level earlier followed to mitigate the damages caused by over-voltage issues and their short comings are discussed. We then propose new mixed voltage tolerant IO buffer which address all the issues existed with earlier designs. The proposed design is validated through simulations in 0.13um CMOS process. 8

24 Chapter 2 ESD in Integrated Circuits In Chapter 1 we introduced in general various IC failure mechanisms and noted that nearly 50-60% of all these IC failures are due to ESD and Overvoltage Stress [29,32,34]. In this chapter we cover in detail ESD in Integrated Circuits, ESD Test Models and ESD Design Window. Electrical overstress is defined as the damage to a product caused by exceeding datasheet maximum ratings. EOS usually leads to gross damage in an integrated circuit resulting from high-energy events such as electrostatic discharge, electromagnetic pulses, lightning, or reversal of power and ground pins. EOS failure mechanisms fall into the two broad categories of thermally induced failures and high electric-field failures. The duration of an EOS event may be anywhere from less than one nanosecond to one millisecond and longer. Long EOS events can lead to damaged areas such as blown metal lines, cavities in the silicon, or discoloration of silicon due to local heating. This damage leads to either a reduction in IC performance (e.g., increased leakage current on one or more pins) or total circuit failure. The region of EOS phenomena with stress times of less than one nanosecond up to a few hundred nanoseconds is known as electrostatic discharge. ESD is a relatively rapid, high-current event resulting from the high voltage created when electrostatic charges are rapidly transferred between bodies at different potentials. ESD usually leads to relatively subtle, localized damage sites. Dielectric failure and thermal failure are generally considered to be catastrophic, i.e., the IC is no longer functional after the ESD stress. However, as it has been noted above there is another type of ESD damage referred to as 9

25 latent damage. Latent damage consists of increased leakage current or reduced oxide integrity, without loss of functionality, of a stressed circuit. A latent ESD failure is defined as a malfunction that occurs in use conditions because of earlier exposure to ESD that did not result in an immediately detectable discrepancy. Low-level leakage (an increase in leakage which remains below the failure threshold), also referred to as soft failure, may be due to injection of hot carriers into the gate oxide, which would cause a threshold-voltage shift, or to damage in the silicon resulting from localized melting, or to both. A small damage site could act like a high-resistance filament across a diode junction, thereby increasing the leakage current to a significant but non-catastrophic level. It is certainly possible for second breakdown to occur, and even for melting to occur, without catastrophic failure if there is not enough energy in an ESD pulse to cause widespread damage. In narrow devices, when a hot spot forms all of the available current rushes to the spot, but there is not enough total current to cause catastrophic damage. Extensive damage will not occur until the device is driven deeper into second breakdown by being stressed with a higher current. Table lists ESD protection levels generally targeted in Integrated Circuits. Table 2.1 ESD Protection Level Targets ESD Model Industry Standard Human Body Model (HBM) Machine Model (MM) Charged Device Model 2000V 200V 500V (CDM) 10

26 2.1 ESD Protection Network in Integrated Circuits Figure 2.1 ESD Protection Design in ICs The internal ESD protection requires the placement of adequate on-chip protection devices on the I/O and on the power supply pins to reliably bypass the ESD energy before it can damage the sensitive circuits [32,34]. The onchip protection scheme should have an explicit and robust path for the ESD currents to flow between any pair of pins. In general, pad protection networks shunt I/O pins to the ground or VDD bus under stress events. For each input pin, a dedicated protection network, that is completely passive under normal operating conditions, has to be added. A good protection element should minimize the nominal performance and/or voltage degradation to the I/O circuit due to its insertion and provide a lowimpedance shunt path for the ESD current. The protection element must be capable of handling multiple ESD events without itself being destroyed. It should also not interfere with the I/O circuit during its normal operation. Figure shows general ESD network followed in ICs. During ESD event at one of the IO or supply pins the ESD Protection Devices act as short circuit 11

27 and shunt signal power to the ground. The power clamps are used to complete the current loop during positive ESD Zap at the PAD. 2.2 ESD Test Models In order to characterize the susceptibility of an IC to ESD damage, the IC must be tested using standard models which simulate real ESD events [29,30,32]. The ESD models are represented as lumped circuit equivalents, so that testing is consistent and reliability can be defined as a quantitative attribute. ESD stress occurs during wafer fabrication, surface bonding, packaging, testing, or any other time the circuit comes in contact with a person or machine. Specific tests are designed to model particular events such as human- or machine- discharge to ground, field induction, cable interconnections, among other conditions encountered in the handling and operation of ICs Human Body Model Figure 2.2 HBM Setup 12

28 One of the most frequently observed ESD events is the transfer of electrostatic charge from a charged human body to an ESD sensitive device due to improper handling. The model developed to represent this event is the Human Body Model (HBM), which is the most classical and common industrial test methods. In the HBM, it is assumed that a certain amount of electrostatic charge initially is stored on the body and the charge is transferred to an object through a finger when the physical contact between the charged human body and the object is made. Fig. 2.2 shows a simplified equivalent circuit of HBM ESD conditions. It consists of a charging capacitor, and contact resistance between the charge source and the Device Under Test (DUT). In the HBM standard, the circuit component used to simulate the charged human body is a 100 pf capacitor and the resistance of the discharging path is 1.5K Ω; it electrically looks like a current source if the DUT provides a current path of low resistivity. LHBM (~0.75 μh) is the effective inductance of the discharge path in a real tester. HBM has the longest pulse among the three primary ESD models. The rise time of the HBM pulse is approximately 5-10 ns, and the decay time is ~150 ns Machine Model (MM) Figure 2.3 Machine Model Setup 13

29 Another fundamental model widely used in the industry is the Machine Model (MM). Similar to HBM event, a capacitor (200pf) which represents a conductive object such as a metallic handler is charged up to a high voltage and then discharged through the pins of an IC. In this model, it is assumed that an arc discharge occurs between the charged source and the DUT. An arc discharge fundamentally has a resistance of Ω which is much lower than the RHBM (~1500 Ω). Therefore, the MM response is more rapid than the HBM event, and has a form of bidirectional damped oscillation. The MM event also shows a significantly higher current than the HBM Charge Device Model Figure 2.4 Charged Device Model Setup The CDM event charges a chip and then discharges to ground out of a single pin. While the HBM and MM events occur between two pins, the discharging process of the CDM events involves a single pin on the module. The charging process can be initiated either by direct charging, or field-induced charging. Electrostatic charge can be accumulated on the device through triboelectric 14

30 effects, which frequently occur when a device moves across a surface or vibrates in a package. The discharge process can be initiated as electric contact is made between the charged device and the discharging means such as automated handlers. In an actual test environment, a filed plate imposes a specified charge on the packaged module, and then a metallic probe touches a pin, forming a low resistive path from the pin to ground. As shown in Fig. 2.3, the CDM event occurs in an extremely short time interval, but generates very high current. CDM discharge occurs at less than 5 ns where typically the rise time of the event is of the order of 250 ps. Since the waveform of CDM events are different from HBM and MM, the failure signatures are not identical either. While thermal destruction is the primary failure mechanism in the HBM and MM, dielectric failure is the typical failure mode in the CDM type ESD Transmission Line Pulsing(TLP) Besides the three primary ESD standards described above, the Transmission Line Pulsing (TLP) technique is the industry standard for characterization of ESD devices for protection. ESD events occur within the time period of a few nanoseconds to hundred nanoseconds. Therefore, it is important to characterize behavior of devices on the ESD-relevant time scales. Since DC measurements can cause severe self-heating, and cannot address the transient characteristics of devices under ESD conditions, pulsed measurement techniques are required for ESD characterization. The basic concept of TLP is to apply a square wave to the DUT and then measure the current and voltage across the device. The energy in so generated TLP pulse is same as in any of ESD event. The schematic of a TLP system and the principle of pulsed characterization are illustrated in Fig A transmission line is charged to a specified test voltage and then discharged 15

31 through the DUT when the switch closes. The pulse width of a transmission line pulse is determined by the length of the transmission line and the propagation velocity of the transmission line; therefore, the pulse width as well as amplitude of input voltage to the device can be controlled by the physical length of the transmission line and the initial voltage on the transmission line. In standard practice today, the TLP cable length is chosen to provide a TLP pulse width of 100 ns with less than 10 ns rise time. To investigate and characterize ESD behavior of protection devices, the transmission line pulsing (TLP) have been used throughout this work. Figure 2.5 Transmission Line Pulsing(TLP) Setup 2.3 HBM and TLP Correlation Typically, TLP systems have 100ns wide rectangular pulses because this length pulse has been found to initiate junction damage at the same peak current as HBM test pulses. The 100ns wide rectangular TLP pulse has been shown to provide correlation to the HBM pulse. This conclusion was done 16

32 based on TLP and HBM testing of different devices implemented in 0.35um and 0.18um CMOS Technology. For 0.18um technology the correlation model is VHBM(KV)=1.5*ITLP. 2.4 ESD Design Window Many different aspects need to be taken into account for the development of ESD protection concepts in nano-metric CMOS technologies [32,34]. It starts with the selection of suitable protection elements and ends in the choice of an ESD optimized circuitry All ESD devices have to fulfill certain conditions concerning their I-V characteristics, which are described by the ESD design window shown in Figure 2.6 and Figure 2.7. The ESD design windows for each protection structure incorporated in different protection schemes are generally different, and strongly affected by migration between technologies and circuit operating conditions. The ESD structure may depict different types of conductions, e.g., (a) junction breakdown-type characteristics, or (b) S-type I-V characteristics. Key considerations for the design of this specific protection component include: 1) low leakage current in the V to V operating voltage, 2) the breakdown SS DD voltage (BV ), trigger voltage (V ), as well as the clamping voltage at the f tf required ESD level, have to be kept below the range of voltage where oxide breakdown or breakdown of internal parasitic components take place, 3) the sustaining point (also called holding point) in the case of the S-type I-V characteristics has to be larger than the V plus a safety range; this avoids DD latchup problems or unintentional on-state condition in the protection devices, and 4) good robustness of the protection device, i.e., low power dissipation and high ratio of ESD protection per unit area. 17

33 Figure 2.6 ESD Design Window junction breakdown-type conduction Figure 2.7 ESD Design Window S-type I-V characteristics. 18

34 2.5 ESD Devices for IO Protection Based on the shape of the I-V characteristic of semiconductor devices, ESD devices are divided into two main categories: non-snapback devices and snapback devices [29,34] Non Snapback Devices In case of non snapback devices if the voltage across them is increased beyond a certain voltage, the current starts to increase rapidly while the voltage across them remains constant. Diodes are good examples of this category. As an ESD protection device, p-n junction diode, zener diode, and punch through TVS are widely used Diode A p-n junction diode is a simple and effective ESD protection device. Their forward bias behavior is exploited to safely carry a large amount of ESD current while their reverse bias behavior is exploited under normal operating conditions. Diode has very low on resistance in forward biased mode and hence can handle large current with very low power dissipation. Since diode can handle large current per unit capacitance it is generally used as ESD protection device in RF and High speed IO application Zener Diode In addition to p-n junction diode, zener diode can also be used in ESD protection circuits. Zener diode is a reverse biased diode with lower triggering voltage. Although the zener diode has lower on-voltage compared to regular reverse-biased p-n junction diode, its on-voltage is still higher than oxide breakdown voltage and hence, it is not used as the main protection 19

35 device. This diode is usually used as a secondary device which helps the main protection device Snapback Devices Snapback devices, similar to a reverse biased diode, go to the breakdown region as the voltage across them is increased. After breakdown, due to an internal positive feedback mechanism, the voltage across the device drops and the device moves from breakdown region to the holding region. MOSFET and Silicon Controlled Rectifier (SCR) are the most important snapback devices in the CMOS technology GGNMOS The simplest form of a MOSFET in ESD protection applications is the grounded gate configuration where the gate and source of the transistor are connected to ground. Here the parasitic lateral BJT inherent in the NMOS is use as ESD protection device. As the drain voltage increases, the drainsubstrate junction becomes more reverse biased until it goes into avalanche breakdown. At this point the current flowing towards the substrate develops voltage which forwards bias the source substrate junction diode. Once this diode turns on the current increases and the voltage across the GGNMOS is clamped to low voltage. Generally GGNMOS are not used for RF applications because of large capacitive loading Silicon Controlled Rectifier (SCR) Silicon Controlled Rectifier (SCR) is another active device that is often used as a protection element. It consists of a pnpn structure. The p+ diffusion in the n-well forms the anode, and the n+ diffusion in the p-sub forms the cathode of the SCR. Among all the ESD protection devices SCRs have best 20

36 Figure of Merit and hence are widely used for RF applications. Their disadvantage is large trigger voltage which makes them not suitable for applications like LNA protection. So generally they are used in high voltage technologies like RF Switch protection. In this dissertation double diode protection in CMOS SOI Technology is considered for LNA protection because of its low turn on voltage, low ON resistance and low capacitive loading. 21

37 Chapter 3 ESD in Radio Frequency Integrated Circuits Wireless communication market is growing rapidly. There is an increasing demand for portable electronic devices such as cellular and cordless phones, pagers, wireless modems and GPS receivers. Furthermore, more options are constantly added to these portable devices. As a result, today s cellular phones have a much wider capabilities such as sending and receiving data, pictures and even receiving radio and television networks. This evolution is a result of constant increase in the integration level of semiconductor devices and reduction in their cost. Figure 3.1 Receiver Front-End Blocks In all of the above mentioned systems, the receiver block is one of the most challenging parts of the design. Figure 3.1 shows the block diagram of a receiver. In this block diagram, the input RF signal is received at the antenna and is amplified by the Low Noise Amplifier (LNA). Down conversion of RF frequency is achieved using the Local Oscillator (LO) and the mixer. As any integrated circuit, RF systems need to have an ESD protection circuit. Referring back to Figure 3.1 it can be seen that the LNA form the first blocks of the system and is the most sensitive one to parasitics of ESD protection 22

38 circuits. An LNA block has input matching and low noise requirements. However, adding an ESD protection circuit to the LNA adds extra parasitic capacitance and resistance to the input of the amplifier. These extra capacitance and resistance degrade both matching constraint and noise requirements of the LNA [43,44]. The situation worsen as the frequency of operation increases. This poses bound upon the size of ESD device and the level of ESD protection that can be achieved without much degrading the LNA performance. In this chapter we propose a methodology to improve the level of ESD protection achievable with given ESD size by making use of ON chip inductors available for frequency selection and matching in LNA. 3.1 ESD Protection Design in RF ICs As the demand for wireless RF and high speed mixed-signal systems is rapidly increasing, on chip ESD protection design for these systems has posed a tremendous challenge [31,42,44]. While providing sufficient immunity to the ESD stresses, ESD protection devices should not affect the signal under normal operating conditions. However, the ESD protection devices introduce parasitic capacitances and resistances, and the capacitance associated with the ESD protection devices can be of the order of pf. In the GHz frequency regime, the reactance due to this large capacitance becomes comparable to the characteristic impedance at the interfaces (typically 50 Ω), causing reflections of the signals, inefficient power transfer etc. The ESD devices can also generate noise or exacerbate the substrate noise coupling problem. Because of these negative effects on the circuit performance, there used to be a sign-off waiver for the ESD protections of RF ICs, which means that no ESD protection or only limited size of ESD protection devices were installed at the inputs of RF ICs. However, due to the integration of today s complex mixedsystem in CMOS technologies, there is no longer any differentiation between 23

39 RF pins and digital pins. Therefore, there should be no difference in their ESD performance. As the number of RF pins per device increases, the ESD robustness of the RF pins has become a critical factor in determining the yield ratio. Thus a good methodology to provide sufficient ESD protection capability with tolerable interference to the RF performances is required. To develop a good RF ESD protection scheme, at first the nature of ESD-tocircuit impact should be understood. Figure 3.2 shows ESD design practice generally followed in Integrated Circuits. Two clamp devices such as diodes take care of positive and negative ESD zaps at the pad. Power clamp completes the current loop to ground during positive zap.esd device provide predefined low resistance current path to ground during ESD event at the pad. The same protection approach is followed in the discussions to follow. Figure 3.2 General ESD Protection Network in ICs In this dissertation we focus on ESD Protection for LNA which form most ESD sensitive blocks at most Receiver Front-Ends. We consider Cascode LNA with inductive degeneration for all the analysis. 24

40 3.2 RF ESD Capacitive Loading Requirements In the race to provide more and faster functionality, on-chip ESD protection is often sacrificed in favor of chip performance. According to the ESD Association, the ICs of tomorrow will not sustain the current levels (2KV HBM) of on-chip ESD protection[37,38]. At the system level, as on-chip protection is reduced, ICs will be more sensitive to transients such as cable discharge events and ESD from the human body. With increased ESD sensitivity of future ICs, the need to protect systems with more robust off-chip transient voltage suppression is greater than ever. With applications of increasing RF frequencies in areas like communication (several GHz) there is increased pressure to reduce the capacitive loading and improve the quality factor (Q-factor) of ESD devices. The roadmap for ESD projects severe restrictions on the achievable HBM ESD levels as shown in Figure 3.3 and Figure 3.4 [35]. What should be noted from Figures is that the major impact is expected within the next 5 years around the 32nm technology. Constraints from the circuit designs such as RF could eventually reduce the practical ESD HBM design levels into the 100V range. Similarly, the CDM level may get reduced to the 50V range. This will severely degrade the overall life time of ICs. 25

41 Figure 3.3 ESD Roadmap for HBM Figure 3.4 ESD Roadmap for CDM In RF receiver, LNA forms the most ESD sensitive block since its gate is directly connected to the outside world. As LNA operates at higher frequencies, another bottleneck emerges[46,48,49]. Capacitance of propersized ESD protection devices cannot be reduced unlimitedly. The limitation causes difficult trade- off between RF performance and ESD immunity. As the RF frequency increases the degradation of LNA performance, by the given ESD capacitance increases. This is because the capacitive reactance 26

42 decreases as the frequency increases and hence shunts more signal power to the ground. This calls for reduction in ESD capacitance to maintain the performance which results in reduced ESD immunity of the circuit under consideration leading to reduced lifetime of the circuit. 3.3 RF LNA ESD Co-Design Even though every pin on a chip is intended to connect to the outside world, they all have a different affinity for ESD-stress[44,46,47,48,49]. Some pins are more intrinsically immune since they connect for instance to a large junction diode or they feature a large bias resistance in series. The most sensitive pins are the ones connecting directly to the gate of a MOS transistor. Since the LNA input pin connects to the gate of the amplifying NMOS transistor, it is extremely sensitive to ESD. Hence when talking about RF-ESD co-design for LNA s, the main issue is how to protect the input gate without severely deteriorating the performance of the LNA. Although this is a critical issue, very few LNA s have been published with ESD-protection results. In fact, one of the main bottlenecks for introducing CMOS RF circuits to the market is their susceptibility to ESD. It is mainly due to both gate oxide breakdown and junction degradation related problems. These problems become even more severe as technologies scale further towards nanometer dimensions. As gate length decreases, so does the oxide thickness reducing the breakdown voltage of the transistor gate. The ESD problems are still aggravated by the tight design window for the high performance RF circuits, not allowing large ESD devices to be used as protection elements. Most CMOS ESD-protection structures (e.g. as they are used in digital CMOS) have parasitics that are detrimental for the LNA performance. The introduced parasitic input capacitance also has a serious 27

43 influence on the performance of the common source LNA. The discussion on RF-ESD co-design will concentrate mainly on this topology. The passives used in the design of RF Receiver blocks also influence the ESD robustness of LNA [52,55]. Inductors and capacitors in RF circuits can be implemented either ON chip or OFF chip. In earlier technologies where the passives used to be OFF chip the ESD immunity of the LNA was totally determined by the robustness of ESD protection device. However in modern RF ICs the focus is on full integration to reduce system cost and area. So the passives appear ON chip. On-chip inductors are integrated on IC using semiconductor technologies. ON chip inductors provide the similar performance as the surface mounted passives, while occupy less package substrate area and cost less. When inductors stay off chip, parasitics from packaging interface (such as bonding wires, I/O pad, ESD) will be introduced, which may degrade the performance. Extra I/O pads, to connect chips and passives consume extra chip area. This is particularly true for small chips where chip size is dominated by the number of I/O pads. In addition, most packaging technologies present larger process variations than IC technologies, which consequently cause variation of the circuits' responses and degradation of robustness, thus reducing overall yield and increasing product costs. In RF ESD Protection it is common practice where capacitors and inductors in the circuit used for matching and frequency selection, are used to tune out ESD frequencies [55]. In a cascode LNA with inductive degeneration (Figure 3.5)where ON chip inductors are used they can be used for ESD protection. The most common ESD protection topology is to position two clamp diodes at the gate of LNA as shown in Figure 3.2. However modifying this topology by shifting these protection diodes after the gate inductor towards the antenna in the above LNA topology the ESD robustness of LNA may be increased 28

44 especially at high frequencies. In this modified topology inductor helps in suppressing steep current transients. Also the performance degradation of LNA at operating frequencies is reduced since the capacitive effects of ESD protection device on LNA performance parameters is reduced. This will be discussed in detail in the sections to follow. The focus of this chapter will be to analyze the ESD robustness (protection level) of LNA in modified topology. The analysis is validated by simulation for 2.1GHz LNA with ON chip Spiral inductors and ESD protection in Cadence Design Suite using IBM CSOI7TF 180nm RF Technology. 3.4 ESD Modeling and LNA Design Parameters The circuit diagram of the LNA used in this discussion is shown in the Figure 3.5. The LNA topology was chosen as it is the most popular topology for the implementation of narrow band LNAs today [55,56,57]. The ESD Device have been modeled with a capacitance Cp and ideal inductors have been used to simplify the analysis. Although a capacitance in series with a resistance is a more accurate model for ESD structure, the value of this resistance is intrinsically small. Hence modeling of the ESD structures with a capacitance is realistic. It should be noted that higher level of ESD protection leads to larger ESD device and hence Cp increases with ESD protection level. 29

45 Figure 3.5 Common Source LNA with inductive degeneration ESD protection methodology for LNA which is analyzed for the case of OFF Chip gate inductor in earlier works is shown in Figure 3.6. The same analysis is still followed for the case of On Chip inductors in the works published in recent times. For this method of protection as the frequency increases to increase the ESD immunity of the circuit without degrading the performance of LNA, additional components have to be used. This increases the chip area and cost and also degrades RF Block noise performance. However the gate inductor Lg can be used as a part of ESD protection circuit to improve the ESD immunity of LNA without use of additional components and without sacrificing the LNA performance. Also the parasitic resistances of the gate inductor serve as secondary ESD protection component by limiting the ESD current flowing into the circuit. In what follows is the analysis of the ESD along with the inductor. Two cases have been considered for this purpose. Firstly ESD structure positioned at the gate of LNA. Secondly ESD structures positioned at a point away from gate of 30

46 LNA between Gate Inductor and Antenna and determine the level of protection provided by given ESD size at these different points. This is followed by performance analysis of LNA for these two different cases Case 1:ESD Protection at the Gate of LNA Figure 3.6 ESD Device at the Gate of LNA Figure 3.7 Two stage impedance transformation The circuit schematic with ESD device at the gate of LNA is shown in the Figure 3.6 [52,56,57]. Cp denotes parasitic capacitance of the ESD device. For the moment it is assumed that Cp behaves ideally. This means it is completely linear and lossless. If Cp were zero then the gate of LNA would see a signal source with a complex source impedance ZS given by 31

47 Z S = R S + jωl g where Rs = 50 Ω. However in the presence of Cp, looking to the left from the gate of LNA now sees different impedance. At the operating frequency of the LNA, this equivalent source impedance can again be split into a real and imaginary part Zseq = Rseq + jω 0 Lgeq, where Rseq and Lgeq are the resistive and inductive part of the new, equivalent source impedance as indicated in Figure 3.7. They can be found through the two-step series-parallel transformation shown in Figure 3.7, valid at ω 0. The ESD device when connected at the input would affect the input matching which in turn gets reflected as change in the power gain, the bandwidth of LNA and NF. In the following is an analysis of the effect of ESD on all these parameters. For this purpose the S-Parameters of LNA are used for discussion The effect of ESD Capacitance on the Matching of LNA The presence of ESD at the input disturbs the original matching conditions namely; the impedance seen by the antenna would be different from the characteristic impedance of 50 Ω. This results in reflections at the input and doesn t result in maximum voltage needed. Therefore it is necessary to modify 32

48 the matching network to take account of the presence of ESD capacitance so that there are no reflections at the antenna side. This calls for modification of inductive elements in the matching network. The real part of Zin looking into the gate of LNA is given by It has is found that the affect of Cp can be annulled by varying source inductance Ls. To find exact value of Ls, Ls is varied as shown in Figure 3.8, from 0 to 4nH and S11 in measured through simulation of LNA. For different values of Cp variation of S11 with Ls is shown if Figure 3.8. S11 of the amplifier indicates how well the antenna is matched to the amplifier. It is taken as the ratio of reflected power to the incident power expressed in db. It may be seen from the graph the lowest value of S11 can be obtained with a Cp=0 and as Cp increases the lowest value of S11 goes higher indicating that matching becomes difficult with higher Cp. 33

49 Figure 3.8 Plot of S11 against Varying Ls Figure 3.9 Plot of Real part of Zin at resonance against varying Ls 34

50 With a view to find out the limitation on lowest S11 the input impedance of the amplifier and matching network together has been found at resonant frequency where the impedance is purely resistive. The curves in Figure 3.9 show the behavior of Re(Zin) for different values of Cp at resonance. The Re(Zin) vs Ls curve shifts down as Cp increases. If Cp is large enough the curve is shifted down such that its maximum value is less than 50Ω which implies that irrespective of the value of Ls the input cannot be matched to 50Ω. From Figure 3.9 it is seen that beyond 200fF input capacitance the input is never matched to 50Ω whatever is the value of Ls. This investigation clearly establish the limitations of using larger area diodes (with higher Cp) The affect of ESD Protection Device on Power Gain and Bandwidth The affect of this protection diode on the power gain and bandwidth of LNA has been measured from the frequency response of LNA given in Figure 3.10 and Figure The resonant frequency for the purpose of the discussion is that frequency for which the power in the load is maximum. The frequency response curve given in Figure 3.10 is power in load at different frequency. During measurement of this power the input is given through a generator of 50 Ω internal impedance and the input voltage is kept at constant amplitude of 50uV. From these curves the shift in resonant frequency and the drop in power gain at different ESD capacitance have been obtained and given in Table

51 Figure 3.10 Plot of frequency response of LNA for different ESD Size Figure 3.11 Plot of Gain of LNA with varying ESD Size 36

52 Table 3.1 Simulated results for S21 and Noise figure for different ESD Size CESD (ff) S21 (db) Noise Figure (db) The affect of ESD Device on Noise Figure The noise figure of the amplifier is also likely to be affected by the presence of ESD Capacitance Cp. This has been measured through simulation using Cadence. Noise Figure is given by Fcla Fnqs From equation Noise Figure has two components. Classical Noise(Fcla) which increases as Cp increases and Non Quasi-static Noise(Fnqs) which decreases as Cp increases. But Fcla is always greater than Fnqs. So Noise Figure of LNA increases with increasing Cp as shown in Figure

53 Figure 3.12 Plot of Noise Figure with Varying ESD Size The performance parameters of LNA degrade with increasing ESD device size as seen from the above simulation. Also it has been pointed out that once the Cp crosses 200fF it is almost impossible to obtain optimal performance of LNA like lowest S11,low noise figure etc. This aspect is the motivation for investigating the condition in which the ESD shifted towards antenna as shown in Figure 3.13 (Case 2) Case 2 : ESD structure at the Antenna Figure 3.13 ESD Device positioned between Antenna and gate inductor Lg 38

54 Figure 3.14 Two stage Impedance Transformation The Circuit schematic with ESD device at the Antenna away from Gate of LNA is shown in the Figure 3.13.Cp denotes parasitic capacitance of the ESD device. Again looking towards the source from the gate of LNA, LNA sees equivalent resistance different from Rs=50Ω at resonance. Using two stage transformation the equivalent impedance is given by Zseq = Rseq + jω 0 Lgeq Where Rseq is given by Rseq = Rs/(1- Rs 2 ω 0 2 Cp 2 ) Effect of ESD structure on Input Matching Again S11 is obtained from real part of Zin. Now Re(Zin) is function of both Lg and Ls. It has been found that in Case 2 both Lg and Ls can be tuned for a given Cp to obtain optimal performance even with Cp s higher than those that may be used in Case 1.For this purpose the graphs of S11 with varying Ls and varying Lg is shown in Figure 3.16 and Figure Just as in Case 1 for given 39

55 Cp the variation of S11 with Ls has been obtained. Ls corresponding to lowest S11 for this Cp has been fixed and Lg is varied. It has been found that variation in Lg can improve S11 in this case unlike in Case 1. Further it is found that even with Cp values much larger than the maximum that could be used in Case 1 it has been possible to obtain fairly low S11.The variation of S11 with Ls and for different Cp s is given in Figure 3.16 for Case 2.For given Ls, S11 variation with Lg is given in Figure From these set of figures it may be seen that tuning Ls alone cannot result in lowest S11.Tuning both Lg and Ls for different Cp s can result in very low S11 without reflections. From the graph of Re(Zin) vs Ls (Figure 3.15) we see that it is possible to obtain input impedances which are closer to 50Ω even with values of Cp greater than 200fF which show that capacitive effects are reduced as we go away from the gate of LNA. In Case 2 one would be able to use ESD devices with higher Cp which imply that protection can be better. 40

56 Figure 3.15 Variation of Real part of Zin with Ls at resonance for different Cp Figure 3.16 Plot of S11 against varying Lg for different Cp 41

57 Figure 3.17 Plot of S11 against varying Ls for different Cp Effect of ESD structure on Noise Figure Again NF of LNA increases witch increasing Cp but at reduced rate. This is because NF is function of Rseq and Rseq variation with increasing Cp is less as we move away from the gate of LNA as shown in Figure Figure 3.18 Plot of Noise Figure against varying ESD Capacitance 42

58 Effect of ESD structure on Power Gain: The gain of LNA again reduced with increasing Cp but at a reduced rate.lna Transducer Gain is given by Variation of R Seq with ESD size for this case is shown in Figure Since variation in R Seq is small gain reduction is less as Cp increases as shown in Figure Figure 3.19 Plot of Rseq against Cp 43

59 Figure 3.20 Plot of Gain against varying Cp Figure 3.21 Plot of Frequency response of LNA for different Cp Table 3.2 Simulated results for S21 and Noise figure for different ESD Size CESD (ff) S21 (db) Noise Figure (db)

60 In order to validate above analysis where we showed that positioning ESD device away from the gate of LNA and between antenna and gate inductor higher level of ESD protection is possible, 2.1GHz LNA with ON chip spiral inductors taken from IBM CSOI7TF Technology kit and Diode protection has been considered. 3.5 Common Source Narrowband LNA Design Low Noise Amplifier (LNA) is the first stage in most receiver architectures. This LNA should meet certain requirements to be useful for an RF system. The most important requirements for an LNA are matching, noise, gain and linearity. Matching is one of the most important requirements of an LNA. As LNA is fed through a 50Ω transmission line coming from the antenna, input impedance of the LNA should be 50Ω to avoid reflections over the transmission line. Noise is another important consideration in the design of an LNA. As LNA is the first stage after the antenna it sets the lower bound on the achievable noise figure of the entire receiver. Hence, design of an LNA with a very low noise figure is crucial. Finally, as in any amplifier, an LNA should have high power gain. Moreover, this high gain is desirable as it improves the SNR of the stages following the LNA. In this section, before going through the details of performance analysis of LNA with ESD Diode protection, a few basic concepts in design of low noise amplifiers (LNAs), are discussed. These concepts include quality factor of inductors and capacitors, Noise Figure (NF), Matching, Linearity and Gain of amplifiers. 45

61 3.5.1 Quality Factor of Inductors An inductor is nothing more than a wire wound or coiled in such a manner as to increase the magnetic flux linkage between the turns of the coil. This increased flux linkage increases the wire s self-inductance (or just plain inductance) beyond that which it would otherwise have been. Inductors are used extensively in RF design in resonant circuits, filters, phase shift and delay networks, and as RF chokes used to prevent, or at least reduce, the flow of RF energy along a certain path. Figure 3.22 Inductor equivalent model The inductor is probably the component most prone to very drastic changes over frequency. Figure 3.22 shows what an inductor really looks like at RF frequencies. Whenever we bring two conductors into close proximity but separated by a dielectric, and place a voltage differential between the two, we form a capacitor. Thus, if any wire resistance at all exists, a voltage drop will occur between the windings, and small capacitors will be formed. Initially, at lower frequencies, the inductor s reactance parallels that of an ideal inductor. Soon, however, its reactance departs from the ideal curve and increases at a much faster rate until it reaches a peak at the inductor s parallel resonant frequency (F r ). Above F r the inductor s reactance begins to decrease with frequency and thus the inductor begins to look like a capacitor. Theoretically, the resonance peak would occur at infinite reactance. However, due to the series resistance of the coil, some finite impedance is seen at resonance. 46

62 Figure 3.23 Plot of Inductance against varying frequency It was mentioned earlier that the series resistance of a coil is the mechanism that keeps the impedance of the coil finite at resonance. Another effect it has is to broaden the resonance peak of the impedance curve of the coil. The ratio of an inductor s reactance to its series resistance is often used as a measure of the quality of the inductor. The larger the ratio, the better is the inductor. This quality factor would be infinite for lossless inductor. Of course, there is no perfect conductor and thus an inductor always has some finite Q. At low frequencies, the Q of an inductor is very good because the only resistance in the windings is the DC resistance of the wire-which is very small. But as the frequency increases, skin effect and winding capacitance begin to degrade the quality of the inductor. At low frequencies, Q will increase directly with frequency because its reactance is increasing and skin effect has not yet become noticeable. Soon, however, skin effect does become a factor. The Q still rises, but at a lesser rate and we get a gradually decreasing slope in the 47

63 curve as shown in Figure Above this point, the shunt capacitance and skin effect of the windings combine to decrease the Q of the inductor to zero at its resonant frequency. The dimensions of inductor are chosen such that its Q is maximum at the frequency of operation. Figure 3.24 Plot of Q of inductor with varying frequency LNA Performance Parameters Impedance Matching Impedance matching is an important and necessary in the design of RF circuits in order to transfer the maximum power from source to its load. In front end of any sensitive receiver it is very important that there is such maximum power transfer, even if there is any loss in the circuit, carrying a weak signal levels cannot be tolerated. While designing such front end circuits uttermost care has to be taken so that each device in the system is well matched to its load. According to maximum power transfer theorem, power delivered to the load is 48

64 maximum when source resistance is equal to load resistance at resonance. The input impedance looking into the gate of LNA is given by Zin=(L g +L s )s + (1/sC gs ) + (g m L s /C gs ) At resonance Zin is purely resistive and is given by Re(Zin)=g m Ls/C gs This resistance must be matched to 50Ω source resistance for maximum power transfer. In the absence of any additional matching network Ls is the only parameter which can be varied to get required match. Since it is difficult to get perfect match of 50Ω and also due to other tradeoffs there is specification on the acceptable reflection which in our design is <-20dB as shown in Figure Figure 3.25 Plot of S11 with varying frequency 49

65 Power Gain Power gain is generally defined as the ratio of the power actually delivered to the load to the power actually delivered by the source. However this definition is not entirely relevant and is difficult to quantify since the source impedance in turn is difficult to specify. For that reason Transducer Gain which is the ratio of average power delivered to the load to maximum available power from the source is defined. As previously discussed the power delivered to the load is maximum when source resistance is equal to load resistance at resonance. The gain of LNA in our design is shown by simulation in Figure Noise Figure Figure 3.26 Plot of S21 with varying Frequency The input of the receiver receives both the main signal and noise. Both noise and signal are present at different points of the receiver. An ideal amplifier amplifies both signal and noise and hence, doesn t change the SNR. However, 50

66 a real amplifier adds extra noise to the signal which is coming from resistive and active elements of the amplifier. This extra noise causes a reduction in SNR. In an RF receiver, the change in SNR is measured through noise factor (F), which is defined as the ratio between SNR at input to SNR at output. A more common term to measure noise performance in RF applications is noise figure (NF) which is simply noise factor expressed in db given by NF=20Log F Noise Figure is always greater than zero. Figure 3.27 Plot of Noise Figure with frequency Linearity and 1dB Compression The linearity of the LNA is another concern that must be taken in account. Linearity of LNA in the operating region is crucial particularly when the input signal is weak such as the case of GSM and CDMA with strong interfering 51

67 signal in close proximity. This is because in such a scenario there is possibility for undesired intermodulation distortion such as blocking and cross modulation.p1db shows at what power level the output power drops 1dB, as a consequence of non-linearities, relative to the theoretical linear power gain. Figure 3.28 Plot of LNA 1dB Compression Third Order Intermodulation (IIP3) Third Order Intermodulation Product or IIP3 determine the ability of LNA to reject unwanted signal. When two sinusoidal signals of same amplitude and slightly different frequency is applied to a non linear system the output in general exhibit some components that are not harmonics of fundamental frequency. Generally IIP3 intercept point must lie beyond 1dB compression point of the LNA. Rule of thumb is IIP3 is 10dB above 1dB Compression point. Figure 3.27 shows IIP3 simulation curves for our LNA design. Table 3.3 lists the simulation results for the 2.1GHz LNA. 52

68 Figure 3.29 Plot of IIP3 for LNA Table 3.3 Simulated Results for LNA Simulation Result Noise Figure (db) 2.94 Gain (db) 18.5 S11 (db) -24 1dB Compression (dbm) -12 IIP3 (dbm)

69 GHz LNA for CDMA standard with ESD Diode Protection In Section 3.4 we concluded that positioning ESD structure at the PAD reduce LNA performance degradation for given ESD size and ESD protection level. So in this section we consider particular case of 2.1GHz LNA designed in section 3.5 for CDMA standard with ESD Diode Protection and study the effect of ESD structure on LNA performance parameters. In the discussions to follow the ESD diodes are positioned at the Antenna away from gate of LNA towards the antenna ESD Diode Figure 3.30 N diffusion in P-well diode(esd NDSX) The diode is one of the most frequently used ESD-protection devices [44,48]. The main reason is that they are very efficient and robust. Furthermore, their characteristics are fairly simple to model and simulate, allowing a reliable sizing of these devices. This is especially important if the size of the ESD device directly affects the performance of the core circuit, as is the case for RF IC s. 54

70 Unlike the forward-biased diode, the reverse-biased diode has high on resistance and high on-voltage. Therefore, power dissipation and internal temperature of the reverse-biased diode are high under high current conditions. Hence, the maximum current carrying capability of this diode is very low and in the order of 0.5 2mA/um, making it unsuitable for ESD protection applications. On the other hand this diode shows small current when used in normal circuit operation, i.e. the voltage across it is VDD. Therefore, a p-n junction diode can be used in such a way that under ESD conditions it is biased in forward biased region while under normal operating conditions is biased in reverse biased region. When diode is used for RF ESD Protection it must have low trigger Voltage, low parasitic capacitance and low ON resistance. Also diode capacitance must be linear in the operating region. The ability to provide a low-voltage trigger voltage,fast turn ON and low ON resistance can be achieved by the following means: a) Use diode elements in the forward bias mode of operation to achieve low turn-on voltage and good current handling capacity. b) Minimize the diode series resistance. c) Minimize the number of diode elements in series for fast turn on and low ON resistance. d) Maximize the number of parallel diode elements for better current handling capacity Diode CV Figure 3.31 shows the CV characteristics of the diode for different number of fingers.the capacitance is fairly linear in operating region of the LNA.Hence the linearity degradation of LNA due to ESD diode is very minimal. 55

71 Figure 3.31 Diode CV Characteristics Characterizing ESD Diode by 100ns TLP: In order to characterize ESD Diode for protection it is run through 100ns TLP for different number of fingers. Figure 3.32 shows Failure current vs voltage graph for diode for different number of fingers. From the graph it can be noted that given diode with 2 fingers can handle maximum current of 1.5A before it fails. Table 3.4 lists the size of ESD diode required for different level of ESD protection. For example for 2KV HBM protection the chosen ESD Diode offer parasitic capacitance of 150fF. 56

72 Figure 3.32 ESD VPNP 100ns TLP Table 3.4 Diode Sizing for HBM ESD Protection HBM (KV) TLP (A) CESD (ff) Area (um 2 )

73 3.7 LNA ESD Diode Co-Design Simulation Results VDD Antenna D1 Lg D2 Figure 3.33 LNA ESD Diode Protection Figure 3.33 shows LNA with Double Diode Protection. From earlier discussions Diodes are positioned at the Antenna away from gate of LNA. Figure 3.34 plots the variation of LNA matching parameter S11 with ESD diode size. 58

74 Figure 3.34 Plot of S11 against varying CESD at 2.1GHz Figure 3.35 Plot of NF against varying CESD at 2.1GHz Figure 3.35 plots the variation of LNA Noise Figure with Diode Size. It can be seen from the figure that the variation in noise figure with ESD capacitance is 59

75 in agreement with the analysis carried put earlier where we assumed ideal capacitors and inductors. Figure 3.36 Plot of Gain against varying CESD at 2.1GHz Figure 3.36 plots variation in LNA Gain with ESD Diode Size. The drop in the gain is very small even with ESD capacitance of 200fF which corresponds to 2KV HBM. Table 3.5 Simulated Results for LNA with ESD Protection NF Cap (ff) Noise Figure 2.94dB Gain(dB) S11-21dB

76 3.8 Conclusion LNA input matching, NF and gain tradeoff with ESD protection level. Large ESD Device Capacitance Cp limits the input match and Gain of LNA. ESD Protection device at the Antenna gives greater freedom to choose ESD Device size since both LNA Gate inductor Lg and Source inductor Ls can be varied to achieve required match. This methodology is essential especially at high frequency of operation where maximum achievable ESD protection level drops considerably with ESD device positioned at the gate of LNA.The analysis is validated by simulation of 2.1GHz LNA with CMOS SOI ESD Diodes from IBM CSOI7TF Technology. 61

77 Chapter 4 MIXED-VOLTAGE TOLERANT IO BUFFER With rapid development of complementary-metal-oxide-semiconductor (CMOS) techniques, the transistor dimension and core supply voltage have been continually scaled down to reduce chip area, to increase operating speed and to reduce power consumption. Nonetheless, the scaled-down transistors also have the limitation of lower maximum tolerable voltage across the transistor terminals (drain, source, gate, and bulk) under vulnerable circuit operating conditions for lifetime concern. In the mixed-voltage I/O buffers, that interface the high-vdd signal environment of the old I/O specifications to low-vdd environment for low power consumption of core circuits, the voltages across transistor terminals should be managed carefully to overcome reliability problems, such as gate-oxide overstress, hot-carrier degradation, and the undesired circuit leakage paths (for the conduction of the parasitic drain-towell pn-junction diode in the main pullup PMOS device). The expected normal lifetime for IC products is generally specified as 5 10 years, which will be affected by different processes and overstress conditions. Degradations caused by hot carriers and gate-oxide overstress are actually time dependent issues, which are also functions of the probability for the happening of overstress condition during circuit operations. When the drain voltage of NMOS device is larger than its gate voltage (for the overstress condition in the following circuits under discussion), the drain avalanche hot carrier injection (DAHC) becomes an important mechanism. For ensuring IC products to meet normal lifetime expectation, reliability problems in both of steady state and transition period should be considered. 62

78 Various approaches[13,18],[20,24] to protect IO Buffer against Overvoltage induced damages in mixed voltage environment have been proposed. At process level dual oxide method was proposed where thick oxide devices were used in the driver buffer. In yet another approach both enhancement and depletion mode MOSFETs provided by the foundry were used in IO Buffer. At circuit level floating N-well technique was proposed to protect mosfets in the IO Buffer during overvoltage condition at the pad. These various approaches have several disadvantages in terms of fabrication cost, reliability issues, area considerations etc which will be covered in detail in later sections. In this dissertation we propose circuit technique implemented with thin oxide devices to overcome gate oxide reliability and leakage issues in IO Buffer operated in mixed voltage environment. 4.1 Mixed-Voltage Condition in IO Design Figure 4.1 a)gate Oxide Over stress b)parasitic PN junction diode Turn ON during Over voltage at the PAD 63

79 When two digital logic devices having different power supply levels are coupled an interface is generally required to prevent damage to transistors in the device having the lower power supply level. In mixed voltage IO design the driver operated at lower supply voltage experience three kind of damages during over voltage condition. First is that the standby current through the PMOS in Figure 4.1 may be large enough to damage the MOS. Under over voltage condition at the pad the drain of PMOS acts as the source and draws very large current. This results in considerable wastage of power. Also the current may be large enough to damage the MOS. Secondly since the N-well is connected to VDD, when overvoltage appear at the pad the drain substrate parasitic diode gets forward biased resulting in substrate leakage current and may lead to latch up issues. Thirdly the NMOS in the driver buffer may be subjected to over voltage stress. Apart from these issues there are other considerations like subthreshold leakage due to body effect in 130nm technology and beyond. The interface circuit should minimize leakage and prevent latch up. With a 3.3V interface, such as PCI-X application, highvoltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1V/2.5-V low-voltage devices in a 130nm CMOS process. A 2.5V device can safely drive its own IO pin during transmit mode. However when IO pin of 2.5V device is being driven by neighboring 3.3V device, the 2.5V device must include protection circuits attached to the IO pin. The protection circuits should be able to shift the voltage at the gate and the n-well of main PMOS in the IO Buffer to PAD voltage so that there are no standby and leakage currents. Also the protection circuit should take care of oxide overstress issues in NMOS of the buffer. 64

80 4.2 Prior Art The I/O circuits of prior arts those attempted to avoid reliability problems due to gate-oxide overstress and hot-carrier degradation in mixed voltage conditions as reported in [13,18],[20,22] suffer from many shortcomings. Figure 4.2 Mixed Voltage Tolerant IO Buffer in Dual Oxide Process Mixed Voltage Tolerant IO Buffer using Dual-Oxide Process Figure 4.2 shows one mixed-voltage I/O buffer with dual-oxide (thick-oxide and thin-oxide) devices and an external n-well bias voltage. For such mixedvoltage interface applications, the dual oxide process provided by foundry is used to avoid the gate oxide reliability problem [11] [13]. Since the thick oxide can sustain higher gate voltage, the devices which have the gate oxide reliability problem can be replaced by the thick-oxide devices to prevent the high-voltage overstress on the thin gate oxide. Therefore, the core circuits are designed with thin-oxide devices to decrease the chip area and power consumption, but the I/O circuits are designed with thick-oxide devices to avoid the gate-oxide reliability issue. In order to avoid leakage current path 65

81 from the I/O pad to the power supply (VDD) through the parasitic drain-towell PN-junction diode in the pull-up PMOS device, the body terminal of the pull-up PMOS must be connected to an extra pad that provides a higher external voltage (VDDH) to bias the body of the pull-up PMOS device. In addition, a gate-tracking circuit is needed to avoid the leakage current path induced by the incorrect conduction of the pull-up PMOS device. Although the traditional mixed-voltage I/O buffer with dual oxide devices and an external n-well bias can be used to solve the aforementioned problems, there are still some limitations in this I/O buffer. Using an external bias voltage needs an extra pad and another power supply (VDDH), the silicon area and the cost of the whole system are increased. The threshold voltage of the thickoxide devices is so high that their driving capacities are decreased when their gates are controlled by the pre-driver circuit with low-voltage devices. In addition, because the body terminal of the pull-up PMOS device is connected to a higher voltage (VDDH), the threshold voltage of the pull-up PMOS device is also increased due to the body effect. Because the driving capacity is decreased, the larger device dimension is needed for the pull-up PMOS device to support the desired driving specifications. In turn, it increases the silicon area for such I/O buffer. Therefore, the mixed-voltage I/O buffer with dualoxide devices and an external n-well bias is unsuitable for the low-cost commercial ICs. 66

82 Figure 4.3 Mixed Voltage Tolerant IO Buffer using Depletion MOS Mixed Voltage Tolerant IO Buffer Using Depletion MOS The mixed-voltage I/O buffer with a depletion PMOS device is drawn in Figure 4.3 [16].The depletion PMOS device MP2 in the I/O buffer is used as the gate-tracking circuit. In the tri-state mode, if the input signal at I/O pad is 5 V, the gate voltage of transistor MP0 is biased at 5 V through the depletion PMOS device MP2 to avoid the undesired leakage current path through the transistor MP0. This I/O buffer uses an extra pad that is connected to 5V power supply (VDDH) to avoid the undesired leakage current path through the parasitic drain-to-well pn-junction diode. However, using the depletion device increases mask layer and process modification. Thus, the fabrication cost of such I/O buffer design will be increased. In addition, using the extra n-well bias (VDDH) not only degrades the driving capacity of output device MP0 due to the body effect, but also increases the system cost. 67

83 Figure 4.4 Mixed Voltage Tolerant IO Buffer using stacked PMOS Mixed Voltage Tolerant IO Buffer Using Stacked Devices Figure 4.4 re-draws the mixed-voltage I/O buffer with stacked pull-up PMOS devices [14]. Signal OE is the output-enable control signal. In the transmit mode, transistor MN1is turned on and transistor MP2 is turned off, so that this I/O buffer drives the I/O pad according to the output signal Dout. In the tristate input mode, transistor MN1 is turned off and transistor MP2 is turned on by the control signal OE at logic zero. If the input signal at the I/O pad is 5 V, the gate voltage of transistor MP1 and the floating N-well are pulled up to 5 V through transistor MP2 and the parasitic drain-to-well pn-junction diode in transistor MP0 to prevent the undesired leakage current paths from I/O pad to power-supply voltage (VDD), respectively. Although this I/O buffer is simple, transistors MN0, MN1, and MP2 have the gate-oxide reliability problem in the tri-state input mode when the input signal has a 5V voltage level. Besides, because the stacked PMOS devices with the floating n-well to prevent the leakage current is applied to this I/O buffer, the PMOS devices in stacked configuration occupy more silicon area. 68

84 4.2.4 Mixed Voltage Tolerant IO Buffer Using Thin Oxide Devices Figure 4.5 shows the mixed-voltage I/O buffer realized with thin oxide devices, a dynamic N-well bias circuit, and a gate-tracking circuit [10], [14] [18]. The stacked nmos devices, MN0 and MN1, are used to avoid the highvoltage overstress on their gate oxide. In a 0.25um CMOS process, the powersupply voltage (VDD) is 2.5 V and the threshold voltage of the devices is about 0.6 V. Because the gate terminal of transistor MN0 is connected to 2.5 V (VDD), the drain voltage of transistor MN1 is about 1.9V when the input signal at the I/O Figure 4.5 Mixed Voltage Tolerant IO Buffer using thin oxide devices pad is 5 V in the tri-state input mode. Hence, the gate drain voltages and the gate source voltages of the stacked NMOS devices, MN0 and MN1, are limited below 2.5 V even if the input signal at the I/O pad is 5 V. Therefore, the stacked nmos devices, MN0 and MN1, can solve the gate-oxide reliability problem. The gate-tracking circuit shown in Figure 4.5 is used to prevent the leakage current path due to the incorrect conduction of the pull-up PMOS device when the input signal is higher than VDD. In the transmit mode, the gate-tracking circuit must transfer the signal from the pre-driver circuit to the 69

85 gate terminal of the pull-up PMOS device exactly. In the tri-state input mode (receive mode) with 5V input signal, the gate-tracking circuit will charge the gate terminal of the pull-up PMOS device to 5 V to turn off the pull-up PMOS device completely, and to avoid the leakage current from the I/O pad to the power supply (VDD). On the contrary, the gate-tracking circuit will keep the gate terminal of the pull-up PMOS device at 2.5 V to turn off the pull-up PMOS device completely, and to prevent the overstress on the gate oxide of the pull-up PMOS device, when the input signal at the I/O pad is 0 V in the tristate input mode. The dynamic n-well bias circuit shown in Figure 4.5 is designed to prevent the leakage current path due to the parasitic drain-to-well pn-junction diode in the pull-up PMOS device. In the transmit mode, the dynamic n-well bias circuit must keep the floating n-well bias at 2.5 V. So, the threshold voltage of the pull-up PMOS device isn t increased by the body effect. In the tri-state input mode with a 5V input signal, the dynamic n-well bias circuit will charge the floating n-well to 5 V to prevent the leakage current from the I/O pad to the power supply (VDD) through the parasitic pn-junction diode. When the input signal at the I/O pad is 0 V, the dynamic n-well bias circuit will bias the floating n-well at 2.5 V. Because the floating n-well is clamped to 2.5Vor 5V through the parasitic diodes by some dynamic n-well bias circuits [14],[15], [17], the voltage on the floating n-well will be a little lower than 2.5 V or 5 V. The lower floating n-well voltage results in the lower threshold voltage of the pull-up PMOS transistor. Thus, the subthreshold leakage current becomes large when the pull-up PMOS transistor is in off state. If the given process has serious subthreshold leakage issue, such as the 0.13um or below processes, the dynamic n-well bias circuit must clamp the floating n-well directly to the desired voltage level by the MOS transistor to decrease the subthreshold leakage. Also the voltage level of the floating n-well 70

86 may be coupled with transient noise when the operating frequency of the mixed-voltage I/O buffer becomes higher. Figure 4.6 Modified Mixed Voltage Tolerant IO Buffer using thin oxide devices Modified Mixed Voltage Tolerant IO Buffer Using Thin Oxide Devices Another mixed-voltage I/O buffer realized with only thin oxide devices is redrawn in Figure 4.6 [18]. The gate-tracking circuit in Figure 4.6 is composed of transistors MN3, MN4, MP2, MP3, and MP4. The dynamic n-well bias circuit in Figure 4.6 is formed by transistors MN5, MP5, MP6, and MP7. Besides, the body terminals of all PMOS transistors in the gate-tracking circuit and the dynamic n-well bias circuit are connected to the floating n-well. Such I/O circuit shown in Figure 4.6 can overcome the gate-oxide reliability problem and avoid the undesired leakage paths. However,too many devices are used to realize the desired functions of the gate-tracking circuit and the dynamic n-well bias circuit. More devices used in the mixed-voltage I/O buffer often cause more complex metal routing connection in the I/O cells. 71

87 4.2.6 Modified Mixed Voltage Tolerant IO Buffer Another conventional mixed-voltage I/O buffer with the gate-tracking circuit and the dynamic n-well bias circuit is shown in Figure 4.7 [20-22].The limitations of voltage difference within 1.1xVDD across the terminals of each transistor can be satisfied by the circuit in Figure 4.7 under steady state. However, during the transition from receiving 2xVDD input signal to transmitting 0V output Figure 4.7 Modified Mixed Voltage Tolerant IO Buffer signal, the Vds of transistors MN0 and MN3 will be much higher than VDD. The drain-to-source voltages of MN0 or MN3 start to increase from VDD, since the source terminal is pulled down faster than the drain terminal at the beginning of this transition period. The transistor MP5 also has larger Vgs, since its source and gate are connected to the drain and source of transistor MN0, respectively. 72

88 The above techniques to overcome gate oxide reliability, hot carrier degradation and leakage issues in IO Buffer operated in mixed voltage environment either use costly process, consume more silicon area or use floating well technique which may be dangerous from noise point. To alleviate the aforementioned reliability problems during both steady state and transition period in the mixed-voltage I/O buffer with only 1xVDD devices, a new mixed voltage-tolerant I/O buffers with novel transmitting circuit and new gate control circuit is proposed in this work. 4.3 Proposed Mixed Voltage Tolerant IO Buffer Figure 4.8. shows block diagram of an interface circuit proposed in this work. A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit and a pull up protection circuit. During receive mode when a high voltage is applied to the IO pad, the pull-up protection circuit drives the gate of the pull up transistor to the high IO pad voltage to ensure that no Figure 4.8 Block Diagrm of the Proposed Circuit 73