Page 1 ATLCE - G2 17/06/2013. Analog and Telecommunication Electronics 2013 DDC 1. Politecnico di Torino - ICT School

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1 Politecnico di Torino - CT School Lesson G2: Linear voltage regulators Analog and Telecommunication Electronics G2 - Linear voltage regulators» Shunt regulators» Series regulator» ntegrated regulators»ldo Shunt regulator Zener diode oltage reference Series regulator Transistor and Op Amp circuits Current limit ntegrated regulators Low DropOut (LDO) regulators eferences: book1 (Sedra): Ch 3.5, /06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Unregulated output voltage Output voltage regulation With the transf.-diode-c scheme, the output voltage Has ripple, related with output current Changes when load current changes Changes when the mains voltage changes A voltage regulator can deliver constant O When load current changes: load regulation S L = Δ O Δ L» Equivalent output resistance o = S When input voltage changes: in/out regulation Si = Δ O /Δ educe the ripple (is considered as a change of ) L i OLTAGE EGULATO o L 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Shunt and series regulation Shunt regulator Goal of regulator constant o, for changes in, L Two basic techniques Build a current divider, change the partition ratio using the parallel branch p shunt regulators Build a voltage divider, change the partition ratio using the series branch s series regulators i P L L o o Basic shunt regulator: the zener diode ery simple Low efficiency, suitable for low power oltage reference circuits are shunt regulators (low current capability) Current in the zener diode Higher than zmin Less that zmax (to limit power dissipation) Constant input current Wasted power! A benefit for some applications dc pol z 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Page DDC 1

2 Zener diode i(v) characteristic Zener diode i(v) operation z and z have inverse sign from d, d of standard diodes Z z and z have inverse sign from d, d Standard diodes operates in forward/reverse bias» Breakdown is a fault condition Zener operates in reverse bias (breakdown) d z z Zener operation reverse bias Z d About 0,6 Zener voltage 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Zener diode equivalent circuit Zener diode operating point Z0 : Z for = 0 (linear model) Z : Δ/Δ (actually differential r Z ) zmin: minimum current to exit knee region Pdmax (or zmax): limited by temperature rise Z0 z Slope Δ/Δ = z Z0 Select, sign as for diodes Draw characteristic of left-side circuit (su s) Draw Zener () characteristic Operating point at intersection Evaluate effect changes in su or s f Dz operates in breakdown o regulation su/s s su Operating point su 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Example 1: zener regulator Example 1: results Design a shunt regulator from these specs: o = 5 (as close as possible); o = ma Available zener diode: zo = 5, z = 10 ohm, zmin = 5 ma Pdmax = 2 W Evaluate Drop resistance (min/max) o min/max (any combination of, o, ) Pdmax on and Zener Discuss selection min/max o Drop resistance (min/max) min = max = o min/max (any combination of, o, ) omin = ( = min, o = omax, = max) omax = ( = max, o = omin, = min) Pdmax on and Zener Pdmax = PdZmax = Discuss selection min/max Low values for increase the current in the -Dz, causing high power dissipation High values give lower dissipation, but could limit the max out current capability 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Page DDC 2

3 Series regulators Series regulator basic scheme Need a controlled variable resistor Can use BJT or MOS Current amplifier from a reference or shunt regulator Feedback circuits (voltage reference and Op Amp) Always o < All regulators require a minimum drop voltage (drop)» losses on regulator; low efficiency LDO (Low Drop Out) regulators for better efficiency Available as commodity Cs Standard voltages (5, 6, 9, 12, ) ariable voltage The series regulator operates as a controlled variable resistor The variable is a BJT or MOS transistor The controller CNT compares output o with a reference r i o r CNT o 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Example of series voltage regulator Basic -Zener regulator egulation by current steering between Zener and load Limited current capability (zmax) Add Emitter follower (CC) as current amplifier Output voltage o = z be same Sv Allows large load current change Δo = Δz β lower o Lower bound on o from gm (hie) Feedback voltage regulator Control circuitry includes a reference and an amplifier Compare (a fraction β) the output voltage o with the reference r Drive the control element to keep O S1 β o = r r O β Needs a voltage reference β U 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC oltage reference circuits Provide a known and stable voltage ndependent from Power Supply, temperature, aging, load, equired for voltage regulators and measurement circuits Use Zener diode or Band-gap reference The amplifier isolates the load from the reference pol dc dc pol EF EF Example of band-gap voltage reference Zener diode Zener voltage changes with temperature (inversion at about 6) Zener pair to compensate temperature changes Need voltages higher than 9 Not the best choice for high precision and stability Band-gap reference Uses combination of be and T Op Amp Can operate from low voltages A 3-pin regulator with low current but precise and stable ntegrated within 3-pin regulators z 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Page DDC 3

4 The BJT is connected as a CC power stage The feedback loop makes β O = ref Drop from to o: ao be Op Amp and BJT oltage divider on ref The feedback loop makes O = β ref Drop from to o: ao be Op Amp and BJT o < ref β U O O β EF EF 2 EF 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Op Amp and Darlington pair Current limit A darlington pair has higher current gain Drop from to o: ao 2 be EF O Current sense resistor s As s rises above 0,7, Q3 steers current away from Q1, Q2. External current sense at least 4 pins ariable current limit Current sense differential amplifier ariable threshold External sense/divider One additional pin (tot 5) ref Q3 Q1 s Q2 o 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Load current sense NA differential amplifier High side Sense inside the regulator Needs differential amplifier (matched components)» nput common mode close to supply Low side eferred to GND, no need for differential amplifier Load not directly to GND Additional pins on regulator Precise differential amplifiers need matched resistors NA circuit: used to sense low differential voltage close to supply No need for matched components S 1 High side with NA circuits Differential amplifier for high side current sense No need for matched components Can handle common mode voltage near S (2/1) 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Page DDC 4

5 Efficiency of series linear regulators Losses caused by voltage drop and leakage current. Usually leakage current much less than output current POUT OUT N LEAK PN N N To improve efficiency educe oltage drop Low Drop-Out (LDO) educe leakage current Q Low power r and control Move to switching regulators OUT N Drop-out voltage on regulator Transistors in a series regulator requires ce margin to operate in active region > o BE1 BE2 A power BJT has BE = 1, therefore > o 1,7 The Op Amp adds further internal drop AO from positive supply to output (from 1 to a few m): > o 1,7 AO = o H, the headroom voltage H represents the minimum drop-out voltage on the series regulator Usually H is about 2-3 The power dissipated on regulator depends on headroom voltage: Pd = H x omax 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Standard regulator Low DrOpout (LDO) with pnp BJT Drop-out is related with Op Amp output voltage range: rail-to-rail Op Amps provide Base drive b = s Power transistor BE. A minimum about 1. Using MOS does not reduce drop-out GSON > BE charge pump for gate driving (g = 0) i ref i ref u 1 u 1 Output stage becomes CE No longer a voltage follower, amplifier with gain Keep negative feedback (switch /- Op Amp pins) Gain depends on load, critical stability Analyze the loop:» Op Amp, CE stage, feedback network Using LDO Manufacturers specify type and value of output capacitor Keep value and type of capacitor, to get the required ES! ref 1 2 u ZL 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC ssues with LDO regulators PNP have lower current gain (β) The Op-Amp must sink a high current, related with the load High leakage, decreased regulator efficiency Not best for variable output voltage regulators Darlington to increase the current gain, no longer LDO Good design rules nput capacitor C1 to compensate wire inductance Diode to protect from fast switch of at input (may cause o > ) C 1 C 2 o emote sense: four-wire Output current causes voltage drop on power wires Use separate sense wires connected directly to the load n sense wires no current, therefore no voltage drop i s D1 D2 L O 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Page DDC 5

6 EM sensitivity ariable o from 3-pin regulators emote sense wires can pick EM interference and noise (e.g. from 50Hz mains). Use differential signals and twisted pair for remote sense The 3-pin regulator keeps a constant preset voltage p between OUT and COMMON pins. f voltage of common pin is c = βo (rather than GND), we get o = p c c comes from o through a voltage divider 1/2 c = βo = o 2/(1 2) o = p 1/(1 2) N OUT s o The quiescent current Q adds a (small) drop on 2 2 = Q reg /1 o =p 2 2 o =p 1/(12) Q 2 COMMON Q 2 c 1 p o 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Commercial voltage regulator 78xx data sheet Power supply regulators are available as standard Cs Linear regulators: the 78xx family (positive) Xx = output voltage High power package Max current related with case» 50 ma 5 A Other devices 79xx family: negative 317 family: variable output LM9076 LDO shutdown delayed reset 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC 78xx data sheet LDO regulator with commands 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Page DDC 6

7 Numeric example Lesson G2 final test Goal: 5, 1A PSU with linear regulator Draw complete block diagram without and with regulator Define specs for unregulated voltage (e.g: 8dc, 1r, ) Evaluate parameters for transformer, diodes, capacitor Evaluate Sv and o Add zener regulator; Define required zener parameters Evaluate Sv and o Add power transistor (CC) Evaluate Sv and o Select suitable 3-pin regulator Compare Sv and o Describe the difference between parallel and series regulators. Draw an example of parallel regulation circuit. Which are the benefits of feedback regulators? Explain how to get output voltage lower than reference voltage with a feedback regulator. Describe a current limiter circuit. Describe operation of foldback current limiters Motivate and describe the 4-wire technique for remote voltage sensing. Describe high-side current sensing with NA. Discuss benefits and problems of LDO regulators. 17/06/ ATLCE - G DDC 17/06/ ATLCE - G DDC Page DDC 7