AOZ8102. Ultra-Low Capacitance TVS Diode Array. Features. General Description. Applications. Typical Application

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1 Ultra-Low Capacitance TS Diode Array General Description The is a transient voltage suppressor array designed to protect high speed data lines from SD and lightning. This device incorporates eight surge rated, low capacitance steering diodes and a TS in a single package. During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground. They may be used to meet the SD immunity requirements of IC , Level 4 (±15k air, ±8k contact discharge). The TS diodes provide effective suppression of SD voltages: ±20k (air discharge) and ±20k (contact discharge). The comes in a RoHS compliant DFN-6 1.6mm x 1.6mm package and is rated over a -40 C to +85 C ambient temperature range. The is compatible with both lead free and SnPb assembly techniques. The small size, low capacitance and high SD protection makes it ideal for protecting high speed video and data communication interfaces. Features SD protection for high-speed data lines: IC , level 4 (SD) immunity test ±20k (air discharge) and ±20k (contact discharge) IC (Lightning) 3A (8/20µs) Human Body Model (HBM) ±20k Small package saves board space Low insertion loss Protects four I/O lines Low capacitance from I/O to GND: 1.0pF Low clamping voltage Low operating voltage: 5.0 Pb-free device Halogen free Applications USB 2.0 power and data line protection ideo graphics cards Monitors and flat panel displays Digital ideo Interface (DI) 10/100/1000 thernet Notebook computers Typical Application USB Host Controller R T R T BUS +5 Downstream Ports BUS D+ D- GND R T R T +5 BUS D+ D- GND Figure 1. 2 USB High Speed Ports Rev. 1.4 August Page 1 of 9

2 Ordering Information Part Number Ambient Temperature Range Package nvironmental DI -40 C to +85 C 1.6mm x 1.6mm DFN-6 RoHS Compliant Green Product AOS Green Products use reduced levels of Halogens, and are also RoHS compliant. Please visit for additional information. Pin Configuration CH1 1 6 CH4 NC 2 5 P CH2 3 4 CH3 DFN-6 (Top iew) = GND PAD Absolute Maximum Ratings xceeding the Absolute Maximum ratings may damage the device. Parameter P N Peak Pulse Current, t P = 8/20µs Storage Temperature (T S ) SD Rating per IC , Contact (1) SD Rating per IC , Air (1) SD Rating per Human Body Model (2) Rating 6 3A -65 C to +150 C ±20k ±20k ±20k Notes: 1. IC discharge with C Discharge = 150pF, R Discharge = 330Ω. 2. Human Body Discharge per MIL-STD-883, Method 3015 C Discharge = 100pF, R Discharge = 1.5kΩ. Maximum Operating Ratings Parameter Rating Junction Temperature (T J ) -40 C to +85 C Rev. 1.4 August Page 2 of 9

3 lectrical Characteristics T A = 25 C unless otherwise specified. Symbol Parameter Diagram I PP CL Reverse Peak Pulse Current Clamping I PP I RWM Working Peak Reverse oltage I F I R Maximum Reverse Leakage Current BR I F F Breakdown oltage Forward Current Forward oltage CL BR RWM I R IT F P PK C J Peak Power Dissipation R = 0 and f = 1MHz I PP Specifications in BOLD indicate a temperature range of -40 C to +85 C. Symbol Parameter Conditions Min. Typ. Max. Units RWM Reverse Working oltage Between pin 5 and 2 (4) 5.5 BR Reverse Breakdown oltage I T = 1mA, between pins 5 and 2 (5) 6.6 I R Reverse Leakage Current RWM = 5, between pins 5 and µa F Diode Forward oltage I F = 15mA CL Channel Clamp oltage Positive Transients Negative Transient I PP = 1A, tp = 100ns, any I/O pin to Ground (3)(6)(8) Channel Clamp oltage Positive Transients Negative Transient Channel Clamp oltage Positive Transients Negative Transient I PP = 5A, tp = 100ns, any I/O pin to Ground (3)(6)(8) I PP = 12A, tp = 100ns, any I/O pin to Ground (3)(6)(8) C j Junction Capacitance R = 0, f = 1MHz, between I/O pins (3)(7) pf R = 0, f = 1MHz, any I/O pin to Ground (3)(7) pf ΔC j Channel Input Capacitance Matching R = 0, f = 1MHz, between I/O pins (3)(6) 0.03 pf Notes: 3. These specifications are guaranteed by design. 4. The working peak reverse voltage, RWM, should be equal to or greater than the DC or continuous peak operating voltage level. 5. BR is measured at the pulse test current I T. 6. Measurements performed with no external capacitor on P (pin 5 floating). 7. Measurements performed with P biased to 3.3 olts (pin 3.3). 8. Measurements performed using a 100ns Transmission Line Pulse (TLP) system. Rev. 1.4 August Page 3 of 9

4 Typical Performance Characteristics Normalized Input Capacitance Forward oltage () Typical ariation of C IN vs. R ( P = 3.3, f = 1MHz, T = 25 C) Input oltage () Forward oltage vs. Forward Current (t period = 100ns, t r = 1ns) Forward Current (A) Clamping oltage, CL () Insertion Loss (db) Clamping oltage vs. Peak Pulse Current (t period = 100ns, t r = 1ns) Peak Pulse Current, I PP (A) I/O Gnd Insertion Loss (S21) vs. Frequency ( p = 3.3) Frequency (MHz) 0-20 Crosstalk (I/O-I/O) vs. Frequency ( pp = 3.3) SD Response (8k Contact per IC ) ertical: 20/div, Horizontal: 10ns/div) Insertion Loss (db) Frequency (MHz) Rev. 1.4 August Page 4 of 9

5 Application Information The TS is design to protect four data lines from fast damaging transient over-voltage by clamping it to a reference. When the transient on a protected data line exceed the reference voltage the steering diode is forward bias thus, conducting the harmful SD transient away from the sensitive circuitry under protection. PCB Layout Guidelines Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines. The location of the protection devices on the PCB is the simplest and most important design rule to follow. The devices should be located as close as possible to the noise source. The placement of the devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the device. Long signal traces will act as antennas to receive energy from fields that are produced by the SD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for SD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC s signal ground can cause ground bounce. The clamping performance of TS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces. The PCB layout and IC package parasitic inductances can cause significant overshoot to the TS s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design. The ultra-low capacitance TS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Good circuit board layout is critical for the suppression of SD induced transients. The following guidelines are recommended: 1. Place the TS near the IO terminals or connectors to restrict transient coupling. 2. Fill unused portions of the PCB with ground plane. 3. Minimize the path length between the TS and the protected line. 4. Minimize all conductive loops including power and ground loops. 5. The SD transient return path to ground should be kept as short as possible. 6. Never run critical signals near board edges. 7. Use ground planes whenever possible. 8. Avoid running critical signal traces (clocks, resets, etc.) near PCB edges. 9. Separate chassis ground traces from components and signal traces by at least 4mm. 10. Keep the chassis ground trace length-to-width ratio <5:1 to minimize inductance. 11. Protect all external connections with TS diodes. Rev. 1.4 August Page 5 of 9

6 CC Reset Clock I/O GND SIM SIM Card Port Connection I 1394 PHY TPBIASx TPAx+ 1μ 56Ω 56Ω I 1394 Connector TPBx+ GND 56Ω 5.1kΩ 56Ω 270p I1394 Port Connection TRD0+ thernet Controller RJ45 Connector TRD3+ TPAx- TPBx- TRD0- TR+ TR- TRD2+ TRD2- TRD3-10/100 thernet Port Connection Rev. 1.4 August Page 6 of 9

7 Package Dimensions, DFN 1.6mm x 1.6mm, 6L D b e 1 Pin #1 Dot by Marking 1 1 2e Ref. TOP IW L BOTTOM IW R, Pin #1 ID A A1 c SID IW RCOMMNDD LAND PATTRN Dimensions in millimeters Symbols A A1 b c D 1 e Min Nom RF BSC Max L R Dimensions in inches Symbols A A1 b c D 1 e L R Min Nom Max RF BSC Note: 1. Controlling dimension is millimeter. Coverted inch dimensions are not necessarily exact Rev. 1.4 August Page 7 of 9

8 Tape and Reel Dimensions, DFN 1.6mm x 1.6mm, 6L Carrier Tape P1 P2 D0 K0 B0 2 1 T Ref. 3 P0 A0 Feeding Direction UNIT: mm Package DFN 1.6x1.6 A B K D P P P T 0.20 Reel W1 S K M N H UNIT: mm Tape Size 8mm Reel Size ø149 M ø179.0 ±0.50 N 55.0 ±0.50 W /-0.0 H /-0.0 S 1.5 Min. K 10.1 Min. R 2.7 ±0.20 Leader / Trailer & Orientation Trailer Tape 300mm Min. Components Tape Orientation in Pocket Leader Tape 500mm Min. Rev. 1.4 August Page 8 of 9

9 Part Marking DI (1.6 x 1.6 DFN) BWL Product Number Code Assembly Lot Code Week Code Alpha & Omega Semiconductor reserves the right to make changes to this data sheet at any time without notice. LIF SUPPORT POLICY ALPHA & OMGA SMICONDUCTOR PRODUCTS AR NOT AUTHORIZD FOR US AS CRITICAL COMPONNTS IN LIF SUPPORT DICS OR SYSTMS. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Rev. 1.4 August Page 9 of 9