Certain deviations must be made from this designation scheme during the configuration of a network, (see configuring manual Communication P32).

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1 2 Master Program 2.1 Basics The master program (MP) describes the system hardware configuration: the utilized rack, the allocation (the utilized boards) and the bus structure. The distribution of the total task onto the processor modules, as well as the data exchange between the processor modules, are also specified by the master program. The following blocks are available to the master program: rack, boards and sub--modules. Sub--modules are components, that are located on a board and therefore do not occupy their own rack slot. The boards can be sub--divided into processors, peripherals, coupling memory and special peripheral boards Designation Scheme Each master program must describe a rack and all the boards and sub--modules located in it. The block names can be defined by the designer without restrictions, with the exceptions of the restrictions for the processor modules. It is recommended to allocate the names according to the following designation scheme for equipment components: Rack : Axxx xxx 3 Digits, i.e. 100 Processor : Dxx_Pn xx Slot Number. n = Processor Number. Board : Dxx xx Slot Number. Sub--Module: Dxxy xx Slot Number. y = Plug Connector Number. The racks are sequentially numbered within a project (i.e. 100, 101, etc.). The slot designates the number of the slot, on to which the corresponding board is configured ( ). The plug connector number represents the last number of the plug connector, on to which the corresponding sub--moduleis installed ( 0 forthe plugconnector X50 -- EPROM, 1 for the plug connector X01 and 2 for plug connector X02 -- serial interfaces). Certain deviations must be made from this designation scheme during the configuration of a network, (see configuring manual Communication P32). A special name convention applies for processor modules. The module name must have a length of 6 characters, whereby the last three characters must be an underscore, the letter P and the logical processor number n = The logical processor number appears in the 7 segment display of the operating processor module. Examples for the processor module names: D01_P1, D04_P Modes of Operation There are two principally different modes of operation of a rack in the version V 4.0 (see diagrams 2.1 and 2.2): Siemens AG Release

2 Constellation 1: Mixed mode signifies: 0 to 8 P16, with any number of P32, not MM4. (also i.e. 8 P32 with MM21). 32 Bit Address Space C Bus CSH11 (16 kb) 16 Bit Address Space MM11/ MM21/ CS11 CS21 P16/ MM3 P32 Clock (MM3) EA11 CS7 EP22 CS4 EB11 (64 kb) EM11 L Bus 32 Bit Address Space Diagram 2.2: Mixed Mode Basic Architecture Memory Object Standard Peripheral Cannot be Utilized Special Peripherals 16 Bit A rack is configured and operated in one of the two versions Mixed (see above) or P32 Modes (see below). The compiler decides, dependent upon the configured constellation, which of the two versions are present and sets a corresponding flag for the system. Constellation 2: Pure P32 mode signifies: 1 to 8 P32 with MM4. Without MM4 mixed mode valid; MM3 utilized as a clock (standard peripherals). 3 MB Special Perpherals 32 Bit MM4 Memory 2 M Byte Address Space Distribution (see far left) CSH11 (64 kb) 32 Bit Address Space C Bus 16 Bit Address Space P32 L Bus MM4 MM3 CS11 Clock (MM3) EA11 EB11 EM11 CS21 EP22 Address Space Distribution (as above) CS7 (64 kb) 32 Bit Address Space Diagram 2.3: P32 Mode Basic Architecture Memory Object Special Peripherals 16 Bit Special Peripherals 32 Bit Cannot be Utilized Standard Peripherals The special peripheral boards (CSH11, CS7), designed for the pure P32 mode, are set for the expanded address space and can be utilized with a larger memory than can be utilized in the mixed mode (CSH11); the CSH11 can be operated with a memory of 64 k byte, allocates 256 k byte in the memory) Release Siemens AG

3 2.2 Rack Allocation (Arrangement Drawing) The board and its sub--modules must be configured for each installed slot. Every module is defined with a user name according to the name rules and possibly the conventions mentioned above. Specify each non--installed sub--module with 0, when fewer sub--modules as the maximum are installed on a board. Slots can be left free, when no board is to be installed. Therefore the arrangement drawing is an exact mapping of the rack configuring. If the communication bus ( C bus) is to be utilized, then processor modules with a C bus interface (i.e. PM3, PM16) and a C bus coupling memory module must be utilized. A C bus processor module must be installed in slot 1. The C bus coupling memory module must be installed in front of all the other processor modules; the best location is directly next to the first processor module. If several processor modules are located on a local bus, that are to exchange data with one another, then an L bus coupling memory is necessary on the L bus. A separate L bus coupling memory module must be installed in front of the second processor module, when processor boards without integrated L bus coupling memory are to be utilized. The best location for the L bus coupling memory is directly next to the first processor module. ~ Only one coupling memory is to be configured per rack and bus. Exception: The board MM3 can be operated as a radio clock (no coupling memory!) as an addition to the coupling memory MM4 in pure P32 mode Initialization of the Boards The initialization of each passive board (not processor) is implemented via a processor module, installed to the left (lower slot number). A prerequisite is the possession of the same bus connector ( L or C bus) and the capability of initializing this board, since boards exist that are only capable of initializing P16 or P32 processors (see diagram 2.3 or 2.4). Therefore ensure, during the configuring, that these types of boards are installed to the left of those boards that can only be allocated a P16 or P32 processor. Violations of this rule are rejected by the MP compiler with an error message (i.e. a P16 processor has not been installed to the left of an EM13). The MP compiler carries out the assignment of the boards to the processor modules and the designer can assume, when the MP--COP run is error free, that the configured board configuration will in principle run up. Siemens AG Release

4 P16: P32: PT1 PT20 PT20G PT20M PG16 PG26 PM16 PS16 PM3 PT31 PT32 P16 P32 P16 and P32 CS3 CS41 CS51 CS61 DPM EM13 MS41 MS45 SS1 SS2 SS3 EA12 EB11 EM11 MM11 MM21 MM3 SR4 SR7 SR8 SR81 SR82 SR83 SR9 CSH11 CS11 CS21 CS7 SS4 SS5 SS51 EP22 IS_1 IS_2 IS_3 MS5 MS55 MM4 Diagram 2.4: Overview of the Board Assignments, Version Release Siemens AG

5 P16: P32: PT1 PT10 PT20 PT20G PT20M T300 PG16 PG26 PM16 PS16 P16 P32 PM3 PT31 PT32 PM4 CS3 CS41 CS51 CS61 CSZ DPM DPZ EM13 MS41 MS45 MS47 MS48 MS300 SS1 SS2 SS3 SS31 EA12 EB11 EM11 P16 and P32 MM11 MM21 MM3 SR4 SR6 SR12 SR24 SR81 SR82 SR83 CSH11 CS11 CS21 CS12 CS13 CS14 CS22 CS7 SS4 SS5 SS51 EP22 IS_1 IS_2 IS_3 MS5 MS55 MM4 IT41 IT42 Diagram 2.4: An Overview of the Board Assignments, Version 4.2. Siemens AG Release

6 2.2.2Daisy Chain Jumpers Processor modules, that exchange data with one another on the L or C bus, must be connected to one another via daisy chain jumpers of the corresponding bus. This connection is made when board connectors exist at all slots between the processor modules, since each bus connector jumpers this line. This is not the case on the second slot of double width boards, such as processor modules. Therefore daisy chain jumpers must be inserted at these empty slots, in order to connect the daisy chain link. Please take note that the majority of peripheral boards do not possess a C bus plug connector and therefore require a daisy chain jumper at the corresponding slots at which the peripherals boards are installed and when data exchange is to take place via the C bus. The arrangement drawing of the graphical MP documentation indicates where daisy chain jumpers are to be installed Bus Termination Connectors Each back plane bus ( L and / or C bus), existing in a rack, must be configured with a bus termination plug connector (resistor) SR17 by the user. The coupling memory boards MM11 and MM21 have this type of termination resistor integrated for the corresponding bus. Therefore utilization of these boards do not require the separate installation of a termination resistor. 2.3 Configuring the Boards (Module Parameter Drawing) 2.3.1Dimension Specifications All dimension specifications, utilized on a rack, must be specified in the DIM list of the module parameter drawing (see user manual STRUC V 4.0). The dimension specifications can contain a maximum of 8 characters. Lower case and upper case letters are internally handled in the same manner, this signifies that i.e. [MIN] = [min]. Dimension specifications, utilized in the signal attributes LOG 1 and LOG 0 must be sequentially inserted in pairs, i.e. in the sequence LOG 1, LOG Connector Identifier There are 3 different possibilities available for the connector identifiers: = Assignment connectors, < Hardware addresses for inputs and > Hardware addresses for outputs Assignment Connectors PIJ IJ1, IJ2 SFJ PRX The name of the interrupt processing function packet is inserted here. The name of a maximum of 16 interrupt processing function packets are entered here for P32 processors. The user can specify an FP, that implements a system error handling with interrupt type processing. Currently not implemented. The user must specify an FP here, when he is to configure central receive blocks, (name must start ) Release Siemens AG

7 PJ1...PJ8 PTX All FP s (a maximum of 8 for P16 or 64 for P32), that are cyclically processed in sampling times (permanent processing FP), must be specified here. The user must specify an FP here, when he is to configure central transmit blocks (name must start ). ILS, ICS Specifications regarding the processor module synchronization are possible here (see chapter 5). Specifications of both whether and which interrupt event (C1, C2, S1..S8, E1..E4, L1..L4) is to be switched to the interrupt line of the L or C bus (default with 0 no interrupt). T0 The basic sampling time of the processor module is specified here. Additional specifications with regard to the processor module synchronization can be made (see chapter 5). I1...I5 (8) T1...T5 TY SSM ISE CCT, CCR COP X01...X0n CIP SIG TCR ICR EMA TCT/TCR Five (P16) or eight (P32) interrupt events (possibly with alternative sampling times) can be specified here. Any non--utilized interrupt task must be preset with 0 (default value). Five sampling times can be specified in rising sequence (multiples of the basic sampling time T0). Only steps of the power of two are permitted as factors (up to a maximum of 2**15 = 32768). The FP connections must also be specified. An non--utilized sampling time must be set with 0. This specifies in which sampling time the system FP is processed (T1..T5). The length of the SAVE area can be configured here. The value specified here is added to the 2 k byte that always exists (only for P16 processors!! -- P32 always possesses a 64 k byte SAVE area). This specifies whether the failure message (RDYINT) is to be ignored (Y) or not (N). A maximum of 64 transmit or receive communication names can be configured with sampling time specifications (only for P16 processors, review the configuring manual Communication P16 ). A maximum of 64 communication names for dialog blocks with sampling time references can be specified in this line (only for P16 processors, review configuring manual Communication P16 ). Names can be inserted in these lines (serial interfaces), they have no significance and are only to be viewed as comments. The specification at the connector of a coupling memory module (MM11, MM21, MM3, MM4), defines whether the data interface for communication is to be created (Y) or not (N) on this coupling memory (CIP3, see configuring manual Communication P16 or P32 ) The signal type to receive the time of day (0 = DCF--77,1 = IRIG--B) is specified here for the MM3. The configuring here specifies, for the CS21, whether the basic sampling time is to be received (Y) or not (N) from the CS11. This specifies, for the CS21, whether the interrupt from the C bus is to be switched through (Y) or not (N) by the CS11. Defines for CS12/13/14/22 whether the board is to be allocated the (N) or (Y) bit address space. When the 32 bit address space is allocated, then only P32 processors may access (checked by the compiler). The configuring here, for the CS3, defines whether the basic sampling time is either to be transmitted to the MMC / received from the MMC (Y) or not (N). Siemens AG Release

8 TSH/TSL The telegram specification for the plug connector X5 -- X8 is configured here for the CS41 (DL = long telegram, DS = short telegram for the DUST6 and ET for ET--100U operation). ND5 --ND8 The number of devices (DUST6) or ET100, connected to the plug connectors X5 -- X8, is configured here for the CS Input / Output Connectors Symbolic designations can be specified here, for the input and output hardware addresses, that can be utilized in the function packets. When no specifications are made, then the hardware address in the function packet can only be accessed via the module name in connection with the sub--connector designation. The symbol designation permits a standardization of the function drawings. 2.4 Sampling Times / Interrupt Events 2.4.1Basic Sampling Time The basic sampling time must be set--up according to the technological requirements. It causes the operating system to be cyclically activated and to check whether a sampling time is to be started. When no sampling time is to be started, then this signifies that processing power is discarded. Therefore the basic sampling time must be selected to be the same as the smallest sampling time (i.e. set T1 = 1 in the processor module screen). The basic clock T0 is to be set equal to the lowest desired processing time. If a smaller basic sampling time is required, due to the desired nesting of sampling times, then it should be noted that processing time is lost due to the frequent activation of the operating system. Therefore the larger the sampling time selected, the more processing is possible within this sampling cycle. Select the sampling time to satisfy the technological requirements. If a Torque Shell is to be calculated on a processor module, then thebasic sampling time should not be equal to or be a whole number multiple of the average cycle time of the torque shell (1 / linefrequency * pulse number). The average cycle time of the torque shell is 3.3 ms for a 6 pulse power converter and a line frequency of 50 Hz. Therefore a basic sampling time of 4 ms is desirable Sampling Times A total of 5 different cyclic sampling times can be configured. If a sampling time Tn is not used in any of the function packets of a processor, then it can be disabled by configuring Tn = 0 in the board screen. This sampling time is then not started by the operating system, thereby saving processing time. An unutilized sampling time Tn should be configured with Tn = 0 in the master program Sampling Time of the System Function (P16) (P32) The sampling time, in which the system tobe processed, should beset toapproximately 128 ms in the processor module screen with TY. The system FP is supplied as a previously compiled FP and is linked into each processor module, when not configured to the contrary in the master program. The FP was compiled such that the block, that controls the flashing frequency of the seven segment display, is processed with 128 ms Release Siemens AG

9 2.4.3Interrupt Events The configuring of interrupt processing has been changed in the version V4.2. The interrupt events are now configured the same as sampling times in the master program and are no longer defined in the interrupt controlled function packet. This has been necessary, since version V4.2 on P32 processors permit up to 16 interrupt controlled function packets and up to 8 interrupt tasks to be configured. No changes have been made for P16 processors, that previously permitted one function packet and 5 interrupt tasks. An unutilized interrupt task In should be configured with In = 0 in the master program (default value). New interrupt sources have been additionally added for P32 processors. The following shows an overview of all interrupt events that can be defined in version V4.2: C1...2 Processor Counter E1...4 External signal via interrupt generating binary interrupts (for P16 only E1..2) S1...8 Software interrupt I1...5 = IL,...IC Interrupt from L or C bus L1...4 Interrupt via LE bus (only P32) X Group interrupt via LE bus (only P32, i.e. for PM4 together with the power converter module ISL) Differences to Version V3.x Configuring of transport and message systems no longer occurs in the master program (no communication initialization blocks, i.e. DUST1, MSQ). Version V4.0 requires central blocks to be configured in the communication function packets instead. Two different modes of operation exist starting from version V 4.0, due to the introduction of the P32 processors: --- Mixed mode (P16 and / or P32 processors and no MM4), --- Pure P32 mode (only P32 processors with MM4). An additional type for FP connections (floating point format) was required for the specifications in the master program, (configure: G$NAME --- only for P32 processors). Increase in the number of cyclic function packets for the P32 processors from 8 to 64. Increase in the configurable number of FP connections for P32 processors (review chapter 4, Limit Values for FP Connections ). Siemens AG Release

10 Differences to Version V4.0 Configure the interrupt task in the master program (new connectors I1...I5 or I8 in the processor screen). Increase in the number of interrupt controlled function packets for P32 processors from 1 to 16 and an increase of the number of interrupt tasks from 5 to 8 for P32. New interrupt sources X01...X32 for group interrupts via LE bus Release Siemens AG