Introduction. PURPOSE: - List and explain the 15 i.mx1 modules that are also used on the i.mx21 device.

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1 Introduction PURPOSE: - List and explain the 15 i.mx1 modules that are also used on the device. OBJECTIVES: - Identify the similarities and differences between the two devices. - Describe the enhancements made in the. - Identify which modules are derived from the i.mx1. CONTENT: - 23 pages - 4 questions LEARNING TIME: - 45 minutes This module summarizes 15 modules on the that are re-used from the i.mx1, with special attention being paid to the enhancements and differences between the two devices.

2 Registers and GPIO Mux $ADDR0 $ADDR1 $ADDR2 $ADDR3 $ADDR4 $ADDR5 i.mx1 REGISTER A REGISTER B REGISTER C REGISTER D REGISTER C REGISTER B REGISTER D REGISTER A REGISTERS OF CARRIED-OVER MODULES Registers on modules carried over from the i.mx1 to the typically do not have the same address on both devices. The GPIO multiplexing scheme is different on the 2 devices. Similar dedicated functions existing internally on both devices may be routed out to different package connections. These address and GPIO multiplexing differences are not covered in this training, but are detailed in the Reference Manual.

3 (diagram for text_2 event on preceding page) i.mx1 FUNCTION A GPIO FUNCTION C GPIO FUNCTION B MUX OUT 1 FUNCTION B MUX OUT 1 FUNCTION C GPIO FUNCTION A GPIO FUNCTION D MUX OUT 2 FUNCTION D MUX OUT 2 GPIO MUXING SCHEME

4 Serial Peripheral Interface Attribute Chip Selects per module FIFOs Bits per Xfer SPI-2 i.mx1 1 8 x 16 bits 1 to 16 Master Mode only 3 8 x 32 bits 1 to 32 Master or Slave Mode The serial peripheral interface or SPI is enhanced on the. While each device has 2 distinct SPI circuit blocks, the number of chip selects per block has been increased to 3 on the. Both transmit and receive FIFOs are increased to 8 by 32. As determined by the FIFOs, the maximum transfer packet is increased to 32 bits. SPI-2 is more flexible - it can be configured in either master or slave mode.

5 Synchronous Serial Interface Attribute Routed by Word Length i.mx1 Function Mux Control Reg 8, 10, 12, 16 Bits Digital Audio Mux Adds 18, 20, 22, 24 bits The synchronous serial interface or SSI is modified on the. While each device has 2 SSIs, routing is now accomplished via the Digital Audio Multiplexor. This is detailed in the Reference Manual. Programmable word length has been expanded to include up to 24 bits.

6 Inter-IC (I 2 C) and PWM Both devices are the same design. There is no difference in the I 2 C blocks or the PWM blocks of the i.mx1 and.

7 UART Roll your mouse pointer the rows marked with an asterisk for a summary. Attribute i.mx1 Number of UARTs 3 4 * Number UARTs with full 8-wire interface 2 0 Max Baud Rate 1.0 Mbit/s Mbit/s Automatic Baud Rate Detection Not reliable over 57.6 kbit/s Improved up to kbit/s Special Auto-Baud Mode Present Removed Automatic Power Saving No Yes * Works with any reference clock frequency No Yes The universal asynchronous receiver/transmitter or UART has been modified and enhanced on the. A 4th UART has been added. All UARTs now work in 4-wire mode and no longer in 8-wire mode like the i.mx1. The 4-wire mode is comprised of 4 signals: TXD (transmit data), RXD (receive data), CTS (clear to send) and RTS (request to send). The 8-wire mode adds the following signals: DSR (data signal ready), DTR (data terminal ready), RI (ring indicator) and DCD (data carrier detect). For the, DSR, DTR, RI, and DCD are handled through General-Purpose Input Outputs (GPIOs). The maximum baud rate has been increased to megabits per second. The automatic baud rate detection has been improved. It is now reliable up to kilobits per second. The unused Special Auto-baud mode has been removed. The has added capability to automatically switch-off UART internal clocks when some parts of the module aren t used. The i.mx1 reference clock is restricted when the UART is working in Escape sequence determination or in Infrared mode. However, there is no restriction for the due to the new One-Millisecond register or ONEMS. The user writes the reference clock frequency into ONEMS, and the UART automatically adapts the counters for Escape detection and Infrared mode. Roll your mouse pointer over the two rows marked with an asterisk for more information.

8 (callouts for preceding page) 4-wire mode is comprised of 4 signals: TXD (transmit data) RXD (receive data) CTS (clear to send) RTS (request to send) The 8-wire mode adds the following signals: DSR (data signal ready) DTR (data terminal ready) RI (ring indicator) DCD (data carrier detect) For the, DSR, DTR, RI, and DCD are handled through General-Purpose Input Outputs (GPIOs). The i.mx1 reference clock is restricted when the UART is working in Escape sequence determination or in Infrared mode. There is no restriction for the due to the new One- Millisecond register or ONEMS. The user writes the reference clock frequency into ONEMS, and the UART automatically adapts counters for Escape detection and Infrared mode.

9 MMC/SDHC Attribute SDIO Support Max Data Rate i.mx1 SPI Mode only 100 Mbps All Modes 96 Mbps Clock Control Register (soft rst & enable sequence) Endian Prescaler bits Clk Divider bits $8 $D $5 8 times Big & Little 3 3 $8 $9 $1 8 times Little 12 4 The multimedia card and secure digital host controller or MMC/SDHC is slightly different on the. The is fully compatible with SDIO specification 1.0 using 1 or 4 channels. The has a maximum data rate of 96 megabits per second. To achieve a soft reset and enable, the clock control register must be programed with a special sequence: hexadecimal 8, followed by hexadecimal 9, followed by programming 1 eight times. The MMC/SDHC only supports little endian. The Prescaler control is expanded to 12 bits. Clock divider control is expanded to 4 bits.

10 SDRAMC imx1 A[15:11] A[20:16] MA11 MA10 imx1 A[19:16] A[24:21] A[10:1] DQM[3:0] CS2/CSD0 CS3/CSD1 RAS CAS SDWE SDCKE0 SDCKE1 SDCLK D[31:0] Here is the block diagram of the Synchronous Dynamic RAM Controller or SDRAMC along with external connections multiplexed with the SDRAM controller signals. Those signal names marked in red illustrate the only difference in signal multiplexing between the i.mx1 and the. In summary, only the upper address signal multiplexing has changed while the other signal multiplexing remains the same.

11 SDRAMC Another mode added: Manual Self Refresh Command Bit name changed to reflect what is found in industry standard SDRAM data sheets Here is the control register of the SDRAM controller with the two differences between the i.mx1 and indicated in red. First, a new mode has been added to the Controller Operating Mode bit settings, called manual selfrefresh mode. This allows the user to place the SDRAM memory into a self-refresh condition manually as opposed to having to place the processor in a low-power mode which automatically places the SDRAM in self refresh. The second change is the nomenclature for bits 13 and 12 which represent a power-saving feature employed by industry-standard SDRAM chips. For the i.mx1, this power saving feature is called Clock Suspend Timeout. However, for the, these bit names were changed changed to Power-Down Timeout to more accurately reflect what is commonly found in SDRAM data sheets. Note that the operation remains the same in that, depending on these bit settings, the controller will stop the clock to the SDRAM whenever the memory banks are inactive, or when 64 or 128 clocks have passed since the completion of the last access.

12 External Interface Module (EIM) The modules are essentially identical except for: supports synchronous style Cellular RAM (aka PSRAM) Updates to Chip Select Control Registers for Cellular RAM EW bit added to support WAIT feature PSR bit added to enable Cellular RAM mode CRE bit added to support writes to Cellular RAM control registers Other enhancements WRAP bit added to support wrap and non-wrap burst memories RWA/RWN bits added to adjust timing of RW signal CSA/CSN bits added to adjust timing of CS signal The External Interface Modules or EIMs are identical except as shown. First, the has been enhanced to support synchronous-style cellular RAM, also known as Pseudo SRAM. Thus, several bits are added to the EIM chip-select control register, such as the EW bit which is used to enable the wait feature of cellular RAM. The PSR bit is added to enable the EIM to operate in either Cellular RAM or Pseudo SRAM mode. Finally, the CRE bit enables the EIM to program the Cellular RAM s control register. Further enhancements include addition of the wrap bit which allows the EIM to operate in either wrap mode or non-wrap mode when communicating to burst-style memories that either support or don t support wrap around burst access. The read-write assert and read-write negate bits have been added to allow the user to adjust the assertion and de-assertion timing of the read-write signal. Also, the chip-select assert and negate bits allow the user to adjust the timing of the chip-select signal.

13 Watchdog Timer Module (WDOG) Attribute Condition for WDOG module to generate system reset Time-out period Time-out result Status Register Control Register i.mx1 WDOG Time-out 0.5 to 64 sec Set TOUT bit Assert Sys Reset or Generate Int Req 2 bits 7 bits Time out 6 bits Other WDOG Time-out Setting SRS bit Power-on Reset External Reset 0.5 to 128 sec Set TOUT bit Assert Sys Rst or Assert WDOG 5 bits 8 bits Time out 6 bits Other The Watchdog (WDOG) module has several modifications compared to the i.mx1. The module s system reset is triggered by any of 4 conditions: watchdog time-out, software setting of the SRS bit in the Control Register, power-on reset, or external reset. The maximum time-out period has increased to 128 seconds. The i.mx1 generates an interrupt upon time-out. The does not, but asserts its WDOG bar signal. The Status Register has 3 additional bits as detailed in the Reference Manual. The Control Register has an added bit for time out value. The 6 other bits have new functions as detailed in the Reference Manual.

14 Real-Time Clock (RTC) Attribute Time-of-day (TOD) clock counter i.mx1 512 days (9 bits) 65,536 days (16 bits) Clock counter has been increased to 179 years! The Real-Time Clock has one modification compared to the i.mx1. The Time-Of-Day clock counter, increased to 16 bits, keeps tabs on more than 65 thousand days or 179 years!

15 General-Purpose Input/Output GPIO is essentially identical to i.mx1 Both operate and are programmed the same way adds 2 GPIO ports i.mx1 consists of Ports A, B, C, and D adds Ports E and F GPIO Memory Map Base Addresses Port A: 0x Port B: 0x Port C: 0x Port D: 0x Port E: 0x Port F: 0x The i.mx1 and General-Purpose Input Output or GPIO Modules are of similar designs. Both modules operate and are programmed similarly. However, the adds two GPIO ports to its design. The i.mx1 consists of Ports A, B, C, and D. The adds Ports E and F. The memory map of the GPIO base registers is shown to illustrate the 6 distinct ports available.

16 General-Purpose Timers (GPT) Attribute Number of timers Number of interrupt sources per timer Prescaler division value i.mx to to 2048 i.mx1: Timers able to generate interrupt only on Compare event (generated when timer reaches predetermined value stored in specific register). : Timers also able to generate interrupt on Capture event which is generated on detection of predetermined edge (rising, falling, or both) of TIN input. When this edge is detected, value of timer is captured into specific register and an interrupt can be generated. The general-purpose timers are enhanced on the. There are now 3 timers. For the i.mx1, each timer was able to generate an interrupt only on a Compare event. This event is generated when the timer reaches a predetermined value stored in a specific register. The timers can also generate an interrupt on a Capture event. This Capture event is generated on the detection of a predetermined edge (rising, falling, or both) of the TIN input pin. When this edge is detected, the value of the timer is captured into a specific register and an interrupt can be generated. The prescaler divides the input clock frequency by a programmable value. For the, the division factor maximum is increased to 2,048.

17 CMOS Sensor Interface (CSI) The has more features than the i.mx1: CCIR656 (BT.656) support for the video interface and smart CMOS sensors Direct interface to emma pre-processing block Via dedicated bus faster data transfer Added: Control Register 3 (new features) RGB565 support for LCD direct-image display RGB888 support for further image processing Opportunity to use a Smart CMOS Sensor The CMOS Sensor Interface or CSI of the has more features than the i.mx1. The newer device supports the CCIR656 (BT.656) standard video interface as well as Smart CMOS sensors defined by the standard. Direct interface to the enhanced multi-media accelerator or EMMA pre-processing block via a dedicated bus allows faster data transfer. The new Control Register 3 incorporates bits that control new features of the CSI. There is RGB565 support for LCD panel direct image display. In addition, RGB888 data is supported for further image processing. Reiterating, the supports CCIR656 video and traditional sensor interfaces. The opportunity of using a Smart CMOS Sensor is also facilitated. Smart CMOS sensors that come with on-chip imaging processing usually support video mode transfers. They use an embedded timing code to replace the SOF and Blank signals. The timing codec is defined by the CCIR656 standard.

18 LCD Controller (LCDC) Feature i.mx1 Screen Size Monochrome / CSTN Support TFT Panel Support Max # Colors Hardware Cursor Hardware Panning Sharp 320x240 TFT Graphic Window # Alpha Blend Transparency Levels 640 x 512 Same 4-bit, 8-bit, 12-bit (mapped) 16-bit (true) 64,000 Yes Yes Supported Not Supported Not Supported 800 x 600 Same 4-bit, 8-bit, 12-bit, 16-bit (mapped) 18-bit (true) 256,000 Yes Yes Supported Supported 256 The differences between the i.mx1 and LCDC, are highlighted on this table. The supports larger screen resolution of eight hundred by six hundred pixels. An 18-bit data interface for TFT panels has been added, meaning that the number of achievable colors has increased to 256 thousand. A new feature for the is a graphics overlay function that allows blending a foreground image with a background image. Two hundred and fifty-six levels of blending are supported.

19 LCD Graphics Window Support For Camera Viewfinder or Graphical Hardware Cursor Software Programmable size and memory location 256 levels of alpha blending Graphics window and background image must have same BPP! Graphics Window Virtual Page Width Window Width Window Height Screen Graphics Window Position Background Image Graphics Window Graphics Window Start Address 16 bits per per pixel pixel The new graphics window feature can be used for a viewfinder or graphical hardware cursor, effectively giving a picture-in-picture effect on the display. The graphics window is software programmed similar to the screen you need to specify the virtual page width of the graphics window, the graphics window start address in memory, and the graphics window width and height. The figure shown above depicts how the graphics window is configured and how it is placed on the screen. The graphics window image and the background image can be alpha blended. What this means is that the graphics window can range from completely obscuring the background image, having the background image partially showing through, or not having the graphics window show through at all. There are 256 levels of alpha blending that can be achieved - this is software programmable. Alternatively, a certain color can be used as a color key ; this means that pixels matching this color in the graphics window are made transparent and the pixel in the background image shows through. When using the graphics window feature, the graphics window and the background image MUST have the same number of bits per pixel. For example, if the background image is set to 16-bits per pixel, the graphics window must also be set to 16-bits per pixel.

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21 BGA Package Attribute Ball Count Pitch i.mx mm mm Printed circuit board area is the same: 14 x 14 mm There are 2 differences in the package utilized for the. The number of connections is increased to 289. And the ball pitch is reduced to 0.65 millimeter. Note that the physical size of the i.mx1 and packages is the same: 14 by 14 millimeters. This is due to the ball count increase being offset by a tighter pitch.

22 Question Which of modules are identical on the i.mx1 and? Select all that apply and then click Done. a. I 2 C* b. SPI c. UART d. PWM* Done Here is the first of four questions to test your understanding of the material presented in this module. Correct. Items A and D are identical on the i.mx1 and. Items B and C are different on the when compared with the i.mx1. Click the forward arrow to continue on to the next page.]

23 Question Which of the following statements about the are true? Select all that apply and then click Done. a. All UARTs now work in 8-wire mode. b. The maximum Watchdog time-out period is 128 seconds.* c. The Liquid Crystal Display Controller supports a screen resolution of 800 x 600 pixels. * d. The Time-Of-Day clock counter is 9 bits. Done Here is a another question to test your understanding of the material. Correct. Items B and C are true. Item A is not true - all UARTs on the now work in 4-wire mode, versus 8-wire mode on the i.mx1; item D is not true - the Time-Of-Day clock counter on the is increased to 16 bits, versus 9 on the i.mx1.

24 Question Which of following statements about the i.mx1 and the are true? Select all that apply and then click Done. a. Registers on modules carried over from the i.mx1 to the typically do not have the same address on both devices. * b. The Synchronous Serial Interface (SSI) is identical on the i.mx1 and the. c. The GPIO multiplexing scheme is different on the i.mx1 and the.* d. The has more CSI features than the i.mx1.* Done Here is the third question about the material. Correct. Statements A, C, and D are true. Statement B is not true - the SSI on the is a modified version of that found on the i.mx1.

25 Question True or false? The complete list of i.mx1 modules that are re-used on the are: SPI, I2C, UART, SDRAMC, EMI, PWM, WDOG, RTC, CSI, and LCDC. Select your answer and then click Done. a. True b. False* Done This is the fourth and last question about this module. Correct. This statement is false 15 modules from the i.mx1 are re-used on the. They are: SPI, SSI, I 2 C, UART, MMC/SDHC, SDRAMC, EMI, PWM, WDOG, RTC, GPIO, GPT, CSI, LCDC, and BGA package.

26 Summary - The 15 i.mx1 modules re-used on the are: - SPI, SSI, I 2 C, UART, MMC/SDHC, SDRAMC, EMI, PWM, WDOG, RTC, GPIO, GPT, CSI, LCDC, and BGA package. - Almost all of these modules have been improved upon in the, except the I 2 C and PWM modules, which are identical between the two devices. Freescale TM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc This module summarized the 15 i.mx1 modules that are re-used on the, 13 of which have been improved upon in the device.