Introduction. PURPOSE: This course explains several important features of the i.mx21 microprocessor.

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1 Introduction PURPOSE: This course explains several important features of the i.mx21 microprocessor. OBJECTIVES: - Describe the features and functions of the ARM926EJ-S TM Core - Explain three processor modes for power control - Explain features of the Interrupt Controller - Highlight the Crossbar Switch - Describe the Phase-Locked Loop, Clock, and Reset Controller CONTENT: - 24 pages - 3 questions LEARNING TIME: - 36 minutes This course explains several important features of the i.mx21 microprocessor. Once you have finished this course, you will be better prepared to describe the features and functions of the ARM9 TM core, 3 modes for power consumption control, interrupt controller, crossbar switch, and PLL.

2 ARM Core Overview Multi-tasking JTAG 32-bit RISC I Cache 16 kb D Cache 16 kb VMMU 32-bit ARM instruction set 16-bit thumb instruction set Efficient execution of Java byte codes Symbian OS TM Microsoft Windows CE Linux The i.mx21 uses the ARM926EJ-S TM Core which is targeted for multi-tasking applications. It is a 32- bit RISC architecture with I cache and D cache of 16 kilobytes each, a virtual memory management unit or VMMU, and embedded ICE TM J-tag software debug. The ARM9 TM supports the 32-bit ARM and 16-bit thumb instructions sets and includes features for efficient execution of Java byte codes. The VMMU facilitates support of various platform operating systems such as Symbian OS TM, Microsoft Windows CE, and Linux. Remember, when used in relation to the ARM architecture, byte means 8 bits, half word means 16 bits or two bytes, and word means 32 bits or four bytes.

3 Processor Modes Roll your mouse pointer over the How To links to learn more. How to Enter Doze Mode: 1. Configure SDRAM for self refresh 2. Enable desired interrupts for wake-up 3. Disable watchdog timer interrupt 4. Execute Wait-for-Interrupt instruction ARM9 TM core has three modes for power management: Run Doze (How to Enter Doze Mode) Sleep (How to Enter Sleep Mode) How to Enter Sleep Mode: 1. Configure SDRAM for self-refresh 2. Disable ARM AHB (advanced high-performance bus) peripherals from bus accesses 2. Enable desired interrupts for wake-up 3. Disable watchdog timer interrupt 4. Program the SD_CNT bit in the CSCR register for shutdown countdown 5. Disable the MPLL by clearing the MPEN bit in the CSCR register 6. Execute wait-for-interrupt instruction The ARM9 TM has three modes for tailoring power consumption: run, doze, and sleep. In run mode all functions of the chip are available. This is the highest power mode. In doze mode, the ARM9 TM executes a wait-for-interrupt or WFI instruction. Roll your mouse pointer over How to Enter the Doze Mode for more information. In Sleep mode, the ARM9 TM also executes a WFI instruction. The outputs of the on-chip PLL are shut down and only the 32 kilohertz clock is running. Clocks are not available to external peripherals. This is the lowest power mode. Roll your mouse pointer over How to Enter the Sleep Mode for more information.

4 Interrupt Vectoring Vector Table Located in High Memory This diagram shows the vector table located in high memory. Two vector table modes are supported: one is high memory and one is low memory. If the ARM interrupt controller or AITC is in high-memory vector table mode, the ARM processor loads the Program Counter or PC with a vector from a table of 64 vectors located at Hex FFFF FF00 to hex FFFF FFFF. More specifically, the PC is loaded with the vector located at hex FFFF FF00 plus 4 times the vector index. If the AITC is in low-memory vector table mode, the ARM loads the PC with a vector from a table of 64 vectors beginning at table pointer and ending at table pointer plus hex FF. More specifically, the PC is loaded with the vector located at the table pointer plus 4 times the vector index. This hardware mechanism alleviates the need for software to determine which interrupt source caused the interrupt to be asserted.

5 ARM Interrupt Controller (AITC) Interrupt Controller up to 64 sources Select Normal (IRQ) or Fast Interrupt (FIQ) request for any interrupt source Register indicates pending sources Register indicates highest priority number Independently enable or disable any source Facilitates software scheduling an interrupt Up to 16 priority levels for normal interrupts and priority masking Single-bit disabling of any interrupt, used in enabling secure operations The Interrupt Controller supports up to 64 interrupt sources. Selects normal IRQ or fast interrupt FIQ request for any interrupt source. Register indicates pending interrupt sources for normal and fast interrupts. Register indicates highest priority interrupt number, which can be used as table index. Independently enable or disable any interrupt source. Facilitates software scheduling an interrupt. Supports up to 16 software controlled priority levels for normal interrupts and priority masking. Single-bit disabling of any interrupt, which is used in enabling secure operations.

6 Interrupt Sources FINT IN0 IN1 IN2 IN61 IN62 IN63 ARM INT This diagram illustrates the logical structure of the interrupt controller. It shows that all 64 interrupt input sources are OR d together to form either a normal interrupt request or fast interrupt request to the arm core. The interrupt sources can be chosen to be a fast or normal interrupt source, depending on the settings made in the interrupt controller. You will learn more on the following pages.

7 Interrupt Control Register INTCNTL Read/Write NIAD FIAD NIAD FIAD Disable Disable Enable Enable Alternate Master Interrupt Flag Bus Alternate Master Interrupt Flag Bus This diagram illustrates the interrupt control register and its corresponding bit settings. When the normal interrupt arbiter disable, or NIAD, bit is set, a normal interrupt flag prevents alternate master from accessing the bus. When the fast interrupt arbiter disable or FIAD bit is set, a fast interrupt flag prevents alternate master from accessing the bus.

8 Normal Interrupt Masking NIMASK NIMASK Normal Interrupt Mask Register Read/write RST: RST: Default on Reset enables all Normal Interrupts Normal Interrupt Mask[4:0] - Controls normal interrupt mask level. All normal interrupts of priority level lower than or equal to the NIMASK will be disabled. -1 = Do not disable any normal interrupts 0 = Disable priority level 0 normal interrupts 1 = Disable priority level 1 and lower normal interrupts = Disable all normal interrupts 16+ = Do not disable any normal interrupts This diagram depicts the normal interrupt masking NIMASK register of the interrupt controller. The normal interrupt mask, bits 4 to 0, control the normal interrupt mask level. All normal interrupts of priority level lower than or equal to the NIMASK will be disabled. The default value for this register does not mask any interrupt source.

9 Interrupt Source ENNUM INTENNUM Interrupt Enable Number Register RST: RST: Self Clear 0 Interrupt Enable Number 0 = Enable interrupt source 0 1 = Enable interrupt source = Enable interrupt source 63 DISNUM INTDISNUM Interrupt Disable Number Register RST: RST: Self Clear 0 Interrupt Disable Number 0 = Disable interrupt source 0 1 = Disable interrupt source = Disable interrupt source 63 The interrupt enable number register allows the user to enable the interrupt source number programmed into this register The interrupt disable number register immediately disables the interrupt source number programmed into its register.

10 Interrupt Priority Assignment NIPRIORITY7 NIPRIORITY6 NIPRIORITY5 NIPRIORITY7 Normal Interrupt Priority Level Register NIPRIORITY4 NIPRIORITY3 NIPRIORITY2 Priority = 8 Priority = 8 NIPRx Normal Interrupt Priority x 0 = Lowest priority normal interrupt 0 1 = Priority 1 normal interrupt - - F = Highest priority normal interrupt NIPRIORITY1 NIPRIORITY0 Normal Interrupt Priority Level Register NIPRIORITY The interrupt controller allows the prioritization of all normal interrupts. There are eight normal priority registers, zero to seven, each controlling the priority level of particular interrupt source bits. The normal interrupt priority registers allow normal interrupts to be assigned a priority of 0, which is the lowest priority, to hex F, which is the highest priority. If two or more normal interrupt sources are assigned the same priority value, the higher interrupt source number has priority. For example, if interrupt source number 5 and interrupt source number 58 are assigned a priority of 8, and both occur at the same time, interrupt source number 58 takes precedence. However, if in this example interrupt source number 5 is given a higher priority, say 9, interrupt source number 5 takes precedence if both interrupts occur at the same time. Regardless, fast interrupts have the highest priority over any normal interrupt, no matter what priority is assigned to the normal interrupt.

11 Interrupt Vector/Status NIVECSR Normal Interrupt Vector and Status Register RST: RST: 1 1 FIVECSR Fast Interrupt Vector and Status Register RST: RST: 1 1 The normal interrupt vector and status register displays the highest priority pending normal interrupt source number as well as its corresponding priority value. Roll your mouse pointer over the top diagram for more information. The fast interrupt vector and status register displays the highest priority pending fast interrupt source number. These registers are useful for determining which interrupt source service routine to execute. Roll your mouse pointer over the bottom diagram for more information.

12 (callouts for preceding page) NIVECTOR Normal Interrupt Vector: $FFFF = No normal Interrupts Pending $0000 = Interrupt 0 is the highest pending priority $0001 = Interrupt 1 is the highest pending priority - $003F = Interrupt 63 is the highest pending priority NIPRILVL = Normal Interrupt Priority Level: $FFFF = No Interrupt request is pending $0000 = Highest Priority Interrupt is Level 0 $0001 = Highest Priority Interrupt is Level 1 - $000F = Highest Priority Interrupt is Level 15 FIVECTOR Fast Interrupt Vector: $FFFF = No Fast Interrupts Pending $0000 = Interrupt 0 is the highest pending priority $0001 = Interrupt 1 is the highest pending priority - $003F = Interrupt 63 is the highest pending priority

13 Interrupt Source Registers INTSRCH Interrupt Source Register High Read Only 15.0 INTSRCL Interrupt Source Register Low Read Only 15.0 IN[63:32] - Interrupt Source - Indicates the state of the corresponding hardware interrupt source. 0 = interrupt negated 1 = interrupt asserted IN[31:0] - Interrupt Source -Indicates the state of the corresponding hardware interrupt source. 0 = interrupt negated 1 = interrupt asserted The interrupt source register high and the interrupt source register low are each 32 bits. They reflect the status of all interrupt request inputs into the interrupt controller.

Multi-layer AHB Crossbar Switch ARM9 TM Platform I-AHB D-AHB ARM9 TM Core AHB-Lite Alternate Bus Master Ports Master Ports 0 1 2 3 4 5 MAX Slave Ports 0 1 2 3 Primary AHB AHB-Lite Secondary Slave

14 Multi-layer AHB Crossbar Switch ARM9 TM Platform I-AHB D-AHB ARM9 TM Core AHB-Lite Alternate Bus Master Ports Master Ports MAX Slave Ports Primary AHB AHB-Lite Secondary Slave Ports The Multi-layer AHB Crossbar Switch is also referred to as MAX. This 6 by 4 crossbar switch supports simultaneous connections between 6 master and 4 slave ports. Specifically, the MAX allows for concurrent transactions to occur from any master port to any slave port. The MAX routes bus transactions initiated on the master ports to appropriate slave ports. Note that no provision is made for routing transactions initiated on slave ports to other slave ports or to master ports. Four master and three slave ports are externally routed from the embedded ARM9 TM platform.

15 MAX Registers Roll your mouse pointer over each of the five italicized items for more information. One register resides in each master port Master General-Purpose Control Register Four registers reside in each slave port Master Priority Register Alternate Master Priority Register Slave General-Purpose Control Register Alternate Slave General-Purpose Control Register All registers are 32-bit access and IP bus compliant One register resides in each master port. This is the Master General-Purpose Control Register. Four registers reside in each slave port; namely, the Master Priority Register, the Alternate Master Priority Register, the Slave General-Purpose Control Register, and the Alternate Slave General-Purpose Control Register. All registers are 32-bit access and IP bus compliant. Roll your mouse pointer over each of the five italicized items for more information.

16 (callouts for preceding page) Controls whether or not arbitration occurs during a master s undefined-length burst access. Sets priority of each master port on a per slave port basis Resides in each slave port Same function as Master Priority Register Allows set up of alternate priorities for context switching Controls features of a slave port, such as read only mode, park control when no master is making a request, high-priority input control Same function as register above, except no Read Only bit Allows set up of alternate general control for context switching These are the callouts for the preceding page.

17 PLL Features The Phase-Locked Loop, Clock, and Reset Controller, or PLL, provides: Individual clock gating to each module Two PLLs SPLL: Supplies serial peripherals (USB, UARTs, SSI ) MPLL: Supplies ARM core and system bus; up to 266 MHz Power management: STOP and DOZE modes Frequency Premultiplier 32 khz and 26 MHz oscillators Active Well Bias to reduce standby current Wake Up guard to ensure battery was not removed The Phase-Locked Loop, Clock, and Reset Controller, or PLL, provides individual clock gating to each module for minimizing power consumption. There are 2 independent PLLs. SPLL supplies the serial peripherals, such as the USB, UARTs, SSI, etc. MPLL supplies the ARM core and system bus; it can operate up to 266 megahertz. Power management is accommodated by Stop and Doze modes. There is a Frequency Premultiplier that takes the 32 khz oscillator frequency up to the 16 MHz range, 32 kilohertz and 26 megahertz oscillators, Active Well Bias to reduce standby current consumption, and Wake Up guard to ensure the battery was not removed.

PLL Block Diagram D E A B F C There are 3 main sections to the PLL: clock generation, dividers, and gating. The clock generation section can use either the 32 kilohertz or 26 megahertz oscillator.

18 PLL Block Diagram D E A B F C There are 3 main sections to the PLL: clock generation, dividers, and gating. The clock generation section can use either the 32 kilohertz or 26 megahertz oscillator. The kilohertz oscillator is mandatory because it is applied to RTC module and it is the only clock running while in standby mode. The supported crystals are actually 32.0 or kilohertz. These frequencies, when used as a reference for the whole system, are multiplied by 512 in the FPM block. This results in a or megahertz clock input into the PLLs. If there are tight requirements on the system clock jitter, the 26 megahertz oscillator may be used, and the reference frequency to the PLLs is then 26 megahertz. For each PLL, either 16 or 26 megahertz can be selected as a clock source. The dividers are partitioned into the MPLL and SPLL sides. The MPLL side provides a clock to the ARM CPU, the internal bus, plus most of the IP modules. Right after the MPLL, a pre-scaler permits dividing the frequency to feed into the CPU core. The internal bus frequency is generated from this clock, divided by BCLKDIV. Then, the bus clock is divided by IPDIV to provide the clocks to the IP peripherals. The SPLL side is intended to provide a clock to the FIRI, USB, and SSI. It operates independently from the MPLL. The clock source for these modules can actually be selected to be either SPLL or MPLL. Clock gating facilitates minimizing power consumption. Most IP peripherals have bits to enable or disable clocks feeding them. This permits clock tree reduction to the minimum required by the application that is running. Some peripherals need 2 clocks, HCLK and module clock, for the module to operate normally. Several peripherals can be connected to peripheral clock dividers. These dividers can be gated off when all the modules that are after the divider in the clock tree are off.

19 PLL Connections to peripherals Clock Source SSI1CLK SSI2CLK FIRICLK NFCCLK PERCLK4 PERCLK3 PERCLK2 PERCLK1 CLK48M Others Peripheral SSI1 SSI2 FIRI NFC CSI LCDC SDHC CSPI UART GPT PWM USB HCLK / ipg_clk Each clock feeds one or more peripherals. Most peripherals also have internal dividers, so it is possible for a peripheral clock to be shared between several peripherals, as in the PERCLK1 case.

20 PLL Power Modes Modes Run CPU and utilized peripherals running, unused peripherals gated off Example: an application running Doze Clock to CPU gated off, bus clock running, unused peripherals gated off Example: DMA transfer, LCD refresh (do not require CPU) Interrupt causes return to Run mode Standby (sleep) All clocks of system are turned off (core + bus), PLLs are stopped No activity except Real-Time Clock Interrupt causes return to Run mode Scalable frequency The core and bus frequency can be adjusted according to the computing power that is required. There are 3 power modes. Run is used when the application requires the CPU and peripherals running. Unused peripherals are gated off to save power. An example is running an application. Doze is used when the CPU is not needed. The clock to the CPU is gated off, the bus clock is running, and unused peripherals are gated off. Examples are a DMA transfer or LCD refresh; these don t require the CPU. An interrupt causes a return to the Run mode. Standby forces all the clocks of the system to be turned off; that is, clocks feeding the core and bus. The PLLs are stopped and there is no activity except the real-time clock. An interrupt causes a return to the Run mode. With scalable frequency, the core and bus frequency can be adjusted according to the computing power that is required. This facilitates power management.

21 Question Which of the following statements about the ARM926EJ-S TM core are true? Select all that apply and then click Done. a. It supports the 16-bit ARM and 32-bit thumb instructions sets b. It has two modes for tailoring power consumption: run and doze. c. It has a virtual memory management unit. * d. The ARM926EJ-S Core is targeted for multi-tasking applications. * Done Here is a question to test your understanding of the material. Correct. Statements C and D are true. Statement A is not true the ARM926EJ-S TM supports the 32-bit ARM and 16-bit thumb instructions sets. Statement B is not true there are three modes for tailoring power (run, doze, and sleep).

22 Question Which of the following statements about the Interrupt Controller are true? Select all that apply and then click Done. a. When the NIAD bit is set, a fast interrupt flag prevents alternate master from accessing the bus. b. The interrupt source register high and the interrupt source register low are each 32 bits. * c. The Interrupt Controller supports up to 64 interrupt sources. * d. If two or more normal interrupt sources are assigned the same priority value, the lower interrupt source number has priority. Done Here is a question to test your understanding of the material. Correct. Statements B and C are true. Statement A is not true When the normal interrupt arbiter disable or NIAD bit is set, a normal interrupt flag prevents alternate master from accessing the bus. Statement D is not true - if two or more normal interrupt sources are assigned the same priority value, the higher interrupt source number has priority.

23 Question True or False? The Multi-layer AHB Crossbar Switch supports simultaneous connections between 6 master and 4 slave ports. Select your answer and then click Done. a. True b. False Done Take another moment to answer another question about the material. Correct. The Multi-layer AHB Crossbar Switch supports simultaneous connections between 6 master and 4 slave ports. Click the forward arrow to continue on to the next page.]

24 Question Which of the following are not features of the MPLL? Select all that apply and then click Done. a. Clock generation b. SPLL c. Dividers d. Gating Done Here is a question to test your understanding of the material. Correct. The SPLL is an independent PLL it supplies the serial peripherals. Click the forward arrow to continue on to the next page.]

25 Module Summary - Features and functions of the ARM926EJ-S TM Core - Three processor modes for power control - Features of the Interrupt Controller - Overview of the Crossbar Switch - Description of the Phase-Locked Loop, Clock, and Reset Controller Freescale TM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc In this course you learned the features and functions of the ARM9 TM core, three processor modes for power control, the interrupt controller, the crossbar switch, and the PLL.

Table 1 provides silicon errata information that relates to the masks 0M55B, 1M55B, and M55B of the MC9328MX21S (i.mx21s) applications processor.

Freescale Semiconductor Chip Errata Document : MC9328MX21SCE Rev. 4, 11/2012 MC9328MX21S Chip Errata for Masks:,, Table 1 provides silicon errata information that relates to the masks,, and of the MC9328MX21S