1 Megabit (128K x8) Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010

Transcription

1 Megabit (K x) Page-Mode EEPROM FEAURES: Single Voltage Read and Write Operations.0V-only for the SSEE00.0-.V for the SSLE00.-.V for the SSVE00 Superior Reliability Endurance: 00,000 Cycles (typical) Greater than 00 years Data Retention Low Power Consumption Active Current: 0 ma (typical) for V and 0 ma (typical) for.0/.v Standby Current: 0 µa (typical) Fast Page-Write Operation Bytes per Page, 0 Pages Page-Write Cycle: ms (typical) Complete Memory Rewrite: sec (typical) Effective Byte-Write Cycle ime: µs (typical) PRODUC DESCRIPION he SSEE00/LE00/VE00 are K x CMOS Page-Write EEPROMs manufactured with SS s proprietary, high performance CMOS SuperFlash technology. he split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. he SSEE00/LE00/VE00 write with a single power supply. Internal Erase/Program is transparent to the user. he SSEE00/LE00/VE00 conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance Page-Write, the SSEE00/LE00/VE00 provide a typical Byte- Write time of µsec. he entire memory, i.e., KBytes, can be written page-by-page in as little as seconds, when using interface features such as oggle Bit or Data# Polling to indicate the completion of a Write cycle. o protect against inadvertent write, the SSEE00/LE00/VE00 have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SSEE00/LE00/VE00 are offered with a guaranteed Page-Write endurance of 0 cycles. Data retention is rated at greater than 00 years. he SSEE00/LE00/VE00 are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all Data Sheet Fast Read Access ime.0v-only operation: 0 and 0 ns.0-.v operation: 0 and 00 ns.-.v operation: 00 and 0 ns Latched Address and Data Automatic Write iming Internal V PP Generation End of Write Detection oggle Bit Data# Polling Hardware and Software Data Protection L I/O Compatibility JEDEC Standard Flash EEPROM Pinouts and command sets Packages Available Pin PDIP -Pin PLCC -Pin SOP (mm x 0mm, mm x mm) system applications, the SSEE00/LE00/ VE00 significantly improve performance and reliability, while lowering power consumption. he SSEE00/LE00/VE00 improve flexibility while lowering the cost for program, data, and configuration storage applications. o meet high density, surface mount requirements, the SSEE00/LE00/VE00 are offered in -pin SOP (mm x 0mm and mm x mm) and -lead PLCC packages. A 00-mil, -pin PDIP package is also available. See Figures and for pinouts. Device Operation he SS Page-Mode EEPROM offers in-circuit electrical write capability. he SSEE00/LE00/VE00 does not require separate Erase and Program operations. he internally timed write cycle executes both erase and program transparently to the user. he SSEE00/LE00/VE00 have industry standard optional Software Data Protection, which SS recommends always to be enabled. he SSEE00/ LE00/VE00 are compatible with industry standard EEPROM pinouts and functionality. Read he Read operations of the SSEE00/LE00/ VE00 are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the Silicon Storage echnology, Inc. he SS logo and SuperFlash are registered trademarks of Silicon Storage echnology, Inc. SSF is a trademark of Silicon Storage echnology, Inc. 0- /00 hese specifications are subject to change without notice.

2 chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. he data bus is in high impedance state when either CE# or OE# is high. Refer to the read cycle timing diagram for further details (Figure ). Write he Page-Write to the SSEE00/LE00/VE00 should always use the JEDEC Standard Software Data Protection (SDP) three-byte command sequence. he SSEE00/LE00/VE00 contain the optional JEDEC approved Software Data Protection scheme. SS recommends that SDP always be enabled, thus, the description of the Write operations will be given using the SDP enabled format. he three-byte SDP Enable and SDP Write commands are identical; therefore, any time a SDP Write command is issued, Software Data Protection is automatically assured. he first time the three-byte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired Page-Write, the entire device remains protected. For additional descriptions, please see the application notes on he Proper Use of JEDEC Standard Software Data Protection and Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories in this data book. he Write operation consists of three steps. Step is the three-byte load sequence for Software Data Protection. Step is the byte-load cycle to a page buffer of the SSEE00/LE00/VE00. Steps and use the same timing for both operations. Step is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP three-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. he data is latched by the rising edge of either CE# or WE#, whichever occurs first. he internal write cycle is initiated by the BLCO timer after the rising edge of WE# or CE#, whichever occurs first. he Write cycle, once initiated, will continue to completion, typically within ms. See Figures and for WE# and CE# controlled Page- Write cycle timing diagrams and Figures and for flowcharts. he Write operation has three functional cycles: the Software Data Protection load sequence, the page load cycle, and the internal write cycle. he Software Data Protection consists of a specific three-byte load sequence that allows writing to the selected page and will leave the SSEE00/LE00/VE00 protected at the end of the Page-Write. he page load cycle consists of loading to bytes of data into the page buffer. he internal write cycle consists of the BLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and oggle Bit. he Page-Write operation allows the loading of up to bytes of data into the page buffer of the SSEE00/ LE00/VE00 before the initiation of the internal write cycle. During the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the Page-Write feature of SSEE00/ LE00/VE00 allow the entire memory to be written in as little as seconds. During the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page-Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A through A. Any byte not loaded with user data will be written to FF. See Figures and for the Page-Write cycle timing diagrams. If after the completion of the three-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byteload cycle time ( BLC ) of 00 µs, the SSEE00/ LE00/VE00 will stay in the page load cycle. Additional bytes are then loaded consecutively. he page load cycle will be terminated if no additional byte is loaded into the page buffer within 00 µs ( BLCO ) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. he page load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 00 µs. he page to be loaded is determined by the page address of the last byte loaded. Software Chip-Erase he SSEE00/LE00/VE00 provide a Chip- Erase operation, which allows the user to simultaneously clear the entire memory array to the state. his is useful when the entire device must be quickly erased. he Software Chip-Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle similar to the Write cycle. During the Erase operation, the only valid read is oggle Bit. See able for the load sequence, Figure for timing diagram, and Figure for the flowchart.

3 Write Operation Status Detection he SSEE00/LE00/VE00 provide two software means to detect the completion of a Write cycle, in order to optimize the system write cycle time. he software detection includes two status bits: Data# Polling (DQ ) and oggle Bit (DQ ). he end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal write cycle. he actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or oggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ or DQ. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two () times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ ) When the SSEE00/LE00/VE00 are in the internal write cycle, any attempt to read DQ of the last byte loaded during the byte-load cycle will receive the complement of the true data. Once the Write cycle is completed, DQ will show true data. he device is then ready for the next operation. See Figure for Data# Polling timing diagram and Figure for a flowchart. oggle Bit (DQ ) During the internal write cycle, any consecutive attempts to read DQ will produce alternating 0 s and s, i.e. toggling between 0 and. When the Write cycle is completed, the toggling will stop. he device is then ready for the next operation. See Figure for oggle Bit timing diagram and Figure for a flowchart. he initial read of the oggle Bit will typically be a. Data Protection he SSEE00/LE00/VE00 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than ns will not initiate a Write cycle. V CC Power Up/Down Detection: he Write operation is inhibited when V CC is less than.v. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. his prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) he SSEE00/LE00/VE00 provide the JEDEC approved optional Software Data Protection scheme for all data alteration operations, i.e., Write and Chip-Erase. With this scheme, any Write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. he three byte-load sequence is used to initiate the Write cycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. he SSEE00/LE00/VE00 are shipped with the Software Data Protection disabled. he software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (Figures and ). he device will then be automatically set into the data protect mode. Any subsequent Write operation will require the preceding three-byte sequence. See able for the specific software command codes and Figures and for the timing diagrams. o set the device into the unprotected mode, a six-byte sequence is required. See able for the specific codes and Figure for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~ 00 µs. SS recommends Software Data Protection always be enabled. See Figure for flowcharts. he SSEE00/LE00/VE00 Software Data Protection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). herefore using SDP for a single Page-Write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled or disabled. 0

4 Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SS strongly recommends that Software Data Protection (SDP) always be enabled. he SSEE00/LE00/VE00 should be programmed using the SDP command sequence. SS recommends the SDP Disable Command Sequence not be issued to the device prior to writing. Please refer to the following Application Notes located at the back of this databook for more information on using SDP: Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories he Proper Use of JEDEC Standard Software Data Protection Product Identification he product identification mode identifies the device as the SSEE00/LE00/VE00 and manufacturer as SS. his mode may be accessed by hardware or software operations. he hardware operation is typically used by a programmer to identify the correct algorithm for the SSEE00/LE00/VE00. Users may wish to use the software product identification operation to identify the part (i.e. using the device code) when using multiple manufacturers in the same socket. For details, see able for hardware operation or able for software operation, Figure 0 for the software ID entry and read timing diagram and Figure for the ID entry command sequence flowchart. he manufacturer and device codes are the same for both operations. Product Identification Mode Exit ABLE : PRODUC IDENIFICAION ABLE Byte Data Manufacturer s ID 0000 H BF H SSEE00 Device ID 000 H 0 H SSLE00 Device ID 000 H 0 H SSVE00 Device ID 000 H 0 H 0 PGM. In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the Read operation. he Reset operation may also be used to reset the device to the Read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See able for software command codes, Figure for timing waveform and Figure for a flowchart. FUNCIONAL BLOCK DIAGRAM OF SSEE00/LE00/VE00 X-Decoder,0, Bit EEPROM Cell Array A - A0 CE# OE# WE# Address Buffer & Latches Control Logic Y-Decoder and Page Latches I/O Buffers and Data Latches DQ - DQ0 0 ILL B.0

5 A A A A A NC WE# V CC NC A A A A A A A 0 Standard Pinout op View Die Up 0 0 OE# A0 CE# DQ DQ DQ DQ DQ V SS DQ DQ DQ0 A0 A A A 0 ILL F0. FIGURE : PIN ASSIGNMENS FOR -PIN SOP NC A A A A A A A A A A A0 DQ0 DQ DQ VSS 0 -Pin PDIP op View 0 0 VCC WE# NC A A A A A OE# A0 CE# DQ DQ DQ DQ DQ A A A A A A A A0 DQ0 A A A NC VCC WE# NC 0 -Lead PLCC op View 0 0 DQ DQ VSS DQ DQ DQ DQ A A A A A OE# A0 CE# DQ 0 ILL F0.0 0 FIGURE : PIN ASSIGNMENS FOR -PIN PLASIC DIPS AND -LEAD PLCCS ABLE : PIN DESCRIPION Symbol Pin Name Functions A -A Row Address Inputs o provide memory addresses. Row addresses define a page for a Write cycle. A -A 0 Column Address Column Addresses are toggled to load page data. Inputs DQ -DQ 0 Data Input/output o output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. he outputs are in tri-state when OE# or CE# is high. CE# Chip Enable o activate the device when CE# is low. OE# Output Enable o gate the data output buffers. WE# Write Enable o control the Write operations Vcc Power Supply o provide -volt supply (± 0%) for the SSEE00, -volt supply (.0-.V) for the SSLE00 and.-volt supply (.-.V) for the SSVE00 Vss Ground NC No Connection Unconnected pins. 0 PGM.0

6 ABLE : OPERAION MODES SELECION Mode CE# OE# WE# DQ Address Read V IL V IL V IH D OU A IN Page-Write V IL V IH V IL D IN A IN Standby V IH X X High Z X Write Inhibit X V IL X High Z/ D OU X Write Inhibit X X V IH High Z/ D OU X Software Chip-Erase V IL V IH V IL D IN A IN, See able Product Identification Hardware Mode V IL V IL V IH Manufacturer ID (BF) A - A = V IL, A = V H, A 0 = V IL Device ID (see notes) A - A = V IL, A = V H, A 0 = V IH Software Mode V IL V IH V IL See able SDP Enable Mode V IL V IH V IL See able SDP Disable Mode V IL V IH V IL See able 0 PGM.0 ABLE : SOFWARE COMMAND CODES Command st Bus nd Bus rd Bus th Bus th Bus th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Software Data H AAH AAAH H H A0H Addr () Data Protect Enable & Page-Write Software Data H AAH AAAH H H 0H H AAH AAAH H H 0H Protect Disable Software Chip- H AAH AAAH H H 0H H AAH AAAH H H 0H Erase Software ID Entry H AAH AAAH H H 0H Software ID Exit H AAH AAAH H H F0H Alternate Software H AAH AAAH H H 0H H AAH AAAH H H 0H ID Entry () 0 PGM. Notes: () Address format A -A 0 (Hex), Addresses A and A are a Don t Care. () Page-Write consists of loading up to Bytes (A - A 0). () Alternate six-byte software Product-ID Command Code () he software Chip-Erase function is not supported by the industrial temperature part. Please contact SS, if you require this function for an industrial temperature part. Notes for Software Product ID Command Code:. With A -A =0; SS Manufacturer ID = BFH, is read with A 0 = 0, SSEE00 Device ID = 0H, is read with A 0 =. SSLE00/VE00 Device ID = 0H, is read with A 0 =.. he device does not remain in Software Product ID Mode if powered down.. his device supports both the JEDEC standard three-byte command code sequence and SS s original six-byte command code sequence. For new designs, SS recommends the three-byte command code sequence be used.

7 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. his is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) emperature Under Bias... - C to + C Storage emperature... - C to +0 C D. C. Voltage on Any Pin to Ground Potential V to V CC+ 0.V ransient Voltage (<0 ns) on Any Pin to Ground Potential V to V CC +.0V Voltage on A Pin to Ground Potential V to.0v Package Power Dissipation Capability (a = C)....0W hrough Hole Lead Soldering emperature (0 Seconds) C Surface Mount Lead Soldering emperature ( Seconds)... 0 C Output Short Circuit Current () ma Note: () Outputs shorted for no more than one second. No more than one output shorted at a time. SSEE00 OPERAING RANGE Range Ambient emp V CC Commercial 0 C to +0 C V±0% Industrial -0 C to + C V±0% SSLE00 OPERAING RANGE Range Ambient emp V CC Commercial 0 C to +0 C.0V to.v Industrial -0 C to + C.0V to.v SSVE00 OPERAING RANGE Range Ambient emp V CC Commercial 0 C to +0 C.V to.v Industrial -0 C to + C.V to.v AC CONDIIONS OF ES Input Rise/Fall ime... 0 ns Output Load... L Gate and C L = 00 pf See Figures and 0

8 ABLE : SSEE00 DC OPERAING CHARACERISICS V CC = V±0% Limits Symbol Parameter Min Max Units est Conditions I CC Power Supply Current CE#=OE#=V IL, WE#=V IH, all I/Os open, Read 0 ma Address input = V IL /V IH, at f=/ RC Min., V CC=V CC Max Write 0 ma CE#=WE#=V IL, OE#=V IH, V CC =V CC Max. I SB Standby V CC Current ma CE#=OE#=WE#=V IH, V CC =V CC Max. (L input) I SB Standby V CC Current 0 µa CE#=OE#=WE#=V CC -0.V. (CMOS input) V CC = V CC Max. I LI Input Leakage Current µa V IN =GND to V CC, V CC = V CC Max. I LO Output Leakage Current 0 µa V OU =GND to V CC, V CC = V CC Max. V IL Input Low Voltage 0. V V CC = V CC Min. V IH Input High Voltage.0 V V CC = V CC Max. V OL Output Low Voltage 0. V I OL =. ma, V CC = V CC Min. V OH Output High Voltage. V I OH = -00µA, V CC = V CC Min. V H Supervoltage for A.. V CE# = OE# =V IL, WE# = V IH I H Supervoltage Current 00 µa CE# = OE# = V IL, WE# = V IH, for A A = V H Max. 0 PGM. ABLE : SSLE00/VE00 DC OPERAING CHARACERISICS V CC =.0-. FOR SSLE00, V CC =.-. FOR SSVE00 Limits Symbol Parameter Min Max Units est Conditions I CC Power Supply Current CE#=OE#=V IL,WE#=V IH, all I/Os open, Read ma Address input = V IL /V IH, at f=/ RC Min., V CC=V CC Max Write ma CE#=WE#=V IL, OE#=V IH, V CC =V CC Max. I SB Standby V CC Current ma CE#=OE#=WE#=V IH, V CC =V CC Max. (L input) I SB Standby V CC Current µa CE#=OE#=WE#=V CC -0.V. (CMOS input) V CC = V CC Max. I LI Input Leakage Current µa V IN =GND to V CC, V CC = V CC Max. I LO Output Leakage Current 0 µa V OU =GND to V CC, V CC = V CC Max. V IL Input Low Voltage 0. V V CC = V CC Min. V IH Input High Voltage.0 V V CC = V CC Max. V OL Output Low Voltage 0. V I OL = 00 µa, V CC = V CC Min. V OH Output High Voltage. V I OH = -00 µa, V CC = V CC Min. V H Supervoltage for A.. V CE# = OE# =V IL, WE# = V IH I H Supervoltage Current 00 µa CE# = OE# = V IL, WE# = V IH, for A A = V H Max. 0 PGM.

9 ABLE : POWER-UP IMINGS Symbol Parameter Maximum Units () PU-READ Power-up to Read Operation 00 µs () PU-WRIE Power-up to Write Operation ms ABLE : CAPACIANCE ( a = C, f= MHz, other pins open) Parameter Description est Condition Maximum C () I/O I/O Pin Capacitance V I/O = 0V pf C () IN Input Capacitance V IN = 0V pf 0 PGM.0 0 PGM.0 Note: () his parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ABLE : RELIABILIY CHARACERISICS Symbol Parameter Minimum Specification Units est Method N END Endurance 0,000 Cycles JEDEC Standard A () DR Data Retention 00 Years JEDEC Standard A0 V () ZAP_HBM ESD Susceptibility 000 Volts JEDEC Standard A Human Body Model V () ZAP_MM ESD Susceptibility 00 Volts JEDEC Standard A Machine Model I () LH Latch Up 00 ma JEDEC Standard Note: 0 PGM. () his parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 0

10 AC CHARACERISICS ABLE 0: SSEE00 READ CYCLE IMING PARAMEERS SSEE00-0 SSEE00-0 Symbol Parameter Min Max Min Max Units RC Read Cycle ime 0 0 ns CE Chip Enable Access ime 0 0 ns AA Address Access ime 0 0 ns OE Output Enable Access ime 0 0 ns () CLZ CE# Low to Active Output 0 0 ns () OLZ OE# Low to Active Output 0 0 ns () CHZ CE# High to High-Z Output 0 0 ns () OHZ OE# High to High-Z Output 0 0 ns () OH Output Hold from Address 0 0 ns Change 0 PGM 0. ABLE : SSLE00 READ CYCLE IMING PARAMEERS SSLE00-0 SSLE00-00 Symbol Parameter Min Max Min Max Units RC Read Cycle ime 0 00 ns CE Chip Enable Access ime 0 00 ns AA Address Access ime 0 00 ns OE Output Enable Access ime 0 00 ns () CLZ CE# Low to Active Output 0 0 ns () OLZ OE# Low to Active Output 0 0 ns () CHZ CE# High to High-Z Output 0 0 ns () OHZ OE# High to High-Z Output 0 0 ns () OH Output Hold from Address Change 0 0 ns 0 PGM.0 ABLE : SSVE00 READ CYCLE IMING PARAMEERS SSVE00-00 SSVE00-0 Symbol Parameter Min Max Min Max Units RC Read Cycle ime 00 0 ns CE Chip Enable Access ime 00 0 ns AA Address Access ime 00 0 ns OE Output Enable Access ime 00 0 ns () CLZ CE# Low to Active Output 0 0 ns () OLZ OE# Low to Active Output 0 0 ns () CHZ CE# High to High-Z Output 0 0 ns () OHZ OE# High to High-Z Output 0 0 ns () OH Output Hold from Address Change 0 0 ns 0 PGM.0 0

11 ABLE : PAGE-WRIE CYCLE IMING PARAMEERS SSEE00 SSLE/VE00 Symbol Parameter Min Max Min Max Units WC Write Cycle (Erase and Program) 0 0 ms AS Address Setup ime 0 0 ns AH Address Hold ime 0 0 ns CS WE# and CE# Setup ime 0 0 ns CH WE# and CE# Hold ime 0 0 ns OES OE# High Setup ime 0 0 ns OEH OE# High Hold ime 0 0 ns CP CE# Pulse Width 0 0 ns WP WE# Pulse Width 0 0 ns DS Data Setup ime 0 ns DH Data Hold ime 0 0 ns () BLC Byte Load Cycle ime µs () BLCO Byte Load Cycle ime µs IDA Software ID Access and Exit ime 0 0 µs SCE Software Chip-Erase 0 0 ms 0 PGM. Note: () his parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 0

12 RC AA ADDRESS A -0 CE# CE OE OE# V IH OLZ OHZ WE# CHZ DQ -0 HIGH-Z DAA VALID DAA VALID CLZ OH HIGH-Z 0 ILL F0.0 FIGURE : READ CYCLE IMING DIAGRAM hree-byte Sequence for Enabling SDP AS AH ADDRESS A-0 AAA CS CH CE# OES OEH OE# WP BLC BLCO WE# DH DQ -0 AA A0 DAA VALID SW0 SW SW DS BYE 0 BYE BYE WC 0 ILL F0. FIGURE : WE# CONROLLED PAGE-WRIE CYCLE IMING DIAGRAM

13 hree-byte Sequence for Enabling SDP AS AH ADDRESS A -0 AAA CP BLC BLCO CE# OES OEH OE# WE# CS CH DH DQ -0 AA A0 DAA VALID SW0 SW SW DS WC BYE 0 BYE BYE 0 ILL F0. FIGURE : CE# CONROLLED PAGE-WRIE CYCLE IMING DIAGRAM ADDRESS A -0 CE# CE 0 OE# OEH OES WE# OE DQ D D# D# D WC + BLCO 0 ILL F0.0 FIGURE : DAA# POLLING IMING DIAGRAM

14 ADDRESS A-0 CE CE# OEH OE OES OE# WE# DQ WC + BLCO WO READ CYCLES WIH SAME OUPUS 0 ILL F0.0 FIGURE : OGGLE BI IMING DIAGRAM Six-Byte Sequence for Disabling Software Data Protection WC ADDRESS A -0 AAA AAA DQ -0 AA 0 AA 0 CE# OE# WP BLCO WE# BLC SW0 SW SW SW SW SW 0 ILL F0. FIGURE : SOFWARE DAA PROEC DISABLE IMING DIAGRAM

15 Six-Byte Code for Software Chip-Erase SCE ADDRESS A -0 AAA AAA DQ -0 AA 0 AA 0 CE# OE# WE# WP BLC BLCO SW0 SW SW SW SW SW 0 ILL F0. FIGURE : SOFWARE CHIP-ERASE IMING DIAGRAM ADDRESS A -0 DQ -0 CE# hree-byte Sequence for Software ID Entry AAA IDA AA AA 0 BF DEVICE ID 0 OE# WP WE# BLC SW0 SW SW DEVICE ID = 0 for SSEE00 = 0 for SSLE00/VE00 0 ILL F0. FIGURE 0: SOFWARE ID ENRY AND READ

16 hree-byte Sequence for Software ID Exit and Reset ADDRESS A -0 AAA DQ -0 AA F0 IDA CE# OE# WP WE# BLC SW0 SW SW 0 ILL F.0 FIGURE : SOFWARE ID EXI AND RESE

17 V IH V H V H V IL INPU V L REFERENCE POINS V L OUPU FIGURE : AC INPU/OUPU REFERENCE WAVEFORMS 0 ILL F. AC test inputs are driven at V IH (. V) for a logic and V IL (0. V) for a logic 0. Measurement reference points for inputs and outputs are V H (.0 V) and V L (0. V). Inputs rise and fall times (0% «0%) are <0 ns. Note: V H V HIGH est V L V LOW est V IH V INPU HIGH est V IL V INPU LOW est ES LOAD EXAMPLE O ESER VCC RL HIGH 0 O DU CL RL LOW 0 ILL F.0 FIGURE : A ES LOAD EXAMPLE

18 Start See Figure Software Data Protect Write Command Set Page Address Set Byte Address = 0 Load Byte Data Increment Byte Address By No Byte Address =? Yes Wait BLCO Wait for end of Write (WC, Data# Polling bit or oggle bit operation) Write Completed 0 ILL F.0 FIGURE : WRIE ALGORIHM

19 Internal imer oggle Bit Data# Polling Page-Write Initiated Page-Write Initiated Page-Write Initiated Wait WC Read a byte from page Read DQ (Data for last byte loaded) Write Completed Read same byte No Is DQ = true data? Yes No Does DQ match? Yes Write Completed Write Completed 0 0 ILL F. FIGURE : WAI OPIONS

20 Software Data Protect Enable Command Sequence Write data: AA Address: Software Data Protect Disable Command Sequence Write data: AA Address: Write data: Address: AAA Write data: Address: AAA Write data: A0 Address: Write data: 0 Address: Load 0 to Bytes of page data Optional Page Load Operation Write data: AA Address: Wait BLCO Write data: Address: AAA Wait WC Write data: 0 Address: SDP Enabled Wait BLCO Wait WC SDP Disabled 0 ILL F.0 FIGURE : SOFWARE DAA PROECION FLOWCHARS 0

21 Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Write data: AA Address: Write data: AA Address: Write data: Address: AAA Write data: Address: AAA Write data: 0 Address: Write data: F0 Address: Pause 0 µs Pause 0 µs Read Software ID Return to normal operation 0 ILL F.0 FIGURE : SOFWARE PRODUC COMMAND FLOWCHARS 0

22 Software Chip-Erase Command Sequence Write data: AA Address: Write data: Address: AAA Write data: 0 Address: Write data: AA Address: Write data: Address: AAA Write data: 0 Address: Wait SCE Chip-Erase to FFH 0 ILL F. FIGURE : SOFWARE CHIP-ERASE COMMAND CODES

23 PRODUC ORDERING INFORMAION Device Speed Suffix Suffix SSxE00 - XXX - XX - XX Package Modifier H = leads Numeric = Die modifier Package ype P = PDIP N = PLCC E = SOP (die up) mm x 0mm W = SOP (die up) mm x mm U = Unencapsulated die Operating emperature C = Commercial = 0 to 0 C I = Industrial = -0 to C Minimum Endurance = 0,000 cycles Read Access Speed 0 = 0 ns 00 = 00 ns 0 = 0 ns 0 = 0 ns 0 = 0 ns Voltage E =.0V-only L =.0-.V V =.-.V 0

24 SSEE00 Valid combinations SSEE00-0-C-EH SSEE00-0-C-NH SSEE00-0-C-PH SSEE00-0-C-EH SSEE00-0-C-NH SSEE00-0-C-PH SSEE00-0-C-WH SSEE00-0-C-WH SSEE00-0-I-EH SSEE00-0-I-NH SSEE00-0-I-WH SSEE00-0-C-U SSLE00 Valid combinations SSLE00-0-C-EH SSLE00-0-C-NH SSLE00-0-C-WH SSLE00-0-I-EH SSLE00-0-I-NH SSLE00-0-I-WH SSLE00-00-C-U SSVE00 Valid combinations SSVE00-00-C-EH SSVE00-00-C-NH SSVE00-00-C-WH SSVE00-00-I-EH SSVE00-00-I-NH SSVE00-00-I-WH SSVE00-0-C-U Example:Valid combinations are those products in mass production or will be in mass production. Consult your SS sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: he software Chip-Erase function is not supported by the industrial temperature part. Please contact SS, if you require this function for an industrial temperature part.

25 PACKAGING DIAGRAMS pin index C L PLCS..0.0 Base Plane Seating Plane BSC BSC 0 Note:. Complies with JEDEC publication MO-0 AP dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.00 inches..pdipph-ill. -LEAD PLASIC DUAL-IN-LINE PACKAGE (PDIP) SS PACKAGE CODE: PH OP VIEW SIDE VIEW BOOM VIEW 0 Optional Pin # Identifier R. MAX..0 x R BSC BSC..00 BSC Min..0.0 Note:. Complies with JEDEC publication MS-0 AE dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.00 inches..plcc.nh-ill. -LEAD PLASIC LEAD CHIP CARRIER (PLCC) SS PACKAGE CODE: NH

26 PIN # IDENIFIER BSC Note:. Complies with JEDEC publication MO- BA dimensions, although some dimensions may be more stringent.. All linear dimensions are in millimeters (min/max).. Coplanarity: 0. (±.0) mm..sop-wh-ill. -LEAD HIN SMALL OULINE PACKAGE (SOP) MM X MM SS PACKAGE CODE: WH PIN # IDENIFIER BSC Note:. Complies with JEDEC publication MO- BD dimensions, although some dimensions may be more stringent.. All linear dimensions are in millimeters (min/max).. Coplanarity: 0. (±.0) mm..sop-eh-ill. -LEAD HIN SMALL OULINE PACKAGE (SOP) MM X 0MM SS PACKAGE CODE: EH Silicon Storage echnology, Inc. Sonora Court Sunnyvale, CA 0 elephone 0--0 Fax or Literature FaxBack --, International --