Agilent Bead Probe Technology

Transcription

1 Agilent Bead Probe Technology Page 1

2 Abstract Lead-free, shrinking geometries, new packages and high-speed signaling present new challenges for ICT. The impact will be more defects, loss of access, lower test coverage and higher warranty costs. It is the purpose of this presentation to show how access can be maintained even on highly dense gigabit logic boards. Page 2

3 PCB Technology Waves Continue BGA packaging continues to shrink RoHS is the law July 1, 2006 Lead-Free solders are more brittle and have higher melting point more BGA opens High-speed signaling becomes mainstream No ICT access at higher frequencies PCB density continues to rise Continuous pressure to eliminate testpads Limited Limited Access solutions (BSCAN, MagicTest, DriveThru, AwareTest) Page 3

4 High-Speed Signaling Wave High-Speed Signal Propagation (HSSP) is a coming wave in our industry. This will create a new class of defect effects we have not seen before. We need to prepare ourselves for this wave. Page 4

5 High-Speed Signaling Wave Moore s law continues unabated On-chip logic operates far faster than interconnect Logic density allows IC designers to throw gates at a problem Logic boards have no equivalent exponential advantage Elevated frequencies cause clocking problems Parallel busses are difficult to deskew Need to move to differential signaling, doubles pins Solution: Serialize/De-serialize (SERDES) technology Minimizes pins and board signals Embedded clock-in-data removes skew problems Page 5

6 High-Speed Signaling Wave Parallel Bus Architecture (the past) 64-Bit Single-Ended Bidirectional Bus IC2 IC 1 IC3 Master Clock CLK-1 CLK-2 Clock Distribution & Deskew CLK-3 Page 6

7 High-Speed Signaling Wave Parallel Bus Architecture TX Bit 1 RX Mission Logic Bit 2 Mission Logic Bit 8 Master Clk Page 7

8 High-Speed Signaling Wave Serial Bus Architecture (the future) 4-Bit Serialized Differential Buses IC 1 8-Bit Serialized Differential Buses IC2 IC3 CLK-2 CLK-1 CLK-3 Page 8

9 High-Speed Signaling Wave Serial Bus Architecture TX RX TX CLK Page 9 Mission Logic 8-Bit to 10-Bit Parallel-to-Serial Encoder 10-Bit to 8-Bit Serial-to-Parallel Decoder Mission Logic Recovered Clock

10 Interconnect Standards 2nd gen PCI-Express (5-6.25Gb/s) 6Gb/s SATA III 6.25Gb/s double XAUI AdvancedTCA (PICMG 3.x) VME320 XAUI 3.125Gb/s RapidIO 3GIO, PCI-Express 10Gb Ethernet VXS Backplane (VITA41) GigE Backplane (VITA 31.1) StarFabric Backplane(PICMG2.17) Serial Mesh Backplane(PICMG2.20) 3.125Gb/s 2.5Gb/s InfiniBand 2.5Gb/s Gb/s CoreConnect XAUI On Chip Flexbus 4 POS-PHY L3/L4 CSIX HyperTransport PCI-X 66 & Gb/s PCI 32/33 & 64/66 VME CompactPCI Fibre-Channel IEEE 1394 Serial ATA USB SCSI 1Gb Ethernet Chip-to-Chip Local Bus Backplane System Page 10

11 High Density PCB Wave Continuous pressure to eliminate testpads Consumes PCB real estate Adds to routing complexity Used only at ICT, adds no value to board No testpads for high speed nets Designers perceive risk in adding testpads ICT rapidly loses effectiveness with less than 100% access Limited Limited Access solutions (BSCAN, MagicTest, DriveThru, AwareTest) BSCAN requires DFT, expertise, power MagicTest and DriveThru address corner cases only AwareTest requires X-Ray inspection to perform like a tester Page 11

12 High Density PCB Wave Introducing Bead Probes Before: Add probe targets to a board layout and hit them with probes mounted in a test fixture. Problem: Probe targets disturb circuit layout. Solution: Figure out how to get access without changing the layout. New Paradigm: Place probe targets in a fixture and hit them with tiny probes mounted on the board. No Probe Targets Tx Rx Probe targets, symmetric and 50 mils apart Tx Rx Probe Targets, asymmetric and 50 mils apart Tx Rx Page 12

13 High Density PCB Wave Introducing Bead Probes Page 13

14 Idealized Beads Made from solder using our standard paste-reflow solder process along with all other solder features. End Section Side Section Solder Bead Trace Mask Bead Trace FR4 FR4 Page 14

15 Theory of Operation Solder deformation is the key to making bead probes work! Bead Bead Flattened Semi-minor axis B FR4 End Section Flattened Surface W Semi-major axis A Page 15

16 Bead Solder Mask and Stencil Stackup W L Cu Trace Solder Mask Opening Cu Trace D Stackup Stackup Solder Stencil Opening Page 16

17 Good view of Bead Probe Page 17

18 TDR of Ideal Trace versus 35 mil target Impedance in Ohms Z_p_std_tpt_5_3_0 Z_p_ideal_5_3_ Transit time for 3 inch trace Input discontinuity Ideal Trace time, nsec With 35 mil probe target Output discontinuity Page 18

19 TDR of Ideal, 35 mil and 9 Bead Probes About 0.1 the effect of a Via Z_p_bead_5_3_9 Z_p_std_tpt_5_3_0 Impedance Z_p_ideal_5_3_0 in Ohms trace with 9 bead probes time, psec Ideal Trace trace with 35 mil probe target Page 19

20 Eye of Ideal versus 35 mil test target Ideal Trace Trace with 35 mil test target p_ideal_5_3_0 Voltage p_std_5_3_0 Voltage time, psec time, psec 100 ps rise time, 5 GB/s, 50 bit random pattern. Page 20

21 Eye of Ideal versus 9 bead probes Ideal Trace Trace with 9 bead probes p_ideal_5_3_0 Voltage P_BEAD_5_3_9 Voltage time, psec time, psec 100 ps rise time, 5 GB/s, 50 bit random pattern. Page 21

22 Benefits Improved test access. Now have a method to add to high speed lines that does not affect signal integrity. Also on dense board have a method to add test coverage. Uses standard ICT methods. One the CAD translation software is configured, should be able to use a standard process for bead probe. Can have multiple bead probe locations for a node. Can help reduce/eliminate the need for 50mil and 39mil probes, reducing fixture costs and increasing fixture reliability. Page 22

23 Agilent Bead Probe Technology Summary Simple Design No complex signal trace layout design Board Independence No risk to signal integrity Simple Manufacturing Process Using existing screen printing and Re-flow processes No additional process step needed Maximize Fault Coverage Multiple (Alternative) access points on single signal trace Reliable electrical contact - Bead is self-cleaning (oxide removal) on contact with Test Probe Multiple Re-probing possible Agilent Bead Probe Technology is a proprietary design and manufacturing methodology for Test Probes on PCB signal traces. 15 Patents surrounding the design, manufacturability and measurement of electrical signals using this technology has been filed. Agilent grants the use of Bead Probe Technology on Agilent ICT - free license available Visit Page 23