Cyclone III LS FPGAs Altera Corporation Public
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- Reginald Ellis
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1 Cyclone III LS FPGAs
2 Introducing Cyclone III LS Devices Low power 200K LE for under 0.25 Watt TSMC 60-nm low-power (LP) process Quartus II software power-aware design flow Broadcast Industrial Military Information assurance design capabilities Anti-tamper Design security Design separation IP, design examples, etc. High functionality Densities ranging from 70K to 200K LEs Up to 8 Mbits of embedded memory Up to 396 embedded multipliers Industry s lowest power FPGAs with security
3 High-Functionality AND Low-Power Solution Increase processing bandwidth and lower power 200K logic elements, 8.2 Mbits of embedded RAM, and x18 multipliers for less than 0.25 Watt static power Increase energy efficiency or extend battery life Cyclone III LS FPGAs have the market s lowest power profile Jump-start new designs using reference examples Re-use Altera s Video and Image Processing (VIP) Suite: IP, kits, and reference designs Protect IP investments in new products Cyclone III LS FPGAs enable hardware-based security Cyclone III LS FPGA provides DSP and data processing AND low power
4 Extending Low-Power Leadership Cyclone III FPGA Cyclone III LS FPGA Static power (mw) Density (KLE) Double the resources for less than 0.25 Watt At 85 C junction temperature
5 The Value of Security Features estimated competing gray market sales cost the company between $200 and $300 Million in lost revenue during FY One out of every ten IT products contains counterfeit semiconductors. Security critical for revenue and brand image Sources: New Momentum White Papers ( Fighting High Tech Counterfeiting with High Tech Solutions and Intellectual Property Fraud Prevention
6 Protect IP With Anti-Tamper and Design Security JTAG port protection to prevent reverse engineering Flash 256-bit AES encryption for design security System controller Security features CRC to monitor for configuration changes On-chip oscillator as an uninterruptible clock source for system monitoring Zeroize the device if tampering is detected The most comprehensive IP protection in an FPGA
7 Design Separation Feature XOR Example design requirements Redundancy required for high up-time and reliability Reduce board complexity Benefits Easily design single chip redundancy and information assurance applications Protecting integrity/processing of data inside FPGAs
8 Data Assurance With Design Separation Feature logic User Logic + Nios processor Processor Create multiple isolated blocks Physically User logic User logic User Logic logic + Nios processor Processor User logic isolated partitions with design separation Protect against time-dependent faults and SEU Increase system up-time Achieve a higher level of integration on a single device
9 Example - Video and Image Processing Trends Video and imaging application examples Medical/industrial/military imaging Video surveillance Video conferencing High functionality Video standards continue to evolve, driving higher data rates (e.g. H.264) Processing requirements are outpacing DSP performance Lower R&D $ ASIC design cycles do not meet time-to-market needs Frequently require re-spins and sizable NRE Lower power Extending battery life or increasing energy efficiency Thermal dissipation can interfere with sensitive CCD image capture devices
10 Example - Industrial Trends Standardization of Industrial Ethernet (IE) protocols FPGA supports all IE protocols with one hardware platform Energy efficiency FPGA enables cost-effective variable motion control solutions, increasing efficiency by up to 85% Secure IP for revenue protection The most comprehensive IP protection in an FPGA Long product life cycles Obsolescence-proof to avoid costly re-designs Source: SIA
11 Redundancy in Industrial Motor Control Cyclone III FPGA Cyclone III LS FPGA X Nios II processor Nios II processor X Nios II processor X X XOR XOR Nios II processor Motor control Motor control Reduce board space by up to 50% with design separation Reduce BOM cost with integration Secure IP with anti-tamper and design security
12 Example - Military Market Trends Size, weight, and power (SWaP) Support next-generation software-defined radio (SDR) waveforms with small footprint and low power, e.g. MUOS, SRW Night-vision goggles Secure communications Crypto modernization moving towards standardization Interoperability Common criteria for equipment in US, Canada, and Europe NIST, FIPS, IPsec COTS Reduce cost Reduce time to market Increased product life cycle with COTS products
13 Existing SDR Application RF front end Receiver A/D DDC, filtering Demodulation IFFT Channel decoding Source decoding Host CPU Transmitter D/A DUC, filtering Modulation FFT Channel coding Source coding Cyclone III EP3C120 under 0.25 Watt static power Next-generation SDR waverforms require: More memory and logic resources for networking in the field Low power for extended battery life Small footprint for board space Data security IP security and anti-tamper
14 Next Generation SDR Cyclone CycloneIIIIIILS LSFPGA FPGA for forunder under W Watt RF front end RF front end Receiver A/D DDC, filtering Demodulation IFFT Channel decoding Source decoding Host CPU Transmitter D/A DUC, filtering Modulation FFT Channel coding Source coding Receiver A/D DDC, filtering Demodulation IFFT Channel decoding Source decoding Host CPU Transmitter D/A DUC, filtering Modulation FFT Channel coding Source coding Security Reduce board space by up to 50% Increase battery life by up to 2X Single-chip secure SDR solution
15 Cyclone III LS FPGAs - Device Resources Now shipping* LEs Memory (Mbits) # of M9K blocks 18 x 18 multipliers EP3CLS70 70, EP3CLS , EP3CLS ,848 EP3CLS200* 198,464 Product line PLLs Global clocks Static power* (mw) Core (MHz) Memory (MHz) Multipliers (MHz) LVDS (Mbps) DDR / DDR2 (Mbps) QDR II (Mbps) Performance shown for slowest speed grade (C8) * Pstatic from EPE, junction temperature = 85 C Security features
16 Device Packaging and I/O Matrix U mm 19 x 19 Product line F mm 23 x 23 F mm 29 x 29 I/O LVDS I/O LVDS I/O LVDS EP3CLS EP3CLS EP3CLS EP3CLS Relative size: Highest density + smallest package Commercial (-7, -8) and industrial (-i7) speed grades supported
17 Cyclone III LS Key Architectural Features 60-nm lowpower process Up to 8-Mbit memory Anti-tamper and design security Staggered I/O ring, up to 413 user I/Os 640-Mbps LVDS interface K logic elements at 402 MHz Up to 396 multipliers for DSP 333-Mbps DDR2 interface Dynamically configurable PLLs and 20 global clocks
18 Cyclone III LS FPGAs - Rollout Schedule Device EP3CLS200 General rollout June 2009 ES 4Q Production Commercial -7 Industrial -7 Commercial -8 4Q Q 2009 F484 July F780 Aug. Dec Dec Nov EP3CLS150 4Q 2009 EP3CLS100 1Q Q 2010 EP3CLS70 2Q Q 2010 Now shipping
19 Cyclone III LS FPGA Dev Kit Shipments begin Sept. Oct. 2009
20 Summary The most comprehensive IP protection in an FPGA Anti-tamper to prevent cloning or counterfeiting Design security using state-of-the-art 256-bit AES Design separation for information assurance Design examples to jump-start your design The FPGA industry s most efficient low-power devices per density and package size 200K LE density for under 0.25 Watt (static power) 100K LE density in 19x19 mm and 200K LE in 23x23 mm Increased data and imaging processing 100% more on-chip memory 80% more on-chip multipliers FPGAs and software shipping now
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