When addressing VLSI design most books start from a welldefined

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2 Objectives An ASIC application MSDAP Analyze the application requirement System level setting of an application Define operation mode Define signals and pins Top level model Write a specification

3 When addressing VLSI design most books start from a welldefined specification. They focus more on the design, while the top-level system setting as well as the relationship between the application and its operation environment is often given less attention. From the ASIC design point of view, to develop a correct and complete specification is actually the first step in the design flow. This less addressed issue is one of the most important steps in the whole design flow. In this chapter we study how to derive a specification by analyzing the application from the angle of VLSI design perspective.

4 The specification of an IC design is a set of requirements which should be met and hold true across all possible operating requirements of process, voltage and temperature, as well as across all mismatches for a particular circuit. An example specification of a circuit like an operational amplifier would be open loop gain in db. The open loop gain of the amplifier is defined as the DC gain when the operational amplifier is in an open loop.

5 For digital circuit design, a specification is usually one document that can be used by the circuit designer to implement the circuit in a chip. It includes functionality, specific computation algorithm and method, clock frequency, supply power, interfaces, communication protocol, definition of pins, type of package and etc. The process of specification development is a step-by-step refinement of clarifying the technical requirements needed in the chip design. How much detail a spec contains depends on the particular situation, but it at least covers all the necessary information needed for the design in an unambiguous manner.

6 It is often the case that the original application appears in a nonengineering manner. Many technical terms and restrictions for a chip design may be irrelevant to the original application, and hence they are often ignored when the application is first presented. For instance, consider the application to design an ASIC chip that computes a filter function specify the N Y(n) = h(k)x(n k) k =0 where the application most likely will filter s order N, its coefficients h(k), and the required precision. On the other hand, information such as the number of pins, I/O protocols, and signal definitions may not be mentioned due to their irrelevance to the filter design. IC designers need either to communicate with the customer to obtain the concerned information or to make proper assumptions based on their knowledge of VLSI design and understanding of the application

7 Specification development is the first step in an ASIC design process.

8 A critical task in the specification development process is to obtain a complete knowledge of the application through thorough analysis. It is the starting point to make a functionally correct design. A deep understanding opens the door to multiple design options, which, in turn, will result in a better ASIC implementation.

9 We will discuss the specification developing process with the following specific topics: Top level view of the application and its specific requirements System settings of an application Signals and I/O protocols Power supply, temperature range, package requirement and etc. Top-level modeling

10 The application MSDAP originates from a research paper Included in Appendix A. MSDAP will be used as an example for our discussion and practice. It asks to design an ASIC chip based on a particular algorithm that facilitates low power application, such as the circuit used for disposable hearing aid. By examining this original application, readers can easily observe the gap between the description of a typical application and the specification required for an ASIC chip design. One can see the necessity and importance of deriving a specification step-by-step from a given application before starting other design tasks.

11 Refer to Appendix A Review the computation of linear convolution A quick glance at the specific computation requirement by MSDAP 1-bit shift Use POT representation Optimum POT representation is difficult to be obtained Shall use coefficient u in the design, instead of h It is a real time processing system Clearly, many information for the chip design is missing, such as the signal definition, number of pins and etc.

12 The frame of this spec development process is shown in the following figure, where major involved tasks are shown. Once they are completed, we can put the results in a formal format which will serve as the specification of the chip to be designed.

13 Transform the linear convolution into a series of 1-bit shifting and accumulation

14 An 7-th order filter example (in Appendix A)

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16 Top behavior model for this computation

17 Exercise 3-1

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19 The input format for the C-program of Exercise 3-1. This format is also adopted late in the implementation of the MSDAP chip.

20 The C-program for the above exercise is independent from how the chip is designed. Therefore it provides the expected correct outputs for all to be designed ASIC chips which implements MSDAP. For obvious reasons, this property is very important since the correct outputs must be independent from the specific implementation. A sample C-program for Exercise 3-1 is given in Appendix B. This program mimics the computation of the MSDAP. It can be used to generate the standard reference data for the design debugging due to its independency from any specific chip implementation.

21 It was mentioned in the MSDAP paper that for a given number its POT representation is not unique. As a matter of fact, to obtain the optimum POT representation is the challenging NP-problem. Considering that how to obtain the POT representation is not an issue of the concerned application, we can reasonably assume that the coefficients are given in the POT format for our design. Note that for a given set of POT coefficient set, the corresponding set u is unique. Therefore we can further assume that the coefficient set actually is given in terms of set u. This will greatly reduce the computation load of the MSDAP.

22 Though not explicitly pointed out in the MSDAP paper, it is not difficult to see that a fixed-point computation is actually implied. As a matter of fact, fixed-point numbers are useful for representing fractional values in native two's complement format and provide improved performance or accuracy for the application at hand. Most low-cost embedded microprocessors and microcontrollers use such format. In the simulation program of Exercise 3-1one needs to exactly mimic the fixed-point operation, instead of using floating point computation.

23 For the considered filter, both inputs and coefficients are specified as 16-bit two s compliment numbers. Since the output is the modified audio signal, it naturally should have the same accuracy as the input. In this regard, the output is 16-bit two s compliment numbers as well. To round off the output to 16-bit may bring up the issue of how much accuracy to keep during the computation. To simplify the project, we also assume the full accuracy 40-bit as we did in the previous Exercise 3-1 and in the program in Appendix B. One should understand why 40-bit is adequate in this case.

24 The MSDAP should be a real time processor based on the nature of its application. There should be no output data accumulation in the chip, except for a reasonable latency introduced by the computation. The MSDAP aims at a low power application. A sleeping mode should be considered in the implementation when there is no input. A reset mechanism should generally be available in the chip. Now, we have analyzed the application, its special implementation (computation) requirement, and the other relevant issues to this project. More importantly, we have had a top-level view of the application from the perspective of ASIC design. This completes the first part of the specification development process.

25 In many non-engineering oriented ASIC applications, it is often very vague on how a system is set up. The considered MSDAP is a typical instance that well illustrates this phenomenon. In the MSDAP paper it doesn t say if the clock is generated on the chip or if it is provided from the outside, whether the input/ output is transmitted in serial or parallel manner, and etc. These questions need to be answered before we can really start to design the chip. We now look at this issue and fill in the necessary information if it is not available from the original MSDAP paper

26 The MSDAP implements a filter function on the input audio samples. We can draw a block diagram as shown in Figure 3 4 that represents the place of the MSDAP in the entire system. The input sample data is converted into a digital format by an analog to digital converter (ADC) and is fed to a controller in the system. This controller then transmits this data synchronously to the MSDAP that processes the data. The output is sent back to the controller, which transmits it to a digital to analog converter (DAC) in the system.

27 The system that hosts MSDAP (Figure 3-4)

28 The audio data transmitted between ADC/DAC and the controller is embedded in a framed format where each frame contains one sample of 16-bit data. The controller extracts the audio data from the frame and sends it to the MSDAP in a stereophonic mode. In this mode, both left and right channels are presumed to have been simultaneously sampled. The frame format used to convey audio data between the controller and the MSDAP is sampled at a frequency of 48 KHz. Each frame is divided into 16 timeslots, so that the data rate is 768 KHz.

29 The audio sample word is linear in two s complement form and the sign bit is carried by timeslot 0. The controller sends the sampled audio data and data frame signal to the MSDAP in a serial manner. The original MSDAP doesn t mention the data format. In Figure 3 4 there are several communication signals between the MSDAP and the controller. This set of signals are not specified in the original MSDAP.

30 The signal directions are also indicated in the figure. Definitions of these signals depend on how the MSDAP works with the controller. A Finite State Machine (FSM) type description can be used to address the problem at hand, which precisely defines the execution mode of the MSDAP in the considered system environment. We introduce eight states to represent the working modes of the MSDAP. The state diagram is shown in Figure 3 5. An FSM is used to formally model the operation mode

31 The following assumptions have been made when introducing this FSM. To save the number of pins, the coefficients for the left (right) channel are sent into the chip using the input data port InputL (InputR). Thus, there are no dedicated pins for sending the coefficients. When the chip is in sleeping mode, it shall shut down the unnecessary clocks and operations to save energy. If the external controller detects InReady = 0 sent by the chip, controller will not transmit Dclk, Frame or any input samples to the chip until the InReady = 1 is detected. If the external controller detects InReady = 1 sent by the chip, the continuing inactive time to Frame will not be more than 16 data clock cycles.

32 The FSM that describes the operation mode of the MSDAP

33 The above finite state machine works as follows:

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35 Using the above FSM, we have described the way that the MSDAP works with the controller, or in other words, with its environment. Since FSM is the most popular way to describe the control flow of a VLSI system, we have in this sense derived the second part of the specification: the application system setting. The above system setting can be formalized using VHDL to avoid the ambiguity of human language. Also, one can run a simulation of the VHDL code to verify the transition between states and examine the interaction between the MSDAP and the system it is a part of. Appendix C shows an example VHDL code and the simulation result of this FSM. Such VHDL code can later be used as a part for the top-level behavior model of the MSDAP

36 Using the VHDL code, which describes the operation mode of the MSDAP, and adding a behavior model for the operation at each state, for instance the behavior model in State 6 for the convolution computation Eq. 3 3, we can have a high level behavior model for the MSDAP. This is a homework assignment. This behavior model will be used for system level simulation and verification. Note that this behavior model doesn t include the chip architecture and RTL implementation. We have not designed the ASIC chip for the given application yet, but we have obtained a behavior model which can be used in higher level system development where the MSDAP is a part of the system.

37 The previous section has defined the working modes as well as the communication between the MSDAP and the system controller. The system operation setting is formally described by the FSM in Figure 3 5. The communication is carried out by signals and therefore we need to define the corresponding signals. There are two issues: one is the signal data format and the other is its waveform. We further define the signals related to the I/Os of the MSDAP.

38 Pins and their assignments Pins are the physical elements that carry the I/O signals. In general, pin assignment depends on the packaging, chip floor plan, and the system PCB layout. Due to the performance requirement, some signals needs more than one pin. For example, it is a common practice that the power supply takes a pin on each side of the chip in order to reduce the voltage drop and fluctuation problem. In today s high-end VLSI application, the number of available pins in a chip is always a restriction.

39 The pins and their assignments in the MSDAP chip are shown in Figure 3 6.

40 Data format and their waveform

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49 At this point, we have completed the third part of specification development with a complete I/O signal definition and communication protocols. The top-level view of the application derived in the first part, the system operation setting derived in the second part, and the I/O definitions and protocols derived in this part together comprise the specification for a chip design. A sample specification for the ASIC chip implementing the MSDAP can be found in Appendix D. The designer now can start the next task in the design flow.

50 Three major components of the specification of the MSDAP

51 Other Issues of the Specification In real industrial practice, there are some other requirements that need to be specified. These items include the temperature range, supply voltage, package requirement and etc. Those requirements usually come from the customer or system specification and it is not difficult to obtain them. The specification for a chip design in general will be different from that of an IC product. However, the reader may have already noted that there are many similarities between them. For instance, the system setting for an ASIC chip design is similar to how to use this chip. Therefore, it is helpful to study an IC product specification to see what a reasonable system setting is.

52 We have discussed how to develop a spec for ASIC chip design. We have shown the importance of understanding the application and any special requirements. We see that many items in the spec are actually implied by the application and we need to figure them out based on the correct understanding of the application. Three major components in the spec are: top level view of the application, system setting, and I/O definition and protocols. It is important to describe these items in precise terms.

53 1. Write a VHDL program based on the computation method proposed in the MSDAP. You need to use fixed point computation. 2. Write a complete specification of MSDAP. 3. Why is a behavior model important for verification and debugging in the design process? 4. Write a behavior model in VHDL of the MSDAP based on the specification. 5. Write a test bench to test the behavior model of MSDAP. 6. Why is the clock rate related to the power consumption of a digital system? 7. Estimate the system clock rate of the MSDAP. 8. If after the reset the MSDAP needs to read in coefficients again, how do you change the operation model described by the FSM?