PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing

Transcription

1 Abstract PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing Joan Gibson November 2006 SR-TN062 Add-in cards designed for PCI Express require numerous tests to assure inter-operability with different systems. This document describes testing to verify transmitter compliance with the PCI Express Card Electromechanical Specifications Revision 1.0a [i] and Revision 1.1 [ii], and highlights three important areas in compliance testing: Accurate views for de-emphasis measurements Edge density requirements for clock recovery The speed of making mask tests Table of Contents Introduction...2 Measuring De-Emphasis...3 Clock Recovery Function...4 PC Power Supply...4 PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing Procedure...5 Transmitter Compliance Testing Example...7 Summary...13 Appendix A: Using External 100 MHz Clock to Remove Intrinsic Jitter...13 Appendix B: Analyzing Jitter...14 References...15

2 2 Introduction PCI Express is an I/O interconnect bus standard that expands on the original PCI computer bus. It is based on a much faster serial communications system than the traditional PCI parallel data bus. PCI Express is a two-way, serial connection that carries data in packets along two pairs of point-to-point data lanes. PCI Express add-in cards plug into a connector on a backplane or system board and are mounted in a chassis slot. PCI Express Gen1 cards support a data rate of 2.5 Gb/s; Gen2 supports both 2.5 Gb/s and 5.0 Gb/s data rates. Compliance testing to the Revision 1.0a and Revision 1.1 specifications is currently being done. The latest specification information for add-in cards is contained in the PCI Express Card Electromechanical Specification, which is a companion for the PCI Express Base Specification. Testing PCI Express Gen1 Add-In Card Transmitters (Figure 1) requires jitter analysis and mask testing of both the transition bit and the de-emphasis bit. De-emphasis is used to reduce intersymbol interference and improve data integrity, and is required in transmitters for add-in cards 1. Eye diagram measurements for Revision 1.0a testing require measurements to be made over any 250 consecutive Unit Intervals (UIs) 2. When testing to the 1.1 specification, however, the sample size requirement increases to 1 billion UIs 3. Traditional real-time oscilloscopes can verify compliance for the 1.0a specification by capturing the data quickly and then using a post-processing program to determine whether the specifications have been met. This process becomes more difficult and time consuming with the sample size requirement of the 1.1 specification. Figure 1. PCI Express Gen1 add-in card This paper describes the various tests required for PCI Express add-in card transmitter path compliance through a practical example using SyntheSys Research s BERTScope. The BERTScope displays the measurements on the screen, visually showing PASS/FAIL compliance results without post-processing. Mask tests can be performed in less than one second (including processing time). This equipment can also generate jitter for receiver testing (not covered in this paper). 1 PCI Express CEM Specification 1.0a and 1.1, section PCI Express CEM Specification 1.0a, section PCI Express CEM Specification 1.1, section 4.7.1

3 3 Measuring De-Emphasis De-emphasis must be implemented when multiple bits of the same polarity are output in succession. Bits following a transition bit are driven at a differential voltage level below the first bit (see Figure 2) 4. Figure 2. Transmit parameters showing de-emphasis with a single polarity and with an eye diagram De-emphasis is calculated by: VTX-DE-RATIO = 20LOG10(VTX-DIFF-PP/VTX-DE-EMPH-PP), as shown in Figure 2. The eye height of the transition bit is larger than the subsequent bits. The specifications account for this with a different mask for transition bits and non-transition bits. For a transmitter to meet the specifications, it must pass both eye mask tests. It is therefore important that the transition bit eye and the non-transition bit eye be easily distinguished from each other on the display. 4 PCI Express 2.0 Base Specification, section

4 4 Clock Recovery Function The PCI Express Base Specification Revision 1.0a [iv] and Revision 1.1 [v] require compliance measurements to be made using a clock recovery function. The Clock Recovery must be set to: 1.5 MHz Bandwidth 50% Edge Density 1 st order, which means 0 db Peaking The clock recovery settings shall remain unchanged, using the above values even if the edge density of the real data deviates from the nominal 50%. If a clock recovery function that tracked the real data s edge density was used, the resulting measurements would be incorrect. The errors would be caused by the difference in the loop bandwidths. In the example that follows, the SyntheSys Research BERTScope CR can be set to either fixed edge density or tracking. The default setting is fixed edge density, as per all current standards that we are aware of. PC Power Supply The PCI Express Compliance Base Board requires a power supply for operation. A common method of powering the test board is to use a power supply from a PC. A quick practical note is that some PC power supplies are equipped with load-sensing capabilities, such that if insufficient current is being drawn from the supply, it will shut down. Since most add-in cards draw very little current, an additional load must be connected to the supply for the supply to turn on properly. The example in this document uses a disk drive for this purpose.

5 5 PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing Procedure Transmitter testing of a PCI Express Gen1 card can be done quickly using the following procedure. All specifications are referenced from Section 4.6 of the PCI Express Card Electromechanical Specifications, Revision 1.0a [i] and Revision 1.1 [ii]. Figure 3. PCI Express Gen 1 add-in card transmitter testing flowchart

6 6 Figure 4. Calibration phase block diagram Figure 5. Test phase block diagram

7 7 Transmitter Compliance Testing Example Stepping through the flowchart in Figure 3, an example transmitter test of a Gen1 PCI Express add-in card using a SyntheSys Research BERTScope is shown in Table 1 (following). The general test setup is shown in Figure 6. Figure 6. Basic test setup showing the main elements

8 8 Cable Considerations Cable quality can affect measurement accuracy. High quality, matched, RF cables should be used for the data connections. The clock cable must be tuned to the length of the RF cables to properly align the data and clock. This is especially important when SSC is employed. Refer to The Anatomy of Clock Recovery, Part 2 5 for additional information. The SyntheSys Research BERTScope CR has an option to provide the matched set of cables. Table 1. Task Step by step illustrations of a sample PCI Express add-in card transmitter compliance test Step 1: Set up clock recovery Select the PCI Express Standard labeled PCIe-1 (1.5) on the CR (all parameters will be automatically set from this standard selection, including 1.5 MHz Loop Bandwidth, 50% edge density, and 0 db peaking ) Assure the sub-rate is turned on and set to 1 (the default value) Set the Phase Error limit to 90% (default value is 50% but the 90% setting will allow you to measure easily on DUTs with large jitter) Explanation/Results Selecting the correct PCI Express standard will automatically set all the necessary parameters on the Clock Recovery instrument. Step 2a: Determine insertion loss Set amplitude on BERTScope to 800 mv p-p (400 mv differential) Set data rate to 2.5 Gb/s Set pattern to 1100 Display Eye Diagram and measure amplitude Calculate percent difference between set amplitude and received amplitude Using the block diagram in Figure 4 as a guide, connect the BERTScope and BERTScope CR. The BERTScope s Pattern Generator is used to create a data pattern (in place of the PCI Express add-in card) in order to measure the insertion loss of the system. 5 The Anatomy of Clock Recovery, Part 2, sections 11 & 13.

9 9 Task Explanation/Results Insertion loss caused by cables is: 1 (measured amplitude)/(set amplitude) = 681.6/ = 0.15 = 15% loss Step 2b: Adjust the mask amplitude for the insertion loss of the system Reduce the eye mask amplitude by the insertion loss Step 3: Configure setup for testing Losses caused by cables in the test system should not cause a device to fail a mask test. Therefore, use the percentage calculated above to adjust the eye mask amplitude, in this example by 15%, so that devices do not fail unnecessarily. Adjustment is done in the Mask Test view under Eye Setup. Refer back to Figure 5 to configure the equipment for testing. The Pattern Generator on the BERTScope is disconnected and the PCI Express add-in card is connected, providing the data stream to the BERTScope Clock Recovery instrument.

10 10 Task Step 4: Measure mask of de-emphasized bit Set the depth to 2000 Mask must be centered with respect to the jitter median (this example uses mask CEM 1.02_Add_In_Card_TX Compliance Mask_TX_A_d_360mV ) Explanation/Results The specification requires that the mask be tested over at least 250 consecutive TX UIs. This is to ensure that all combinations of the compliance pattern are at least tested several times. The specification actually requires the mask to be met over any 250 consecutive UIs. In this example using the BERTScope, 2000 UIs are tested within one second, providing eight times the required depth. The mask remains green, showing no failures for the 2000 waveforms. This simple test verifies VTXA_d, T TXA, and JTXA-MEDIAN-to-MAX-JITTER from the PCI Express Card Electromechanical Specification (section 4.7.1) for the deemphasized bit. The number of waveforms can be increased to verify compliance to a greater depth.

11 11 Task Step 5: Measure Q-factor of de-emphasized bit De-emphasis voltage measurements are referenced to the center of each UI. Set markers at the center of the bit and then measure Q-factor at the markers Add the mean numbers to get the amplitude of the deemphasized bit (this becomes the numerator when calculating de-emphasis) Step 6: Measure mask of transition bit Set clock recovery to sub-rate of 5 Turn on the mask and move it to the correct bit Assure the depth is still set to 2000 Mask must be centered with respect to the jitter median (this example uses mask CEM 1.02_Add_In_Card_TX Compliance Mask_TX_A_514mV ) Explanation/Results Amplitude = = 545 mv For an 8b/10b signal, setting the sub-rate to five will allow the first five bits to be displayed, and then the next five bits to be overlaid on top of the first set. From the display, the transition bit can be easily seen. The mask is positioned in the transition bit. The mask remains green if no failures occur. This simple test verifies VTXA, TTXA, and JTXA-MEDIAN-to-MAX-JITTER from the PCI Express Card Electromechanical Specification (section 4.7.1) for the transition bit. The number of waveforms can be increased to verify compliance to a greater depth.

12 12 Task Step 7: Measure Q-factor of transition bit De-emphasis voltage measurements are referenced to the center of each UI. Set markers at the center of the bit and then measure Q-factor at the markers Add the mean numbers to get the amplitude of the transition bit (this becomes the denominator when calculating de-emphasis) Step 8: Calculate de-emphasis Divide the amplitude calculated for the de-emphasized bit in Step 4 by the amplitude calculated for the transition bit in Step 6. This is the de-emphasis and must be between 3.0 db and 4.0 db Step 9: View Unit Interval and Data Rate The eye diagram view displays various measurements Explanation/Results Amplitude = = 638 mv De-emphasis = 545/638 = = 1.37 db Since the specification calls for 3.0 db to 4.0 db of de-emphasis, this add-in card would fail the test. From the eye diagram, other information is available. Shown here are the Data Unit Interval and the Data Rate.

13 13 Summary Using the PCI Express Card Electromechanical Specifications Revision 1.0a and Revision 1.1 documents, we have looked at a process for measuring the transmitter characteristics of a PCI Express Gen1 Add-in Card Transmitter. Using the SyntheSys Research BERTScope and BERTScope CR: Measurements of the transmitter eye mask were performed quickly, with the ability to measure to a depth of in seconds. Clock Recovery Function was properly implemented. De-emphasis was easily and accurately calculated using Q-factor. The methods shown here have been used successfully to test devices at Compliance Workshops. Appendix A: Using External 100 MHz Clock to Remove Intrinsic Jitter Using a low-noise external 100 MHz clock in place of the internal clock on the Compliance Base Board allows you to see the jitter on the add-card without jitter caused by the test board clock. The SyntheSys Research BERTScope is capable of supplying such a clock. Follow these steps to configure the test setup for an external 100 MHz clock: 1. Modify the Compliance Base Board to accept an external clock (refer to the Base Board manufacturer for details). 2. Using high quality, matched RF cables, connect the SyntheSys Research BERTScope and BERTScope CR as shown graphically in Figure 7. Figure 7. Measurement setup using an external 100 MHz clock 3. On the BERTScope: a. Set the synthesizer to 0.1 GHz. b. Set Clock Out Amplitude to 800 mv. c. Set Clock Out Offset to 400 mv. d. Assure that Clk+ and Clk are linked. e. Assure that all stresses are turned off.

14 14 Appendix B: Analyzing Jitter The different specification versions for PCI Express have different jitter requirements. In version 1.1, jitter is specified to an equivalent depth of 10-6 and To conveniently obtain these different jitter values and to better understand the device s jitter margins, it is possible to use the BERTScope s jitter analysis. The Jitter Peak measurement (Figure 8) measures the jitter present on the input, and separates the jitter components present on the signal in the way described by MJSQ [vii]. Figure 8. Jitter Peak Screen Peak-to-Peak Jitter is given by the Total Jitter (TJ) number, which by default displays the value for depth. By clicking on the purple area, it is possible to configure the measurement for other depths, such as 10-6 using a touchscreen keypad (Figure 9). Alternatively, the raw measurements may be exported for further calculation or modeling (Figure 10). Figure 9. Jitter Peak measurement configuration screen

15 15 Figure 10. Jitter Peak raw data table References [i] PCI Express Card Electromechanical Specification, Revision 1.0a, April 15, Downloadable at (membership required). [ii] [iii] [iv] [v] [vi] [vii] PCI Express Card Electromechanical Specification, Revision 1.1, March 28, Downloadable at (membership required). PCI Express 2.0 Base Specification, Revision 0.9, August 8, Downloadable at (membership required). PCI Express Base Specification, Revision 1.0a, April 15, Downloadable at (membership required). PCI Express Base Specification, Revision 1.1, March 28, Downloadable at (membership required). The Anatomy of Clock Recovery, Part 2, SR-TN059, March Downloadable at MJSQ: Methodologies for Jitter and Signal Quality Specifications is a document written as part of the INCITS project T Rev 14, 9 th June Copyright 2006 SyntheSys Research, Inc. All rights reserved.