High-speed I/O test: The ATE paradigm must change

Transcription

1 High-speed I/O test: The ATE paradigm must change 2005 VLSI Test Symposium Session 4C Burnie West May 2005

2 Outline The brave new world Test methodology PHY testing Functional testing ATE specifications 2 VTS May 2005

3 Where we are going ITRS prediction source ITRS 2004 today frequency(ghz) data rate (Gbps) lithography node 250 embedded clock HSIO source-sync HSIO 90 bus clock OTA YEAR OTA - picoseconds 3 VTS May 2005

4 Evolving ATE Requirements Stimulus Variation to validate DUT receiver performance HSIO Input Datasets Start Input Formatting Subsystem D U T Bit Sync Bit Stream ATE Pattern Partitioning Manager Subsystem ATE Sea of Memory Analytical qualification of DUT transmission performance P / F Functional test datasets Captured DUT Data Structural test datasets 4 VTS May 2005

5 100 Years of Moore s Law 5 VTS May 2005

6 Test methodology Traditional methods I/O parameters Setup time / Hold time / Transition time Functional test Stored response Synchronous clock domains High speed serial PHY parameters Clock recovery / Jitter / Bit Error rates Functional test Non-deterministic behavior Asynchronous clock domains 6 VTS May 2005

7 PHY Test issues Rx Data Reg CDR DUT Rx Tx CDR intrinsic jitter (Rj) CDR output vs data center CDR tracking vs Freq ( filter BW) Dj Equalizer testing PLL Data Serializer DUT Tx PLL jitter (Rj) Output stage Bandwidth (Dj) Pre / De emphasis 7 VTS May 2005

8 DUT / ATE Interconnect Path bandwidth 3X carrier freq ATE to fixture to DUT Issues Transmission lines Material Vias Trace density Test socket 8 VTS May 2005

9 New Test Methodologies Separate PHY test from Functional test Test in context of poor DUT/ATE transmission PHY test Short deterministic loops Optimization of partitioning of ATE / DFT High level of technology in fixture design 9 VTS May 2005

10 New ATE Requirements ATE receivers Means to recover clock Should be able to enable / disable Tolerate small eye openings Receiver eye measurement Jitter Waveform analysis ATE transmitters Jitter injection means Pre-emphasis capability 10 VTS May 2005

11 ATE Accuracy Spec Must Change Edge Placement Accuracy no longer sufficient Lane to lane skew only Requirements much less demanding w/ HS IO Need more detail on single channel spec Jitter Rj TG linearity / resolution+ intrinsic jitter Dj Driver / interconnect / path performance Tester Receiver jitter tolerance Comparator bandwidth Receiver Dj Differential EPA Positive vs negative leg error 11 VTS May 2005

12 High speed serial IO functional test Clock data recovery (CDR) Symbol alignment Link training Non-deterministic behavior Asynchronous clock domains Causes slippages of a few UI Disparity Skip ordered sets (PCI express) 12 VTS May 2005

13 High Speed Serial I/O Functional Test Is real time compare still viable Capture / process may be more viable Disparity Lane symbol alignment Tolerate non-deterministic events Do NOT try to mimic the protocol Results may not be repeatable Confound the failure modes Forces protocol specific instrumentation ($ $ $) Requires very high density design to minimize latency 13 VTS May 2005

14 The HS IO Test Paradigm Change PHY test will require new test partitioning ATE and DFT New performance specification More support from ATE supplier on fixture design Functional test of non-deterministic patterns Capture analyze vs real time compare 14 VTS May 2005

15 High-speed I/O test: The ATE paradigm must change 2005 VLSI Test Symposium Session 4C Burnie West May 2005

16 Outline The brave new world Test methodology PHY testing Functional testing ATE specifications 2 VTS May 2005

17 Where we are going ITRS prediction source ITRS 2004 today frequency(ghz) data rate (Gbps) lithography node 250 embedded clock HSIO source-sync HSIO 90 bus clock OTA YEAR OTA - picoseconds 3 VTS May 2005

18 Evolving ATE Requirements Stimulus Variation to validate DUT receiver performance HSIO Input Datasets Start Input Formatting Subsystem D U T Bit Sync Bit Stream ATE Pattern Partitioning Manager Subsystem P / F ATE Sea of Memory Analytical qualification of DUT transmission performance Functional test datasets Captured DUT Data Structural test datasets 4 VTS May 2005

19 100 Years of Moore s Law 5 VTS May 2005

20 Test methodology Traditional methods I/O parameters Setup time / Hold time / Transition time Functional test Stored response Synchronous clock domains High speed serial PHY parameters Clock recovery / Jitter / Bit Error rates Functional test Non-deterministic behavior Asynchronous clock domains 6 VTS May 2005

21 PHY Test issues Rx Data Reg CDR DUT Rx Tx CDR intrinsic jitter (Rj) CDR output vs data center CDR tracking vs Freq ( filter BW) Dj Equalizer testing PLL Data Serializer DUT Tx PLL jitter (Rj) Output stage Bandwidth (Dj) Pre / De emphasis 7 VTS May 2005

22 DUT / ATE Interconnect Path bandwidth 3X carrier freq ATE to fixture to DUT Issues Transmission lines Material Vias Trace density Test socket 8 VTS May 2005

23 New Test Methodologies Separate PHY test from Functional test Test in context of poor DUT/ATE transmission PHY test Short deterministic loops Optimization of partitioning of ATE / DFT High level of technology in fixture design 9 VTS May 2005

24 New ATE Requirements ATE receivers Means to recover clock Should be able to enable / disable Tolerate small eye openings Receiver eye measurement Jitter Waveform analysis ATE transmitters Jitter injection means Pre-emphasis capability 10 VTS May 2005

25 ATE Accuracy Spec Must Change Edge Placement Accuracy no longer sufficient Lane to lane skew only Requirements much less demanding w/ HS IO Need more detail on single channel spec Jitter Rj TG linearity / resolution+ intrinsic jitter Dj Driver / interconnect / path performance Tester Receiver jitter tolerance Comparator bandwidth Receiver Dj Differential EPA Positive vs negative leg error 11 VTS May 2005

26 High speed serial IO functional test Clock data recovery (CDR) Symbol alignment Link training Non-deterministic behavior Asynchronous clock domains Causes slippages of a few UI Disparity Skip ordered sets (PCI express) 12 VTS May 2005

27 High Speed Serial I/O Functional Test Is real time compare still viable Capture / process may be more viable Disparity Lane symbol alignment Tolerate non-deterministic events Do NOT try to mimic the protocol Results may not be repeatable Confound the failure modes Forces protocol specific instrumentation ($ $ $) Requires very high density design to minimize latency 13 VTS May 2005

28 The HS IO Test Paradigm Change PHY test will require new test partitioning ATE and DFT New performance specification More support from ATE supplier on fixture design Functional test of non-deterministic patterns Capture analyze vs real time compare 14 VTS May 2005