Interfacing DSPs and Microprocessors with High Performance Analog Converters

Transcription

1 Interfacing DSPs and Microprocessors with High Performance Analog Converters INTRODUCTION Jim Ryan Analog Devices BV Raheen Industrial Estate Limerick Ireland From the earliest days of digital computing, engineers and scientists have attempted to process real-world analog signals representing such phenomena as temperature, pressure, strain etc. Previously, electronic measurement and control of such phenomena was implemented using electronic analogs whereby the physical phenomenon such as temperature was converted to its electronic analog using a transducer such as a thermocouple or RTD, and processed using analog electronic circuitry [1,2]. Figure 1a shows a block diagram of a typical analog processing system where both input and output signals receive some pre- and post-processing respectively. The signal processing block implements some form of transformation of the conditioned input signal to produce a suitable output signal. In order for this measurement and control to be implemented using digital computers, it was necessary to convert the electronic analog representation into a quantised, digitised equivalent. [3] Figure 1b shows the block diagram representation of a sampled data equivalent of the analog system in Figure 1a. The analog signal processing block has now been replaced by a digital computer. In modern terms this can represent a microprocessor, microcontroller or Digital Signal Processor (DSP). As the processing is now implemented in the digital or sampled data domain, circuitry is required to transform (convert) between the continuous time representation of the analog signal and the sampled and digitised representation that the computer can understand. This requirement gave birth to the first Analog to Digital and Digital to Analog converters ( and respectively) which like the computers that they interfaced to, were very large, power hungry modules. Modern microcomputers and converters have evolved to offer high performance and high speed at much lower cost in smaller packages requiring less power. This ever increasing speed, in both microcomputers and converters, has allowed the digital processing of signals of ever increasing bandwidth such as in digital radio; while increased converter performance has allowed more accuracy in applications such as industrial controls. As Digital Signal Processing becomes more commonplace in application areas as diverse as high volume consumer applications on one hand to high specification military applications on the other, designers of electronic equipment must acquire new skills in the

2 area of DSP software and hardware development. On one level DSP hardware design is mainly digital but in many applications there comes the inevitable and sometimes unenviable task of designing an analog interface (or analog front end - AFE) and making it work to desired specification in the presence of high speed digital activity. This paper focuses on the task of interfacing DSP engines with the converters used for analog interfacing. It will examine some of the options that designers have in terms of choosing their interface method and discuss the software and performance implications of their choice. ANALOG SIGNAL PROCESSING PROCESSOR SECTION (DSP, MICROCONTROLLER OR MICROPROCESSOR) ANALOG SIGNAL CONDITIONING (INPUT SECTION) ANALOG SIGNAL CONDITIONING (OUTPUT SECTION) DATA ACQUISITION SYSTEM (INPUT SECTION) DATA ACQUISITION SYSTEM (OUTPUT SECTION) a Figure 1. Input Output Systems using (a) Analog Processing and (b) Digital Processing Sampling and Conversion [4] An important point to note in any digital signal processing system is that the process of sampling does not necessarily mean conversion. Signal processing theory requires that the sampling rate of the input or output signals must be at least twice that of the highest frequency of interest in order to meet the Nyquist criterion. Sampling itself is an instantaneous process which in most converters involves an analog sampling circuit acquiring the level of the required signal at the sampling instance. In s, this sampled analog signal is now applied to the converter where it is digitised and quantised. Thus the digital representation will not be available until some finite time (t CONV ) after the sampling instance (see Figure 2). In s, the new analog output is generated from the digital representation at the sampling instance hence the implication is that the new conversion data must be available in the s internal register before the sampling instance. The choice of converter type will determine how sampling should be arranged in a mixed-signal system. Many modern converters based on sigma-delta techniques (highly oversampled) [5] are self timed and determine their own sample or update rate - the sample rate is many times the update due to the high over sampling ratio (OSR) that is used in such converters. These devices will typically operate as master-mode devices in that they will prompt the processor to accept results by requesting service by means of a hardware interrupt line or else they will simply transmit results when they are ready. If a conventional, non-sigma-delta converter is used, then the designer must decide whether sampling and conversion is determined by means of a periodic hardware timer or an internal hardware timer within the processor which triggers a software interrupt. Even though most modern DSPs operate at instruction speeds in the 10s to 100s of MHz, there will be a certain latency associated with servicing an interrupt generated by a timer s timeout condition as many processors feature programmable timers as one of their peripherals. In real-time systems where, perhaps, other higher priority interrupts may occur, there may be an appreciable delay between the timeout event and its associated interrupt service routine (ISR) being executed. If this is a concern then it may be more appropriate to use an external timer to generate periodic sampling pulses. This at least ensures that conversions are taken at the correct time instances regardless of whether software latencies cause delays in the reading or b

3 writing of the conversion data. In the case of lower sampling rates (audioband and below) it may be acceptable to have some uncertainty or jitter by using a sampling trigger that is initiated by an ISR. PERIOD = 1/F S AND READ LOAD AND t CONV Figure 2. Sampling Interval INTERFACING CONVERTERS TO DSPS AND HOST PROCESSORS [6]. Digital Signal Processors (DSPs) take many forms nowadays. The traditional view of a DSP is the typical off-the-shelf offering from the major vendors such as Texas Instruments, Analog Devices, Motorola, Lucent and others. However there are many other processor types which offer embedded (non-programmable) DSP functions and those such as RISC engines which offer very high instruction rates well capable of implementing DSP algorithms. The term DSP engine in this paper will be used in a generic sense and will include other high speed processors such as advanced microcontrollers, microprocessors and RISC based processors. The common aspect of all these processors is that they offer a certain degree of connectivity intended for the connection of peripherals or external memory. These interfaces take two distinct forms - fully parallel data interfaces which allow transfer of a word (equal to the data-bus width) of information per read or write cycle; and serial interfaces where information is transferred in a bit-wise sequential manner. All modern DSPs, fixed-point and floating-point, feature either serial interface or parallel memory interface unless it is a device designed for an embedded application which requires no external hardware support. The parallel data-bus will be equivalent in width to the internal word-size of the DSP, which is typically 16-bits for most fixed-point processors but can be 24-bits in some DSP families used in audio processing applications. In the case of floating point processors the data-bus width will be 32-bits or greater. Serial interfaces on the other hand offer full duplex synchronous operation where input and output data is handled in a bit-wise serial fashion. The maximum number of bits per transfer is typically equal to the internal data-bus width of the processor but is usually programmable to allow interface to a variety of different peripherals. Converters can be seen in a general sense to be peripherals of the DSP processor, either memory-mapped or connected to specific hardware ports. Choosing the type of Interface At a first glance it may seem like an easy task - deciding on what type of interface to use between the converter and the DSP. As was stated above there are two basic interface

4 types available on DSP engines - serial and parallel - which is also generally the case in terms of converter interfaces. Practically all DSPs offer serial interfaces, indeed many of the devices aimed at embedded applications may only offer serial interfaces as the device cost is reduced by eliminating the pin-count of costly external data and address buses. However having chosen the basic type of interface to be used, the next step may not be as easy. Variations on the basic theme proliferate in both categories but especially so in the case of serial interfaces where there exists a myriad of open and proprietary standards. Parallel Interfacing Converters were originally conceived with interfaces that allowed them to be configured in the memory maps of early computers. Thus the converter appears as a single or series of addresses in the processor s memory map allowing the conversion data to be transferred by reading (from an ) or writing (to a ) in one cycle. The transfer is very fast and can be regarded as a simple memory access cycle. High speed DSPs operating at instruction rates of up to 100 MIPs and more have very short memory access cycle times, therefore to successfully interface to converters it is often necessary to program the DSP to insert wait-states in the access cycle time for converters. In many DSPs this feature is programmable and can be programmed individually for different ranges of the external memory map. Another technique is to use a memory acknowledge signal which tells the processor when the data is ready to be read or written. DIGITAL SIGNAL PROCESSOR A13 A0 IOMS RD WR ADDRESS DECODE LOGIC IOMS WR RD RD WR CS D15 DB11 D0 IRQ0 DB0 EOC CONVST IRQ1 WR CS TIMER RD WR DB13 DB0 CONVST CS L Figure 3. Example of Parallel Interface Some DSPs offer a separate external mapping (or I/O space) for converters and other non-memory peripherals such as UARTs etc. Figure 3 shows converters connected to the data-bus of a fixed-point DSP. In this case the I/O addressing space is used and it has a relatively large addressing space which may (or may not) need to be decoded in order to

5 select the converter. This figure highlights some of the disadvantages of parallel interfacing as it is obvious that there is a high pin-count requirement on both the DSP and the converter to support the interface. The converter needs pins for each of the data bits of the conversion as well as pins for chip select (CS\), read (RD\) or write (WR\). Higher pin counts associated with parallel interfaces will often result in higher die and package costs over versions with serial interfaces. Converters designed with parallel interfaces have two subsections which need interfacing to the DSP; the data-pins and the control block. If the resolution of the converter equals the data resolution of the DSP (its data-bus-width) then a simple connection of corresponding bit positions on each bus is sufficient. However if the converter resolution is lower than that of the DSP s data-bus-width then the converter s coding scheme (binary, two s complement etc.) will determine how the buses are connected. In the case of binary coding, right justification of the data buses is required while in the case of two s complement coding, left justification of the buses is required to preserve the correct representation when data is transferred from DSP to converter for output or vice versa for input. (See Figure 4). DIGITAL D15 SIGNAL D4 PROCESSOR D0 DB11 DB0 DIGITAL D15 D11 SIGNAL PROCESSOR D0 DB11 DB0 Figure 4: Left Justification (left), Right Justification (right) To illustrate converter to DSP connectivity, Figure 3 shows an interface from both a 12-bit and 14-bit to a DSP featuring a peripheral addressing space or I/O port space separate from its external memory space. Both converters use two s complement coding therefore the data-bus connections must be left justified. This results in the s data bus (12 bits) being connected to the DSP s data-bus with DB11 (msb) connected to D15 down to DB0 being connected to D4. On the, DB13 is connected to D15 down to DB0 connected to D2. The converters feature standard control pins for accessing the devices for read or write. As many converters now feature programmable features such as programmable input or output gains, power-down features, auto-calibration features etc., there may be a need to provide both read and write access to these devices. DSPs feature separate read (RD\) or write (WR\) pins which can be connected to the corresponding pins on the converters. If the converter features a set of programmable registers then there will be one or more select (or address) lines which will need to be connected to the DSP address bus or some decoding logic depending on what other peripherals share the I/O port space. The timer must provide a direct hardware interrupt output signal that can be used to initiate a conversion via the CONVST\ pin of the or the L\ pin of a. In the case of s, once the sampling and conversion are complete following the timer interrupt which starts conversion, an end of conversion (EOC) flag may be set. The EOC\ will occur a time (t CONV ) after the CONVST\. The EOC\ can be used as an interrupt to the DSP to indicate that a new sample is ready to be read from the. The situation with s is slightly different as the sampling interval timer interrupt

6 represents the instance when the new digital conversion data will be converted to its analog representation. Therefore it is necessary for the DSP to have loaded the s input register with the new data before L\ is active. Assuming that the output is the result of processing previous inputs (and outputs) it is necessary that the DSP algorithm complete its processing and send the new output value to the before the next sampling instance. The main advantage of parallel interfacing is that it supports faster transfer rates and at high conversion rates (> 1 Msps) it becomes a necessity as the serial bandwidth becomes too slow to support the required data rate [7,9]. From a programming point of view it is easier to manage as it becomes a simple read or write to a memory or I/O space address location. Even when used with high level languages such as C, it is possible to declare variables in the memory space (or I/O space using special constructs) that allow easy access to the converter. Serial Interfacing Serial interfaces date from the era of the first microcontrollers when manufacturers attempted to reduce pin-count by using typically three-wire interfaces to interface the microcontrollers with their peripherals. This approach is very valid especially if the serial transfer rate is well above the required data bandwidth of the converter or peripheral. Thus instead of transferring the entire conversion data in one cycle as in the case of parallel transfer, the data is transferred in a bit-serial fashion where either the most significant bit (msb) of the conversion data or the least significant bit (lsb) are sent first and so on at each serial clock cycle until all N bits of the N bit conversion are transferred. This principle has been extended to the case of DSP interfacing where the serial transfer rates supported can be in the range of tens of MHz. As one of the main advantages of serial interfacing is the reduction in pin count required, it is not surprising that manufacturers have proposed many different serial protocols some of which have become industry standards while others have remained practically proprietary, all of which strive to minimize the required pin-count. Some of the serial protocols that have received industry wide acceptance include the Serial Peripheral Interface (SPI) and Queued SPI (QSPI) both from Motorola and the Inter IC bus (I 2 C) and Inter IC Sound bus (I 2 S) both from Philips. Examples of serial interfaced converters include devices that are conceived for audio or voiceband signal processing applications (see Figure 5a) where the serial interface can easily cope with the signal bandwidths required even though conversion resolution is often 16-bits. The reduction in pin-count over a parallel interface can be significant. Most fixed point processors allow words of length 4 to 16 bits to be transmitted or received serially through their serial ports - therefore for convenience most converters above 8-bits in resolution operate with 16 bit word lengths for data and status transfer between converter and DSP. The serial ports (SPORTs) of most DSPs are designed for full duplex operation and they differ from the typical serial interface of microcontrollers in that they use a frame sync pulse - usually a separate pin (or two for asynchronous full duplex transfers) - to indicate the start of the data frame. The typical serial interfaces of microcontrollers use the SCLK as an indicator of serial data therefore the SCLK is only active when data is valid. The DSP serial interface can operate with a continuous SCLK where the FS pulse indicates the start of data valid. Due to the great flexibility offered by the DSP s SPORT, it is possible to have the converter as a master or slave - the converter can raise the frame sync to initiate transfer (converter is master) or it can be done by the DSP (converter is slave). [8] It is often convenient to have the converter or AFE provide the sample timing as it will provide a periodic sample rate which is essential in digital signal processing. Some processors however do not have the capability of connecting to master mode converters therefore it is necessary

7 to have the processor provide the sample timing through a real time clock providing a hardware interrupt. Serial interfaces for converter products have become increasingly popular with designers as they offer the advantage of reduced pin-count hence smaller and cheaper devices. Yet for many of today s applications the serial interface between standard DSPs and converters offers sufficient bandwidth to cater for high resolution sampling (approx. 16-bits) up to 500 ks/s or greater. The SPORT section of the DSP must cater for the transmission and reception of data hence it will feature two independent sections often with separate serial transfer clocks (SCLK). The transmit (TX) section typically provides its output as the digital data for conversion in s while the receive (RX) section is associated with the serial data resulting from conversions in an. In many applications independent s and s may be used in the system design but in audio and speech processing applications, hardware codecs (Coder/Decoder - featuring an and ) are used to provide input/output channels. In these cases there is usually a need for full-duplex operation in that both and may need to be serviced by the RX and TX sections respectively at the same time. ADSP-2185 DSP TFS DT SCLK DR RFS SDIFS SDI SCLK SDO SDOFS AD73322 AD7887 SCLK D OUT D IN ADSP21xx SCLK DR DT CS RFS FL0 FL1 RESETB SE TFS a Figure 5: Examples of Serial Interfacing The DSP SPORT operates with a continuous serial clock (SCLK) which can be either generated by the DSP as an output or can be accepted as an input from the converter. Given that the SCLK may be constantly active there must be a different mechanism to indicate (or flag) the start of a data transfer sequence. This is achieved by a Frame Synchronisation pulse (Frame Sync - FS) which occurs at a designated interval before the first bit of data to be transferred. The frame sync is typically programmable in that many of its characteristics can be selected to suit the interfacing requirements of the converter. These characteristics include the following: pulse width and polarity, position relative to the first data bit and whether the frame sync is generated internally in the DSP or is an input from the converter. [8] The convention of data transfer has Tx data latched on the rising edge of the SCLK while Rx data is latched on the falling edge of SCLK. When the DSP acts as a master - when it defines the sampling instance or the time when data is to transferred - it initiates the data transfer by asserting the appropriate frame sync. In the case of TX, when a word is transferred to the TX buffer by the DSP firmware, a TX frame sync is generated after which will follow the data bits to be transferred in conjunction with the SCLK. The number of bits per serial transfer is also a programmable feature of the DSP SPORT. In the case of RX, a read request from the RX register will generate a frame sync which will prompt the converter to begin transferring its register contents. When the converter is the master, the DSP SPORT can be programmed to respond to frame sync pulses generated by the converter. In this case the converter can prompt the DSP TX section to send a new sample or to receive the new sample. It is also b

8 possible to have a hybrid setup where the RX section responds to converter generated frame syncs while the TX section generates the frame syncs to send data to the converter s section. As in the case of the parallel interface, periodic sampling can only be tightly controlled using a hardware output from a timer or interval counter as the convert start trigger. The timer output will periodically trigger the converter to initiate conversion. When the conversion is complete, the converter can alert the DSP in a number of ways. It can raise an end of conversion flag (EOC) which can be used as a hardware interrupt to the DSP. The DSP can respond by initiating a serial transfer to read the serial data from the converter. In the second case, on end of conversion, the converter can initiate the serial transfer by raising a frame sync pulse to indicate to the DSP that data is being sent to its Rx section. In this case the DSP is configured as the slave with the converter as master. Another approach, used by the shown in Figure 5b, is to use the SCLK as the sampling clock for successive approximation. The results of the bit trials are output at each successive SCLK cycle. The conversion produces 12-bits which are transferred as the 12 lsbs of a 16-bit serial frame. If the converter uses a two s complement format, the received result will need to be left justified so that the msb of the conversion result is aligned with the msb of the DSP s databus. MISCELLANEOUS ISSUES Once the design engineer has chosen the optimum configuration of DSP and converter(s), they must consider the implications for the system firmware. There are two areas of firmware design that are concerned with the DSP/Converter interface: converter initialisation and servicing. Converter Initialisation involves setting the attributes of the converter control settings to the desired values. This phase of operation is only applicable when converter devices with programmable settings, such as programmable gain amplifiers (PGAs) or variable sample rates are used in the system. Converter Servicing is concerned with readback and loading of conversion samples between DSP firmware and converters. This is typically interrupt driven is most critical systems and the firmware that the system uses to service the loading/unloading of samples and perhaps pre- or post-processing is contained in an Interrupt Service Routine (ISR). Interrupt Service Routines Interrupt Service Routines (ISRs) are normally used in signal processing applications to handle input/output sample activity. Even though the sampling may be periodic, the interrupts generated to handle the readback or loading of samples are asynchronous to the processor. The sampling of the analog signals and the reading and writing of the conversion data will either be controlled from the ISR or will generate an ISR. The complexity of the ISR will depend on how the converter is interface. If for instance the converter was interfaced through an SPI port implemented using I/O pins on the DSP, the firmware would be required to bit-bash the interface and construct the data word to be transferred. Contrast this with a converter interfaced to the serial port of the DSP - it may simply require a single instruction access to a special serial port register. For converters with parallel interfaces reading or writing can simply be an external memory access cycle while in the case of serial interface converters the ISR can initiate the

9 serial transfer or the ISR may be the result of the completion of the serial transfer. The structure of the system software will determine the amount of processing that occurs in the ISR. In some cases where a single set of interrupts occurs, it is possible to do all processing from within the ISR - provided that it has completed before the next sampling instance. This is often the way in which DSPs are used as their main advantage is in the implementation of signal processing algorithms rather than the implementation of supervisory code. Thus the ISR routines may take most of the processing time. In another case, the processing is done from within the main code body and the arrival of new results is signalled by a software flag or semaphore. Referring to Figure 6, an example of ISR activity during a sample interval is shown. At each sampling instance both and are updated. An interrupt is generated some time (typically t CONV ) following the sampling instance. The DSP firmware vectors to the ISR on receipt of the interrupt. Note that the time between interrupt event and start of ISR is not always predictable as the interrupt may be blocked temporarily by some higher priority interrupt in the system. This time is termed interrupt latency. The first action in the ISR will be to read the result. This value may be used within the ISR to calculate an update value for the. Alternatively the ISR could set a flag for the main system firmware to indicate receipt of a new sample. Once the periodic processing has been done a new update value for the is loaded. This value will be updated to the s analog output at the next sampling instance. PERIOD = 1/F S AND READ RESULT PROCESS DATA LOAD VALUE AND INTERRUPT SERVICE ROUTINE (ISR) Figure 6. ISR Activity in Sample Interval Interfacing Multiple Converters In many applications, given the processing power available to modern DSP engines, the design may involve interfacing multiple converters rather than a single converter. The task for the designer is to include the extra converters without adding extensive glue-logic to support them. This is especially critical in portable, embedded systems as extra support logic adds to power consumption, board size and cost. Converters which use parallel interfaces can simply have their data-bus pins connected to the DSP s data-bus, requiring an extra select line from the address decode logic. Typically the conversion start pulse can be connected to the CONVST\ pin of all converters. Also, many of the modern crop of DSPs offer direct memory access (DMA) channels between memory locations. Given that the converters are decoded to the memory space, it

10 may be possible to read/write them without processor intervention using a DMA approach, which generates an interrupt when complete. If the converters use serial interfacing there are two options: hardware multiplex or software controlled cascade. As most DSPs provide one or at most two SPORTS, and one of these may be required for interfacing to the host or supervisory processor, it may be impossible if not impractical to dedicate a separate SPORT interface to each converter connection. The solution is to provide a means of connecting a series of serial devices to the one DSP SPORT. Different converter manufacturers have approached this in different ways but in essence it comes down to a choice between either a Time Division Multiplexed (TDM) approach where each device is active to the SPORT in a particular time slot or a software controlled cascading approach where all devices are daisy chained together and data transfer is simply accomplished by shifting data through the chain followed by a latching signal or else by a serial protocol. PERIOD = 1/F S S AND S READ LOAD RESULTS VALUES PROCESS DATA S AND S INTERRUPT SERVICE ROUTINE (ISR) Figure 7. Multiple ISR Activity in Sample Interval The software implications of handling multiple converters may pose more difficulties than those of the hardware variety. Most DSP algorithms are calculated in the number of MIPs consumed versus the number of MIPs offered by the particular DSP. Having to handle many interrupts each sampling interval may involve wasted DSP instruction cycles as there is a finite overhead in terms of context switching that is unavoidable. The best approach is to design the interfacing in such a manner as to generate a single interrupt per sample interval regardless of the number of input/output channels. Techniques to achieve this include autobuffering to internal DSP memory of samples from serial converters and the DMA technique in the case of memory mapped and parallel interfaced converters. This is highlighted by comparing Figures 7 and 8. Figure 7 shows the ISR handling the interfacing of 4 input and 4 output channels. By contrast, Figure 8 shows that in the case of using a background transfer technique such as autobuffering or DMA, the ISR is involved only in processing the results and not in transferring samples.

11 PERIOD = 1/F S S AND S READ RESULTS IN BACK- GROUND PROCESS DATA INTERRUPT SERVICE ROUTINE (ISR) LOAD VALUES IN BACK- GROUND S AND S Figure 8. Using Autobuffering to reduce ISR Activity in Sample Interval Performance Considerations For certain converters there are certain aspects of the interfacing process that can have affects on the analog performance. In ladder s there is the issue of glitch feedthrough when the new conversion data is loaded to the register while in certain s rated performance may not be achieved if data readback (either serial or parallel) is attempted during conversion. Ladder s are configured as binary weighted elements which contribute either current or voltage to a common analog output. Each of the binary weighted elements is controlled by a bit in a digital register where the msb of the register data corresponds with the most significant current or voltage weighting. However as the register is changing the output will correspond directly to any glitches in the register data. Therefore many precision s will offer a double buffered register structure where the DSP will write the first register which is connected to the data-bus. The contents of this register can be transferred separately to the register when the write cycle is over. In this way data-bus glitches during the write process do not cause analog output glitches in the. Some s, such as successive approximation register (SAR) based converters, are susceptible to noise during the conversion process; therefore it is important that readback of results should only occur once the conversion process is over but before the next sampling instance occurs. SUMMARY As more and more designs are being developed using digital signal processing; either software based, using general purpose DSP engines or RISC processors, or hardware based, using dedicated DSP hardware engines; a common requirement is the interfacing of s or s or perhaps combination products incorporating both, to provide conversion between the analog domain of continuous signals and the discrete, quantised representation within the processor.

12 The interfacing styles of s and s are matched to meet those of DSP engines and the two main interfacing styles offer distinct advantages in certain design situations. Parallel devices offer higher speed transfers and ease of interface in memory mapped systems; while serial devices offer lower size, due to lower pin-count, and potentially lower cost and power-consumption which is important in embedded and portable applications. For the designer it is important to review the interface specifications of both intended processor and converter(s) to ensure that correct interfacing can be achieved as problems found at the debug phase may be expensive to correct in terms of lost time and extra component cost. References [1] Transducer Interfacing Handbook; Analog Devices (Dan Sheingold Ed.) 1980; (ISBN: ) [2] Mixed-Signal Design Seminar - Sections 1,2; Analog Devices (Walt Kester Ed.) 1991; (ISBN: ) [3] Analog-Digital Conversion Handbook (3rd Ed); Analog Devices (Dan Sheingold Ed.); Prentice Hall; 1986 (ISBN: ) [4] Mixed-Signal Design Seminar - Section 3; Analog Devices (Walt Kester Ed.) 1991; (ISBN: ) [5] System Applications Guide - Section 14; Analog Devices (Walt Kester Ed.) 1993; (ISBN: ) [6] Mixed-Signal Design Seminar - Section 9; Analog Devices (Walt Kester Ed.) 1991; (ISBN: ) [7] High Speed Design Techniques - Sections 4,5; Analog Devices (Walt Kester Ed.) 1996; (ISBN: ) [8] ADSP-2100 Family User s Manual (3rd Ed) - Chapter 10; Analog Devices, Norwood, MA; Available on CDROM [9] System Applications Guide - Section 13; Analog Devices (Walt Kester Ed.) 1993; (ISBN: )