Digital System Design Lecture 7: Altera FPGAs. Amir Masoud Gharehbaghi
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1 Digital System Design Lecture 7: Altera FPGAs Amir Masoud Gharehbaghi
2 Table of Contents Altera FPGAs FLEX 8000 FLEX 10k APEX 20k Sharif University of Technology 2
3 FLEX 8000 Block Diagram Sharif University of Technology 3
4 FLEX 8000 Specifications Contains Logic Array Block (LAB) Each LAB contains 8 Logic Elements (LE) -> 2,500-16,000 gates. LABs arranged in rows and columns, connected by FastTrack Interconnect, with I/O Elements (IOE) at the edges. 2-level hierarchy (like CPLDs) Lowest level consists of LUTs instead of SPLDs Sharif University of Technology 4
5 FLEX 8000 LAB Each LAB contains: 8 Logic Elements (LEs) Local Interconnects Control signals Carry and cascade chains Local interconnects have input from global interconnects (FastTracks) Sharif University of Technology 5
6 FLEX 8000 Logic Element (LE) LE contains: 4-input LUT, can produce any function of 4 variables Programmable FF, configurable as D, T, JK, SR, or bypass Carry chain Cascade chain Sharif University of Technology 6
7 Carry chain Example (n-bit adder) Provides very fast (< 1 ns) carry forwarding between Les Feeds both LUT and next part of chain Good for: Adders Counters Comparators Sharif University of Technology 7
8 FLEX 8000 Cascade Chain Provides wide fan-in Adjacent LE s LUTs can compute parts of the function in parallel, cascade chain serially connects intermediate values Logical AND or logical OR can be used Each LE provides 4 more inputs, with a delay of about.6 ns Sharif University of Technology 8
9 FastTrack Interconnect The only way of interconnection between LABs All FastTrack wires are identical, so predictable interconnect delays Each LE in a LAB drives 2 columns Each LE in a LAB drives 1 row 3-to-1 muxs connect LE output or column channels to row channels Sharif University of Technology 9
10 FLEX 8000 operational modes Command mode Configuration Load configuration from external memory Initialization Reset registers Enable I/O pins Begin normal operation User mode Normal operation mode Sharif University of Technology 10
11 FLEX 8000 Configuration Takes about 100 ms Active configuration Device controls the entire configuration process Faster Time-to_market Passive configuration Device is incorporated into a system and an intelligent host controls the configuration process Faster prototyping and development Sharif University of Technology 11
12 FLEX 8000 Configuration Schemes Active serial: FLEX gives configuration EPROM clock signals (not addresses), keeps getting new values in sequence. Active parallel up, active parallel down: FLEX gives configuration EPROM sequence of addresses to read data from it. Passive parallel synchronous, passive parallel asynchronous, passive serial: passively receives data from some host. Sharif University of Technology 12
13 FLEX 10k Block Diagram Sharif University of Technology 13
14 FLEX 10k Specifications Contains Logic Array Block (LAB) Each LAB contains 8 Logic Elements (LE) -> 10, ,000 gates. Contains 3-20 Embedded Array Block (EAB), which provides bits of RAM Sharif University of Technology 14
15 FLEX 10k Embedded Array Block EABs can be used to implement logic or memory An EAB provides gate equivalents Very large LUT Faster than general logic Delay is predictable, since not scattered throughout the chip Each EAB can be used independently, or combined to implement larger functions Sharif University of Technology 15
16 FLEX 10k EAB (cont.) Can be used to implement synchronous RAM, ROM, dual-port RAM, or FIFO Each EAB can be configured in the following sizes: 256x8, 512x4, 1024x2, or 2048x1 Combine multiple EABs to get larger blocks: combine two 256x8 RAM blocks to form a 256x16 RAM block combine two 512x4 RAM blocks to form a 512x8 RAM block combine all EABs on the chip into one big RAM block Sharif University of Technology 16
17 Embedded Array Blocks EAB gets input from a row channel, and can output to up to 2 row channels and 2 column channels Input and output buffers are available Sharif University of Technology 17
18 APEX 20k Specifications LABs, each containing 10 LEs- -> 162,000-2,391,552 gates Embedded System Blocks (ESB), each provides 32, ,368 bits of memory Can implement CAM (Content Addressable Memory), RAM, dual-port RAM, ROM, FIFO Sharif University of Technology 18
19 APEX 20k Organization Multicore architecture LUTs Product terms Memory MegaLAB structure 16 LAB and 1 ESB MegaLAB interconnect Sharif University of Technology 19
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