ADVANCED ESD PROTECTION

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92521 Email: aw@ee.ucr.edu Tel: (951) 827-2555 http://www.ee.ucr.edu/~aw Fax: (951) 827-2425 Lab: http://lics.

1 ADVANCED ESD PROTECTION June 8, 21 Prof. Albert Wang Dept. of Electrical Engineering University of California 417 EBU2, Riverside, CA Tel: (951) Fax: (951) Lab: Copyright 29 by Albert Wang, All Rights Reserved

2 Outlines YOU ARE ENJOYING EDS-MEMBER BENEFITS! Basics on ESD Protection Mixed-Mode ESD Simulation-Design Method On-Chip ESD Protection Design Examples Summary 1

3 WHY JOIN? Technical events like this MQ! Global-Networking at home! Stay in touch with state-of-the-art t th t globally, ll Discounts for IEEE conferences and journals, etc. Chapter & local activities, Awards & Recognitions, (Early Career Award, etc.) PhD/MS Student Fellowship Awards, All for $12/$6 EDS Membership Fee! How to join? Ask Prof. J. Burghartz! 2

4 AMultiBillion Multi-Billion-$ Problem! ESD = Electrostatic Discharge Phenomena: huge I/V-pulses IC damages! A multi-billion-$ problem ESD failures 3%-5% IC failures A killing factor to time-to-market Informal ESD Failure Statistics on-chip ESD protection required!electrica... Fab 26% Assembly 14% Good 4%Ion 3% Unknown 15% Ref: L. Brown, et al, Electronic Packaging & Production, April 199. R. Merril, et al, EOS/ESD, ESD/EOS 37% 3

5 Old Devil Re-Appears 4

6 ESD Protection Mechanisms V DD Simple turn-on I-V, Snapback I-V. Protect EVERY I/O pad on chip! IN ND PD SD ND PD OUT PS PS DS NS NS I I 2 nd Breakdown (V t2, I t2 ) (ESD protection region) Low-R discharge (ESD protection region) Low-R discharge V SS Turn on (V t1, I t1, t 1 ) Holding (V h, I h ) Ti Triggeringi (V t1, I t1, t 1 ) V ESD-critical parameters are the KEY to ESD circuit design protection! Ref.: A. Wang, On-Chip ESD Protection for Integrated Circuits, Kluwer, ISBN: , 22. V 5

7 ESD Protection: Simple or Complex?! V DD V DD V SS A R 2 Q 1 I Dz D Z I/O ND V SS PD V SS Q 2 R ext K NS V SS PS V SS Ref: J. Chen, et al, IEEE IEDM Digest, 1995, pp ; Ker, et al, US Patent 5,572,394,

8 Moore s Law~ ESD Protection in CMOS 7 7

9 ESD Challenges for sub-9nm CMOS Reverse trend for <9nm CMOS? Narrower ESD design window? ESD Design Window 1% 1~ I 2% Failure (V t2, I t2 ) VDD V VDDmax V Discharging (R ON ) VSafe BV Holding (V h, I h ) Triggering (V t1,i t1, t 1 ) I DD V Ref.: L. Lin & A. Wang, et al, Proc. EOS/ESD Symp, pp.28-37, 29. 8

10 Emerging Challenges in ESD Design Design prediction by simulation Design optimization i by simulation 3D ESD protection device modeling Whole-chip ESD design theory and methodology CAD algorithm & tools for ESD synthesis and verification ESD protection circuitry for RF/AMS ICs RF-ESD co-design method ESD protection for nano technologies 9

11 Mixed-Mode Mode ESD Simulation-Design 2D/3D Mixed-Mode ESD Simulation-Design Methodology: Electro-thermal-process-device-circuit-layout coupling Static-transient ESD simulation ESD design optimization, no trial-and-error! and no over/under-design! Forward ESD design, not backward analysis! Compact ESD protection designs Minimize ESD-induced parasitic effects Explore novel ESD structures t Ref: A. Wang, et al, IEEE Trans Elec. Devs., v52, n7, p134, 25. H. Feng, et al, IEEE JSSC, v38, n6, p995, 23. H. Xie, MS Thesis, IIT, 24. 1

12 Mixed-Mode Mode ESD Design: Example 1 Chip-level l ESD circuit i design No-assumptions C s V HBM L s ESD source C C circuit (e.g., HBM model) R d C t ESD Circuit Core IC Chip ESD sub-circuit to be simulated 11

6 4.4.E+ 2.E-7 4.E-7 6.E-7 8.E-7 1.E-6 1.

13 m p) C urre nt ( A Example-1: ggnmos ~ gcnmos ESD I( A ) E+ 2.E-7 4.E-7 6.E-7 8.E-7 1.E-6 1.E-6.2 Time (Second) V(v) 15 B S G Hot Spot D V ( V ) E-12 1.E-11 1.E-1 1.E-9 1.E-8 1.E-7 1.E-6 1.E-5 t(s) 12

14 Example-1: ggnmos ~ gcnmos ESD Id ( A ) Vd(V ) V g(v ) E E-12 1.E-1 1.E-8 1.E-6 Vd(V) log(t) (s) 25 2 To reduce triggering V t1 by design Tm ax(k) E-12 1.E-1 1.E-8 1.E-6 1.E-4 1.E-2 log(t) (s) 1.E-12 1.E-1 1.E-8 1.E-6 log(t) (s) 13

15 Example 2: ESD + RF tmaxm1 tmaxm2 tmaxesd RF output buffer block, Differential buffer with open collector, 7 5kV SCR ESD protection Tmax (K) 9 5 Out1 3.E+ 2.E-7 4.E-7 6.E-7 8.E-7 1.E-6 1.E-6 Time (s) In1 Out2 3. I-M1 In2 bias ES SD- S CR ES SD- S CR rent (A) Curr 2. I-ESD 1.. Ref: H. Feng, et al, IEEE JSSC, V38, N6, p995, 23..E+ 2.E-7 4.E-7 6.E-7 8.E-7 1.E-6 Time (s) 14

16 RF ESD Protection Design What s Unique for RF ESD protection?! RF IC is extremely sensitive to ESD-induced parasitics Need accurate RF ESD characterization Low-parasitic compact RF ESD protection design Whole-chip ESD protection circuit design concept New & Critical: ESD-Circuit Interactions ESD-to-Circuit Influences Circuit-to-ESD Influences RF+ESD co-design Ref: A. Wang, et al, invited, IEEE Proc. CICC, 22, pp A. Wang, et al, invited, Proc. IEEE RFIC

17 ESD Parasitics: C ESD Circuit performance may be affected by ESD circuitry: ESD-induced parasitic C ESD (up to ~pf) & R ESD, C ESD R ESD delay signal integrity, clock corruption, C ESD loading effect, Z-matching, power efficiency, i BW, C ESD, R ESD ~ frequency, biasing, temperature, Unique Challenge: Accurate C ESD estimation, Including C ESD in RF IC design, Reduce C ESD over f RF 16

18 ESD Parasitics: Noises Substrate noise coupling effect due to C ESD : Incident noises at I/O coupled into substrate, Substrate noises I/O signal path ESD self-generated noises: Thermal noises, Flicker noises, Shot noises, etc. I/O C ESD Unique Challenge: ESD noises into RF ICs. 17

19 Mixed-Signal ESD Protection No global ESD solutions! No one V t1 fits the whole chip! t1 f Multi-V DD /V SS locally-optimized V t1 for different I/Os, Need a safety margin for V t1 : V t1 of 5V fits V DD =3.3V blocks, V t1 of 23V good for V DD =15V blocks. Challenge 4: multi-v t1 ESD design in RF/AMS ICs whole-chip ESD design optimization, on-chip local ESD design optimization 18

Example-3: ESD-Protected RF IC Design ESD affects

transceiver CE-CB cascode topology High/low gain

18 m SiGe BiCMOS 2KV ESD protection ESD GSG RFIN

20 Example-3: ESD-Protected RF IC Design ESD affects RF IC substantially: 5GHz LNA for dual-band WLAN transceiver CE-CB cascode topology High/low gain switching Unique double shutdown function.18 m SiGe BiCMOS 2KV ESD protection ESD GSG RFIN ESD GSG RF FOUT Ref.: G. Chen, et al, Proc. IEEE EMC,

21 Example-3: LNA Noise ~ ESD LNA circuits S 21 (db) S 11 (db) NF(dB) NF w/o ESD with ESD Degradation 16.73% 17.25% 6.8% NF (db) LNA w/ ESD LNA w/o ESD NF: ESD device F Total F ESD F G LNA ESD NF ESD.1 db Frequency (GHz) 2

22 Example-4: RF ESD Characterization Most commonly ESD protection structures ggmos SCR dscr Diode string: Dx1, Dx2, Dx3, Dx4, Dx5, Dxn Designed and fabricated in.35 m BiCMOS 2kV/5kV ESD protection Design optimization by mixed-mode mode ESD simulation Simulation matches measurement very well 21

23 Example-4: 2kV C ESD by SIM & Test CESD (pf) 1 Simulation.8 SCR ggnmos Dx1.6 Dx2 dscr.4.2 C ESD (pf F).8 SCR ggnmos Dx1.6 Dx2 Dx3 Dx4 Dx5 dscr f (GHz).2 Measurement f (GHz) 22

24 Example-4: 2kV C ESD by Test C ESD (pf) 1.1 SCR Dx1 Dx2 8.8 Dx3 Dx4 Dx5 6.6 dscr f (GHz)

25 Example-4: 2kV C ESD ~ Size 2kV Layout Size Comparison ESD 25 2 ize (um2) Layout S kV C ESD Comparison at 2.4GHz Dx1 Dx2 Dx3.45 Dx4 Dx5 ggnmos SCR dscr ESD Structures ESD (pf) CE Dx1 Dx2 Dx3 Dx4 Dx5 ggnmos SCR dscr ESD Structures 24

26 FoM for Overall ESD Design Evaluation Each parameter has different/conflicting meaning, Optimization by overall ESD design performance, Need a new FoM parameter: F-factor F kv 2 Size ( m ) CESD ( pf ) NF ( db ) 2kV F-Factor Comparison (Measured) 2 15 F-fac ctor 1 5 Dx1 Dx2 Dx3 Dx4 Dx5 ggnmos SCR dscr ESD Structures 25

27 Novel ESD Protection Design Helps V DD V DD IN ND PS PD NS V DD SD DS ND PD PS NS ND/PD OUT NS/PS DS ND/PD DS/SD NS/PS V SS V SS V SS SS SS 26

Example-6: All-Mode SCR ESD Protection P + N - A (ND) C K P + 4 2

A. Wang, et al, IEEE Electron Device Letters, Vol. 22, No. 1, pp.

28 Example-6: All-Mode SCR ESD Protection P + N - A (ND) C K P P + C K N - A (PD) P + PW R w Q 6 3 P-well PW R w Q 5 2 P-well N-Epi Q 41 4 N-Epi 3 Q 41 C A 1 P + K N - A (PS) P + K 1 2 P + N - A (NS) K P + 2 PW R w Q 2 P-well PW R w Q 3 P-well N-Epi Q 1 Ref: A. Wang, et al, IEEE Electron Device Letters, Vol. 22, No. 1, pp , Oct. 21. A. Wang, US Patent # 6,635,931 B1, 23. N-Epi Q 1 27

29 Example-7: Low-Parasitic Poly-Si SCR ESD Cathode Anode Polysilicon S N + P + N + P + (N Not to Scale) N 5 P 4 I 3 N 2 P 1 R 2 Q 1 D Q 2 R 1 Field Oxide P-Substrate Xie, et al, A New Low-Parasitic Polysilicon SCR ESD Protection Structure for RF ICs, IEEE Electron Device Letters, Vol. 26, No.2, pp , February 25 28

30 Example-7: Excellent Prediction 3 35 m.35 m SiGe BiCMOS. 3.2kV HBM ESD protection level using a small 75 m2 poly-si SCR a high F-factor of 42 the lowest reported C ESD of ~92.3fF. Ajustable V t I (Anode) (A A) Simulation TLP Testing I (Anode) (A A) Poly Diode V (Anode) (V) Poly SCR_1 Poly SCR_2 Poly SCR_3 Poly SCR_ V (Anode) (V) 29

31 Summary ESD failure is a killing factor to ICs, On-chip ESD protection ti required for ICs, RF/AMS ESD design is very challenging, ESD design prediction by mixed-mode simulation 3

32 REFERENCES L. Lin, A. Wang, et al, Whole-Chip ESD Protection Design Verification by CAD, Proc. EOS/ESD Symp, pp.28-37, 29 X. Guan, et al, ESD-RFIC Co-Design Methodology, Invited, Proc. IEEE RFIC, pp467-47, 28. A. Wang, et al, A Review on RF ESD Protection Design, IEEE Trans. Electron Devices, V2, N7, p.134, July 25. H. Xie, et al, A New Low-Parasitic Polysilicon SCR ESD Protection Structure for RF ICs, IEEE Electron Device Letters, V26, N2, p.121, February 25. R. Zhan, et al, ESDInspector: A New Layout-level ESD Protection Circuitry Design Verification Tool Using A Smart- Parametric Checking Mechanism, IEEE Trans on CAD of Integrated Circuits and Systems, V23, N1, p.1421, Oct. 24. G. Chen, et al, Characterizing Diodes For RF ESD Protection, IEEE Electron Device Letters, V25, N5, p.323, May 24. A. Wang, On-Chip ESD Protection For Integrated Circuits, Kluwer Academic Publishers, Boston, ISBN: , 22. A. Wang, et al, ESD Protection Design for RF Integrated Circuits: New Challenges, Invited, IEEE CICC, p.411, 22. A. Wang, A Study of Parasitic Effects of ESD Protection on RF ICs, IEEE Trans. Microwave Theory & Tech., V5, N1, p.393, Jan. 22. H. Feng, et al, A Mixed-Mode ESD Protection Circuit Simulation-Design Methodology, IEEE J. Solid-State Circuits, V38, No. 6, p.995, June 23. R. Zhan, et al ESDExtractor: A New Technology-Independent CAD Tool For Arbitrary ESD Protection Device Extraction, IEEE Trans on CAD of Integrated Circuits and Systems, V22, N1, p.1362, October 23. A. Wang, et al, " An on-chip ESD Protection Circuit with Low Trigger-Voltage in BiCMOS Technology", IEEE J. Solid-State Circuits, V36, N1, p.4, January 21. A. Wang, et al, "On a Dual-Direction on-chip Electrostatic Discharge Protection Structure, IEEE Trans. Elec. Devices,, V48, N5, p.978, May 21. R. Zhan, ESDcat: a New CAD Package for Full-Chip ESD Protection Design Verification, PhD Dissertation, IIT, 25. X. Xie, 3D Mixed-Mode Simulation-Design Methodology and Electro-Thermal Modeling for ESD Protection Circuits, MS Thesis, IIT, 24. G. Chen, Design and Characterization of ESD Protection for RFICs, MS Thesis, IIT, 23. H. Feng, A Mixed-Mode Simulation-Design Methodology For On-Chip ESD Protection Design, MS Thesis, IIT, 21. K. Gong, ESD Protection in Copper Interconnect and ESD-to-Circuit Performance Influences, MS Thesis, IIT,

Chapter 2 On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process

Chapter 2 On-Chip Protection Solution for Radio Frequency Integrated Circuits in Standard CMOS Process 2.1 Introduction Standard CMOS technologies have been increasingly used in RF IC applications mainly