Investigation on ESD Robustness of P-type TFTs under Different Layout Structures in LTPS Process for On-Panel ESD Protection Design*
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1 * Investigation on ESD Robustness of P-type TFTs under Different Layout Structures in LTPS Process for On-Panel ESD Protection Design* Authors: Ming-Dou Ker 1, Jie-Yao Chuang 1, Chih-Kang Deng 1, Chun-Huai Li 2, and Chung-Hong Kuo 2 1 National Chiao-Tung University, Hsinchu, Taiwan. mdker@ieee.org 2 AU Optronics Corporation, Science-Based Industrial Park, Hsinchu, Taiwan. IEW 2007 This work was partially supported by the Ministry of Economic Affair, Technology Development Program for Academia, R.O.C, under contract 95-EC-17-A-07-S1-046.
2 Biography of Presenter The Presenter, Ming-Dou Ker, is now a Full Professor in National Chiao-Tung University, Hsinchu, Taiwan. His current research topics include reliability and quality design for nanoelectronics and gigascale systems, highspeed and mixed-voltage I/O interface circuits, and onglass circuits for system-on-panel applications in TFT LCD display. With outstanding achievements in reliability and quality design for circuits and systems, he has been selected as one of the Distinguished Lecturers in IEEE Circuits and Systems Society.
3 Abstract System-on-panel (SOP) application has been a major trend for panel development with Low Temperature Poly- Si (LTPS) TFT devices. When more circuits integrated into display panels, the on-panel ESD protection design should be provided against ESD stress to improve reliability and yield of panel manufacturing and assembly. P-TFTs have been demonstrated to be more cost-effective than the N-TFTs in the LTPS process with less variation on device characteristics. In this work, ESD robustness of P-TFTs with different layout structures are investigated by measuring secondary breakdown current (It2) with Transmission-Line-Pulsing (TLP) system.
4 Purpose of This Work The heat generated by ESD current cannot be dissipated easily on glass substrate, as comparing with Si substrate. cause damage on panel and lower production yield. Ref.: N. T. Golo et al., Zapping thin film transistor, Microelectronics Reliability, vol. 42, pp (2002). To develop a good ESD protection design for LCD panel.
5 Outline Introduction Test structures of on-glass P-TFT devices Configuration of TLP (Transmission Line Pulsing) system for on-panel devices Experimental results On-Panel ESD Protection Design With Power Clamp Conclusions
6 System on Panel in LTPS TFT Process CPU on Glass Substrate 3-MHz Z80 CPU (8 bits) Asynchronous Microprocessor (8 bits) with 80 I/O Pins Ref.: B. Lee et al., A CPU on a glass substrate using CG-silicon TFTs, ISSCC (Sharp) Ref.: N. Karaki et al., A flexible 8b asynchronous microprocessor based on low-temperature poly-silicon TFT technology TFTs, ISSCC (Seiko Epson)
7 ESD Events to On-Panel TFT Circuits 2.2 inch TFT-OLED Panel Shift Register / Switches ESD Protection circuits ESD damages The more TFT circuits integrated on a panel, the more ESD protection should be provided.
8 Design Consideration of On-Panel TFT Circuits in LTPS Technology P-TFTs have been found to be more cost-effective than the N-TFTs in the LTPS process, as well as the variation on device characteristics among N-TFT devices is more serious than that of P-TFT devices. P-TFTs N-TFTs Ref.: Y. H. Tai, Device Variation and Its Influences on the LTPS TFT Circuits, International TFT Conference (2005).
9 Circuits Realized with Only P-TFT Devices Inverter with only P-TFTs Level Shifter with only P-TFTs 0 V 0 V 10 V -20 V 0 V -10 V Ref.: S.-H. Jung et al., A new low power PMOS poly-si inverter and driving circuits for active matrix displays, in SID Tech. Dig., 2003, pp S.-H. Jung et al., A new low-power PMOS poly-si inverter for AMDs, IEEE Electron Device Lett., vol. 25, pp , Jan
10 P-TFT Device Structure in a LTPS Process Split Conditions: (1) Channel length: L = 5 ~ 20 µm (2) Channel width: W = 100 ~ 500 µm (3) Fixed W/L ratio but different device dimensions Drain P+ P+ P+ P+ P+ W fp Gate Gate Gate Gate Source Unit finger Width: W fp Finger number: N fp = 4 (fixed) Total width: W = W fp x N fp
11 Wafer-Level TLP System with Different Current Pulse Widths (100ns, 500ns, 1000ns)
12 P-TFT under TLP Stress With 100-ns Current Pulse Fresh W/L = 500µm/20µm Short 1V/Div. and 0.1A/Div. TLP_V TLP_I 20ns/Div. 8V/Div. and 0.1A/Div. 100 ns 100 ns TLP_V 20ns/Div. TLP_I
13 P-TFT under TLP Stress With 500-ns Current Pulse Fresh Short W/L = 500µm/20µm 1V/Div. and 0.1A/Div. 500 ns TLP_V TLP_I 100ns/Div. 8V/Div. and 0.1A/Div. TLP_V 500 ns 100ns/Div. TLP_I
14 P-TFT under TLP Stress With 1000-ns Current Pulse Fresh Short W/L = 500µm/20µm 2V/Div. and 0.1A/Div. TLP_V TLP_I 200ns/Div. 10V/Div. and 0.2A/Div ns 1000 ns TLP_V 200ns/Div. TLP_I
15 P-TFT under forward TLP Stress with Different Current Pulse Widths
16 TLP I-V Curve of LTPS TFT Device under Forward and Reverse Stresses The It2 of LTPS P-TFT device under forward TLP stress is much better than that under reverse TLP stress. (100-ns TLP) TLP t TLP t I TLP I TLP Forward Stress Reverse Stress
17 Dependence of It2 on P-TFT Channel Width (100-ns TLP) Increasing channel width, the diode-connected P-TFT can sustain higher It2 current under forward TLP stresses. The It2 of diode-connected P-TFT is increased from 0.06 A to 0.26 A, when the channel width is increased from 100 µm to 500 µm.
18 Dependence of It2 on P-TFT Channel Width The fresh leakage current and the turn-on conductance of diode-connected P-TFT are increased with the increase of channel width. (100-ns TLP) (100-ns TLP)
19 Dependence of It2 on P-TFT Channel Length Enlarging the channel length of P-TFTs (under the same channel width) will decrease its It2. The estimated HBM ESD level of diode-connected P-TFT with W/L = 500μm/5μm is only ~ 0.45 kv. (100-ns TLP) (100-ns TLP)
20 Dependence of It2 on P-TFT Device Dimension under fixed W/L Ratio (W/L=100) P-TFT drawn with a larger device size has the more area for heat dissipation to sustain a higher It2 level. The estimated HBM ESD level of diode-connected P-TFT with W/L = 1500μm/15μm is about ~1.3 kv. (100-ns TLP) (100-ns TLP)
21 On-Panel ESD Protection Design with Power Clamp in a LTPS Process with P-TFTs I/O Pad I/O Pad V DD I/O Pad Power Clamp R C I/O Pad Location D = 100µm Metal Line Width = 20, 50, or 100 µm I/O Pad Location.. I/O Pad Location Power Clamp C R PMOS
22 Conclusions 1. TFT device under forward-stress condition can sustain much higher It2 current than that under reverse-stress condition. 2. Enlarging the channel width of P-TFTs can improve It2 level, but accompanies the increased fresh leakage current. 3. Increasing the channel length under the same channel width, the turn-on conductance of the diode-connected P-TFT are decreased to cause a lower It2 level. 4. The diode-connected P-TFT drawn in the same W/L ratio with the increased device size can greatly improve It2 level, due to the larger area for heat dissipation. 5. On-Panel ESD protection design with active power-rail ESD clamp circuit should be added on the panel to operate P-TFT devices under forward-stress condition and therefore to achieve higher ESD robustness for System-on-Panel applications.
23 References [1] S. H. Yeh et al., A 2.2-inch QVGA system-on-glass LCD using p-type low temperature poly-silicon thin film transistors, in SID Tech. Dig., pp (2005). [2] F. R. Libsch et al., ESD: how much protection is need for AMLCDs, in SID Tech. Dig., pp (1994). [3] S.-C. Lee et al., Electrostatic discharge effects on poly-silicon TFTs for AMLCD, in SID Tech. Dig., pp (2002). [4] Y. M. Ha, P-type technology for large size low temperature poly-si TFT- LCDs, in SID Tech. Dig., pp (2000). [5] S. C. Huang et al., Statistical investigation on the variation behavior of low-temperature poly-si TFTs for circuit simulation, in SID Tech. Dig., pp (2006). [6] M.-D. Ker et al., Successful electrostatic discharge protection design for LTPS circuits integrated on panel, in SID Tech. Dig., pp (2003). [7] Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), EIA/JEDEC Standard EIA/JESD22-A114-A (1997).
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CDDFN P - Surface Mount TVS Diode Array
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AQ1026 Series 15pF 30kV Bidirectional Discrete TVS
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AQ24CANFD 200W TVS Diode Array
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INPAQ Global RF/Component Solutions
TVL 0402 01 AB1 Specification Product Name Series Part No Transient Voltage Suppressor TVS Series TVL 0402 01 AB1 Size EIA 0402 TVL 0402 01 AB1 Engineering Specification 1. Scope TVL 0402 01 AB1 is a TVS
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TVS Diode Arrays (SPA Diodes)
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Alfa-MOS Technology. AFE0563 One-Line ESD Protection Low Capacitance Bi-direction TVS. General Description. Pin Description ( DFN )
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PESDR0554S2. 4-Line Low Capacitance TVS Diode Array. Mechanical Characteristics. Description. Applications. Features. Ordering Information
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SP pF 8kV DFN Plastic Unidirectional Discrete TVS
SP1053 8.5pF 8kV 01005 DFN Plastic Unidirectional Discrete TVS RoHS Pb GREEN Description Avalanche breakdown diodes fabricated in a proprietary silicon avalanche technology protect each I/O pin to provide
ESD9X5VL ESD9X5VL. X x. Transient Voltage Suppressor
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CDDFN P - Surface Mount TVS Diode Array
Features n RoHS compliant* n Low capacitance -.4 pf (I/O to I/O) n ESD protection to IEC 61-4-2 (Level 4) Applications n HDMI 1.3, 1.4 and 2. n DisplayPort n Digital Visual Interface (DVI) n SATA and esata
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