An overview of Interrupts ECE3534

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Lynette Carroll
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1 An overview of errupts ECE3534

2 Microprocessor erfacing: errupts Suppose a peripheral intermittently receives data, which must be serviced by the processor The processor can poll the peripheral regularly to see if data has arrived wasteful The peripheral can interrupt the processor when it has data Requires an extra pin or pins: If is 1, processor suspends current program, jumps to an errupt Service Routine, or Known as interrupt-driven I/O Essentially, polling of the interrupt pin is built-into the hardware, so no extra time! 2

3 Microprocessor erfacing: errupts What is the address (interrupt address vector) of the? Fixed interrupt Address built into microprocessor, cannot be changed Either stored at address or a jump to actual stored if not enough bytes available Vectored interrupt Peripheral must provide the address Common when microprocessor has multiple peripherals connected by a system bus Compromise: interrupt address table : errupt Service Routine 3

4 errupt-driven I/O Using Fixed Location PROCESSOR PERIPHERAL Time 1(a): is executing its main program. 1(b): receives input data in a register with address. 3: After completing at 100, sees asserted, saves the s value of 100, and sets to the fixed location of 16. 2: asserts to request servicing by the microprocessor. 4(a): The reads data from, modifies the data, and writes the resulting data to. 4(b): After being read, deasserts. 5: The returns, thus restoring to 100+1=101, where resumes executing. 4

5 errupt-driven I/O Using Fixed Location 1(a): µp is executing its main program 1(b): receives input data in a register with address. 18: MOV, R0 100: 101: 5

6 errupt-driven I/O Using Fixed Location 2: asserts to request servicing by the microprocessor 18: MOV, R0 100: 1 101: 6

7 errupt-driven I/O Using Fixed Location 3: After completing at 100, µp sees asserted, saves the s value of 100, and sets to the fixed location of : MOV, R0 100: 101: 100 7

8 errupt-driven I/O Using Fixed Location 4(a): The reads data from, modifies the data, and writes the resulting data to. 4(b): After being read, deasserts. 18: MOV, R0 100: 101:

9 errupt-driven I/O Using Fixed Location 5: The returns, thus restoring to 100+1=101, where µp resumes executing. 18: MOV, R0 100: 101:

10 errupt-driven I/O Using Vectored errupt Time 1(a): is executing its main program. 1(b): receives input data in a register with address. 3: After completing at 100, sees asserted, saves the s value of 100, and asserts a. 2: asserts to request servicing by the microprocessor. 4: detects a and puts interrupt address vector 16 on the data bus. 5(a): jumps to the address on the bus (16). The there reads data from, modifies the data, and writes the resulting data to. 5(b): After being read, deasserts. 6: The returns, thus restoring to 100+1=101, where resumes executing. 10

11 errupt-driven I/O Using Vectored errupt 1(a): P is executing its main program 1(b): receives input data in a register with address. 18: MOV, R0 100: 101: 100 a 16 11

12 errupt-driven I/O Using Vectored errupt 2: asserts to request servicing by the microprocessor 18: MOV, R0 100: 101: 100 a

13 errupt-driven I/O Using Vectored errupt 3: After completing at 100, sees asserted, saves the s value of 100, and asserts a 18: MOV, R0 100: 101: 100 a

14 errupt-driven I/O Using Vectored errupt 4: detects a and puts interrupt address vector 16 on the data bus 16 18: MOV, R0 100: 101: 100 a 16 14

15 errupt-driven I/O Using Vectored errupt 5(a): jumps to the address on the bus (16). The there reads data from, modifies the data, and writes the resulting data to. 5(b): After being read, deasserts. 18: MOV, R0 100: 101: 100 a

16 errupt-driven I/O Using Vectored errupt 6: The returns, thus restoring the to 100+1=101, where the resumes 18: MOV, R0 100: 101:

17 errupt Address Table Compromise between fixed and vectored interrupts One interrupt pin Table in memory holding addresses (maybe 256 words) Peripheral doesn t provide address, but rather index into table Fewer bits are sent by the peripheral Can move location without changing peripheral 17

18 errupts on the MicroBlaze Supports one external interrupt source (connecting to the errupt input port). Will only react to interrupts if the errupt Enable (IE) bit in the Machine Status Register (MSR) = 1. On an interrupt the in the execution stage will complete, while the in the decode stage is replaced by a branch to the interrupt vector (address 0x10). The interrupt return address (the associated with the in the decode stage at the time of the interrupt) is jammed into R14. The processor also disables future interrupts by clearing the IE bit in the MSR. The IE bit is automatically set again when executing the RTID.

19 errupt Latencies DEFINITION: How fast the processor is able to respond when an interrupt condition occurs.

20 Additional errupt Issues Maskable vs. non-maskable interrupts Maskable: programmer can set bit that causes processor to ignore interrupt Important when in the middle of time-critical code Non-maskable: a separate interrupt pin that can t be masked Typically reserved for drastic situations, like power failure requiring immediate backup of data to non-volatile memory must not modify registers, or else must save them first Assembly-language programmer must be aware of which registers stored 20

21 Review errupts vs. Polling errupt-driven I/O Fixed errupt Vectored errupt errupt Table errupts on MicroBlaze

ECE332, Week 8. Topics. October 15, Exceptions. Hardware Interrupts Software exceptions

ECE332, Week 8. Topics. October 15, Exceptions. Hardware Interrupts Software exceptions ECE332, Week 8 October 15, 2007 1 Topics Exceptions Hardware Interrupts Software exceptions Unimplemented instructions Software traps Other exceptions 2 1 Exception An exception is a transfer of control