Summer 2003 Lecture 11 06/25/03

Size: px
Start display at page:

Download "Summer 2003 Lecture 11 06/25/03"

Transcription

1 Summer 2003 Lecture 11 06/25/03 Maskable Hardware Interrupt Process Sequence 1) CPU samples level of interrupt pin at end of last cycle of previous instruction. 2) If the interrupt pin is high, rather than perform the next instruction fetch cycle, the CPU will begin an interrupt acknowledge cycle. 3) The INTA pin is brought low during two successive bus cycles. During the second INTA cycle, the interrupt number will be sampled on the system data bus. 4) The CPU will save the current FLAGS, CS and IP on the stack. 5) The interrupt flag in the FLAGS register is cleared. 6) The interrupt vector address will be computed from the interrupt number, and the corresponding vector will be fetched from the interrupt vector table. 7) The interrupt vector will be loaded into CS and IP. 8) The CPU will start executing the next instruction at the beginning of the interrupt service routine. Implementing Standard C Control Structures: IF THEN ELSE The IF-THEN control construct is the most basic form of decision making structure in programming. The specified condition is tested and if it is true, the associated block of code is executed. If the condition is not true, execution continues: if (condition) { true case code This is implemented in assembler using some instruction that sets the flags, usually CMP, AND, OR, or XOR. If the flag is set indicating that the condition is not true, a conditional jump will jump around the IF code. The only thing tricky about this is to make sure that you have correctly implemented the test for not condition, so that the jump around the if clause code occurs when it is supposed to. if (a == b) { mov ax,a blah; jnz endif

2 blah The IF-THEN can be combined with an ELSE clause, giving an IF-THEN- ELSE construct. If the specified condition is true, the if clause code is executed, otherwise the else clause code is executed. Again, this can be implemented as a test followed by a conditional jump. This can be done one of two ways. 1. If the condition is true, jump to the if block, otherwise fall through to the else code. This is the more natural way to write it, but the if and else blocks end up being in the opposite order from how they would appear in C. 2. If the condition is not true, jump to the else block, otherwise, fall through to the if block. This puts the if and else clauses in the more natural order. However, as with the IF-THEN above, it requires correctly implementing the test for not condition for the jump to the else clause.

3 In each case, following the end of the first clause, a jump is made to the end of the IF construct. if (a == b) { true clause else { false clause mov ax,a mov ax,a jz doif jnz doelse doelse: doif: false clause true clause jmp endif jmp endif doif: doelse: true clause false clause The most complete form of the IF control construct adds additional ELSE IF tests to add more possible choices. In this case, the first IF condition is evaluated. If the test is true, the code associated with the IF clause is executed. If it is not true, the first ELSE IF condition is evaluated. If true, the associated block of code is executed, if not the next ELSE IF condition is tested, and so on. If no ELSE IF conditions are true, then the final ELSE clause code is executed. This is best implemented using the second form as shown above. Test the first condition, if true, fall through to the associated block of code, if not true, jump to the test of the second condition, and so on, so that if the final test if false, a jump is taken to the else clause code. After each of the IF or ELSE IF clauses has executed, a jump is made to the ENDIF. if (a == b) { mov ax,a first clause jnz test2 else if (a == c) { second clause first clause else if (a == d) { jmp endif third clause test2: cmp ax,c

4 jnz test3 else { final clause second clause jmp endif test3: cmp ax,d jnz doelse third clause jmp endif doelse: final clause WHILE The C WHILE loop tests a condition at the beginning of the loop. If the test is satisfied, the body of the loop is executed and the test is performed again. The body of the loop will be executed as long as the test is satisfied. Because the test is made at the top of the loop, the will not be executed at all if the test is not satisfied the first time. This is most naturally implemented in assembler using a similar test to that of the IF THEN, followed by a jump around the body of the loop if the condition is false. Following the is a jump back to the top of the loop and the test. while (a == b) { ltop: mov ax,a jnz lend jmp ltop lend: DO WHILE The DO-WHILE loop in C is similar to the WHILE loop, except that the test is made at the end of the loop instead of the beginning. The will execute at least once.

5 When implementing this in assembler, it is most natural to use a test of the loop condition at the bottom of the loop, and if the condition is satisfied to jump back to the top of the loop. do { ltop: while (a == b); mov ax,a jz ltop

6 FOR LOOP The FOR loop in C uses an initialization expression, a test expression, and a reinitialization expression. The initialization expression is performed once at the beginning of the construct. The test expression tests a condition, and if the test is satisfied, the body of the loop will be executed. Following the body of the loop, the reinitialization expression will be executed and then the test expression is again executed. The test is at the beginning of the loop, and so the will not be executed at all if the test fails the first time. The general syntax for a C FOR loop is as follows: for (<init expr>; <test expr>; <reinit expr>) { This is semantically equivalent to the following C constructs: init expr; while (test expr) { reinit expr;

7 The implementation of this in assembler follows directly from the above description for the implementation of the WHILE loop. for (inx = 0; inx < 10; inx++) {movinx,0 ltop: mov ax,inx cmp ax,10 jae lend add inx,1 jmp ltop lend:

Summer 2003 Lecture 12 06/26/03

Summer 2003 Lecture 12 06/26/03 Summer 2003 Lecture 12 06/26/03 Implementing Standard C Control Structures: IF THEN ELSE if (a == b) { mov ax,a blah; cmp ax,b jnz endif blah endif: if (a == b) { true clause else { false clause mov ax,a

More information

LAB 3: Programming in Assembly Language

LAB 3: Programming in Assembly Language INTERNATIONAL ISLAMIC UNIVERSITY OF MALAYSIA Kulliyyah Of Engineering Department Of Electrical Engineering ELECTRICAL AND COMPUTER ENGINEERING LAB II (ECE 2202) Name: Matric Number: Group: Section: Date:

More information

Lecture 8: Control Structures. Comparing Values. Flags Set by CMP. Example. What can we compare? CMP Examples

Lecture 8: Control Structures. Comparing Values. Flags Set by CMP. Example. What can we compare? CMP Examples Lecture 8: Control Structures CMP Instruction Conditional High Level Logic Structures Comparing Values The CMP instruction performs a comparison between two numbers using an implied subtraction. This means

More information

Introduction to 8086 Assembly

Introduction to 8086 Assembly Introduction to 8086 Assembly Lecture 5 Jump, Conditional Jump, Looping, Compare instructions Labels and jumping (the jmp instruction) mov eax, 1 add eax, eax jmp label1 xor eax, eax label1: sub eax, 303

More information

PC Interrupt Structure and 8259 DMA Controllers

PC Interrupt Structure and 8259 DMA Controllers ELEC 379 : DESIGN OF DIGITAL AND MICROCOMPUTER SYSTEMS 1998/99 WINTER SESSION, TERM 2 PC Interrupt Structure and 8259 DMA Controllers This lecture covers the use of interrupts and the vectored interrupt

More information

It is possible to define a number using a character or multiple numbers (see instruction DB) by using a string.

It is possible to define a number using a character or multiple numbers (see instruction DB) by using a string. 1 od 5 17. 12. 2017 23:53 (https://github.com/schweigi/assembler-simulator) Introduction This simulator provides a simplified assembler syntax (based on NASM (http://www.nasm.us)) and is simulating a x86

More information

Its Assembly language programming

Its Assembly language programming 8085 Architecture & Its Assembly language programming Dr A Sahu Dept of Computer Science & Engineering IIT Guwahati 8085 Era and Features 8085 Outline Block diagram (Data Path) Bus Structure Register Structure

More information

Marking Scheme. Examination Paper Department of CE. Module: Microprocessors (630313)

Marking Scheme. Examination Paper Department of CE. Module: Microprocessors (630313) Philadelphia University Faculty of Engineering Marking Scheme Examination Paper Department of CE Module: Microprocessors (630313) Final Exam Second Semester Date: 08/06/2014 Section 1 Weighting 40% of

More information

Ex: Write a piece of code that transfers a block of 256 bytes stored at locations starting at 34000H to locations starting at 36000H. Ans.

Ex: Write a piece of code that transfers a block of 256 bytes stored at locations starting at 34000H to locations starting at 36000H. Ans. INSTRUCTOR: ABDULMUTTALIB A H ALDOURI Conditional Jump Cond Unsigned Signed = JE : Jump Equal JE : Jump Equal ZF = 1 JZ : Jump Zero JZ : Jump Zero ZF = 1 JNZ : Jump Not Zero JNZ : Jump Not Zero ZF = 0

More information

The due date for submitting this assignment has passed. 1) How many times will the following loop be executed? Depends on the initial value of A

The due date for submitting this assignment has passed. 1) How many times will the following loop be executed? Depends on the initial value of A X reviewer2@nptel.iitm.ac.in Courses» and Microcontrollers Unit 4 - Week 3 Announcements Course Ask a Question Progress Mentor Course outline How to access the portal Week 3 Assignment The due date for

More information

Topic 6: Code Generation

Topic 6: Code Generation Compilers 2008 Topic 6: 6.4 Conditional Instructions Status Flags Conditionals A special register exists called the FLAGS register Consists of a sequence of bits, which are set (1) or unset (0). These

More information

16.317: Microprocessor Systems Design I Fall 2014

16.317: Microprocessor Systems Design I Fall 2014 16.317: Microprocessor Systems Design I Fall 2014 Exam 2 Solution 1. (16 points, 4 points per part) Multiple choice For each of the multiple choice questions below, clearly indicate your response by circling

More information

mith College Computer Science CSC231 Assembly Week #10 Fall 2017 Dominique Thiébaut

mith College Computer Science CSC231 Assembly Week #10 Fall 2017 Dominique Thiébaut mith College Computer Science CSC231 Assembly Week #10 Fall 2017 Dominique Thiébaut dthiebaut@smith.edu 2 Videos to Start With https://www.youtube.com/watch?v=fdmzngwchdk https://www.youtube.com/watch?v=k2iz1qsx4cm

More information

Intel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control.

Intel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control. Part 5 Intel x86 Jump Instructions Control Logic Fly over code Operations: Program Flow Control Operations: Program Flow Control Unlike high-level languages, processors don't have fancy expressions or

More information

Computer Architecture..Second Year (Sem.2).Lecture(4) مدرس المادة : م. سندس العزاوي... قسم / الحاسبات

Computer Architecture..Second Year (Sem.2).Lecture(4) مدرس المادة : م. سندس العزاوي... قسم / الحاسبات مدرس المادة : م. سندس العزاوي... قسم / الحاسبات... - 26 27 Assembly Level Machine Organization Usage of AND, OR, XOR, NOT AND : X Y X AND Y USE : to chick any bit by change ( to ) or ( to ) EX : AX = FF5

More information

Intel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control.

Intel x86 Jump Instructions. Part 5. JMP address. Operations: Program Flow Control. Operations: Program Flow Control. Part 5 Intel x86 Jump Instructions Control Logic Fly over code Operations: Program Flow Control Operations: Program Flow Control Unlike high-level languages, processors don't have fancy expressions or

More information

An overview of Interrupts ECE3534

An overview of Interrupts ECE3534 An overview of errupts ECE3534 Microprocessor erfacing: errupts Suppose a peripheral intermittently receives data, which must be serviced by the processor The processor can poll the peripheral regularly

More information

Assembly Language Programming of 8085

Assembly Language Programming of 8085 Assembly Language Programming of 8085 Topics 1. Introduction 2. Programming model of 8085 3. Instruction set of 8085 4. Example Programs 5. Addressing modes of 8085 6. Instruction & Data Formats of 8085

More information

IFE: Course in Low Level Programing. Lecture 6

IFE: Course in Low Level Programing. Lecture 6 IFE: Course in Low Level Programing Lecture 6 Instruction Set of Intel x86 Microprocessors Conditional jumps Jcc jump on condition cc, JMP jump always, CALL call a procedure, RET return from procedure,

More information

Lecture (08) x86 programming 7

Lecture (08) x86 programming 7 Lecture (08) x86 programming 7 By: Dr. Ahmed ElShafee 1 Conditional jump: Conditional jumps are executed only if the specified conditions are true. Usually the condition specified by a conditional jump

More information

9/25/ Software & Hardware Architecture

9/25/ Software & Hardware Architecture 8086 Software & Hardware Architecture 1 INTRODUCTION It is a multipurpose programmable clock drive register based integrated electronic device, that reads binary instructions from a storage device called

More information

EKT222 Miroprocessor Systems Lab 5

EKT222 Miroprocessor Systems Lab 5 LAB 5: Interrupts Objectives: 1) Ability to define interrupt in 8085 microprocessor 2) Ability to understanding the interrupt structure in the 8085 microprocessor 3) Ability to create programs using the

More information

CS412/CS413. Introduction to Compilers Tim Teitelbaum. Lecture 21: Generating Pentium Code 10 March 08

CS412/CS413. Introduction to Compilers Tim Teitelbaum. Lecture 21: Generating Pentium Code 10 March 08 CS412/CS413 Introduction to Compilers Tim Teitelbaum Lecture 21: Generating Pentium Code 10 March 08 CS 412/413 Spring 2008 Introduction to Compilers 1 Simple Code Generation Three-address code makes it

More information

Marking Scheme. Examination Paper. Module: Microprocessors (630313)

Marking Scheme. Examination Paper. Module: Microprocessors (630313) Philadelphia University Faculty of Engineering Marking Scheme Examination Paper Department of CE Module: Microprocessors (630313) Final Exam Second Semester Date: 12/06/2017 Section 1 Weighting 40% of

More information

CISC324: Operating Systems. Assignment 1

CISC324: Operating Systems. Assignment 1 SCHOOL OF COMPUTING, QUEEN S UNIVERSITY CISC324: Operating Systems Assignment 1 due Tuesday, Jan 22 at the 10:30 lecture January 5, 2019 Student Full Name: Student Number: Group Number: 1 1 COMPUTER ARCHITECTURE

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER MODEL ANSWER SUMMER 17 EXAMINATION Subject Title: Microprocessor Subject Code: 17443 I m p o r t a n t I n s t r u c t i o n s t o e x a m i n e r s : 1) The answers should be examined by key words and

More information

COMPUTER ENGINEERING DEPARTMENT

COMPUTER ENGINEERING DEPARTMENT Page 1 of 11 COMPUTER ENGINEERING DEPARTMENT December 31, 2007 COE 205 COMPUTER ORGANIZATION & ASSEMBLY PROGRAMMING Major Exam II First Semester (071) Time: 7:00 PM-9:30 PM Student Name : KEY Student ID.

More information

Lecture 10 Return-oriented programming. Stephen Checkoway University of Illinois at Chicago Based on slides by Bailey, Brumley, and Miller

Lecture 10 Return-oriented programming. Stephen Checkoway University of Illinois at Chicago Based on slides by Bailey, Brumley, and Miller Lecture 10 Return-oriented programming Stephen Checkoway University of Illinois at Chicago Based on slides by Bailey, Brumley, and Miller ROP Overview Idea: We forge shellcode out of existing application

More information

Branching and Looping

Branching and Looping Branching and Looping Ray Seyfarth August 10, 2011 Branching and looping So far we have only written straight line code Conditional moves helped spice things up In addition conditional moves kept the pipeline

More information

LABORATORY WORK NO. 7 FLOW CONTROL INSTRUCTIONS

LABORATORY WORK NO. 7 FLOW CONTROL INSTRUCTIONS LABORATORY WORK NO. 7 FLOW CONTROL INSTRUCTIONS 1. Object of laboratory The x86 microprocessor family has a large variety of instructions that allow instruction flow control. We have 4 categories: jump,

More information

BAHAR DÖNEMİ MİKROİŞLEMCİLER LAB4 FÖYÜ

BAHAR DÖNEMİ MİKROİŞLEMCİLER LAB4 FÖYÜ LAB4 RELATED INSTRUCTIONS: Compare, division and jump instructions CMP REG, memory memory, REG REG, REG memory, immediate REG, immediate operand1 - operand2 Result is not stored anywhere, flags are set

More information

EXPERIMENT WRITE UP. LEARNING OBJECTIVES: 1. Get hands on experience with Assembly Language Programming 2. Write and debug programs in TASM/MASM

EXPERIMENT WRITE UP. LEARNING OBJECTIVES: 1. Get hands on experience with Assembly Language Programming 2. Write and debug programs in TASM/MASM EXPERIMENT WRITE UP AIM: Assembly language program to search a number in given array. LEARNING OBJECTIVES: 1. Get hands on experience with Assembly Language Programming 2. Write and debug programs in TASM/MASM

More information

Computer Organization & Assembly Language Programming. CSE 2312 Lecture 15 Addressing and Subroutine

Computer Organization & Assembly Language Programming. CSE 2312 Lecture 15 Addressing and Subroutine Computer Organization & Assembly Language Programming CSE 2312 Lecture 15 Addressing and Subroutine 1 Sections in 8088 Code TEXT section, for the processor instructions. DATA section for the initialization

More information

CSC 2400: Computer Systems. Towards the Hardware: Machine-Level Representation of Programs

CSC 2400: Computer Systems. Towards the Hardware: Machine-Level Representation of Programs CSC 2400: Computer Systems Towards the Hardware: Machine-Level Representation of Programs Towards the Hardware High-level language (Java) High-level language (C) assembly language machine language (IA-32)

More information

Assembly Language LAB

Assembly Language LAB Assembly Language LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering 2013 ECOM 2125: Assembly Language LAB Created by: Eng. Ahmed M. Ayash Modified and Presented By: Eihab

More information

SPRING TERM BM 310E MICROPROCESSORS LABORATORY PRELIMINARY STUDY

SPRING TERM BM 310E MICROPROCESSORS LABORATORY PRELIMINARY STUDY BACKGROUND 8086 CPU has 8 general purpose registers listed below: AX - the accumulator register (divided into AH / AL): 1. Generates shortest machine code 2. Arithmetic, logic and data transfer 3. One

More information

Chapter 6 (Part a) Conditional Processing

Chapter 6 (Part a) Conditional Processing Islamic University Gaza Engineering Faculty Department of Computer Engineering ECOM 2025: Assembly Language Discussion Chapter 6 (Part a) Conditional Processing Eng. Eman R. Habib April, 2014 2 Assembly

More information

Lab 3. The Art of Assembly Language (II)

Lab 3. The Art of Assembly Language (II) Lab. The Art of Assembly Language (II) Dan Bruce, David Clark and Héctor D. Menéndez Department of Computer Science University College London October 2, 2017 License Creative Commons Share Alike Modified

More information

CSC 8400: Computer Systems. Machine-Level Representation of Programs

CSC 8400: Computer Systems. Machine-Level Representation of Programs CSC 8400: Computer Systems Machine-Level Representation of Programs Towards the Hardware High-level language (Java) High-level language (C) assembly language machine language (IA-32) 1 Compilation Stages

More information

Assembly Language Programming of 8085

Assembly Language Programming of 8085 Assembly Language Programming of 8085 1. Introduction A microprocessor executes instructions given by the user Instructions should be in a language known to the microprocessor Microprocessor understands

More information

Basic Assembly Instructions

Basic Assembly Instructions Basic Assembly Instructions Ned Nedialkov McMaster University Canada SE 3F03 January 2013 Outline Multiplication Division FLAGS register Branch Instructions If statements Loop instructions 2/21 Multiplication

More information

Faculty of Engineering Student Number:

Faculty of Engineering Student Number: Philadelphia University Student Name: Faculty of Engineering Student Number: Dept. of Computer Engineering Final Exam, Second Semester: 2013/2014 Course Title: Microprocessors Date: 08/06/2014 Course No:

More information

mith College Computer Science CSC231 Assembly Week #9 Spring 2017 Dominique Thiébaut

mith College Computer Science CSC231 Assembly Week #9 Spring 2017 Dominique Thiébaut mith College Computer Science CSC231 Assembly Week #9 Spring 2017 Dominique Thiébaut dthiebaut@smith.edu 2 Videos to Watch at a Later Time https://www.youtube.com/watch?v=fdmzngwchdk https://www.youtube.com/watch?v=k2iz1qsx4cm

More information

Lecture 5 Program Logic and Control

Lecture 5 Program Logic and Control Lecture 5 Program Logic and Control Chapter Outline Short, near and far address JMP Instruction The CMP Instruction Conditional Jump instruction The Loop instruction While Loop REPEAT Loop Short,near,and

More information

CHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMMUNICATION ENGINEERING REG 2008 TWO MARKS QUESTION AND ANSWERS

CHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY COMMUNICATION ENGINEERING REG 2008 TWO MARKS QUESTION AND ANSWERS CHETTINAD COLLEGE OF ENGINEERING AND TECHNOLOGY B.E.,/B.TECH., ELECTRONICS EC6504 MICROPROCESSORS & MICRO CONTROLLERS COMMUNICATION ENGINEERING REG 2008 TWO MARKS QUESTION AND ANSWERS UNIT 1 AND 2 CS SUBJECT

More information

Microprocessor Micro Syllabus BSc. CSIT, IOST, TU. Microprocessor

Microprocessor Micro Syllabus BSc. CSIT, IOST, TU. Microprocessor Microprocessor Micro Syllabus BSc. CSIT, IOST, TU Microprocessor Course Title: Microprocessor Full Marks: 60 + 20 + 20 Course No: CSC162 Pass Marks: 24 + 8 + 8 Nature of the Course: Theory + Lab Credit

More information

MSMF GATE CENTRE. Sub: MICROPROCESSORS. Time: 50min Date: Marks:33

MSMF GATE CENTRE. Sub: MICROPROCESSORS. Time: 50min Date: Marks:33 MSMF GATE CENTRE Sub: MICROPROCESSORS Time: 50min Date:20-12-16 Marks:33 1. Which interrupt has highest priority in 8085 microprocessor? a) INTR b) RST 4.5 c) RST 6.5 d) RST 7.5 2. In 8085 microprocessor,

More information

MACHINE CONTROL INSTRUCTIONS: 1. EI

MACHINE CONTROL INSTRUCTIONS: 1. EI Lecture-33 MACHINE CONTROL INSTRUCTIONS: 1. EI (Enable interrupts): The interrupt system is disabled just after RESET operation. There is an internal INTE F/F (Interrupt enable flipflop) which is reset

More information

Chapter 9. Programming Framework

Chapter 9. Programming Framework Chapter 9 Programming Framework Lesson 1 Registers Registers Pointers Accumulator Status General Purpose Outline CPU Registers Examples 8-bitA (Accumulator) Register 8-bit B Register 8-bitPSW (Processor

More information

Mr. Sapan Naik 1. Babu Madhav Institute of Information Technology, UTU

Mr. Sapan Naik 1. Babu Madhav Institute of Information Technology, UTU 5 Years Integrated M.Sc.(IT) Semester 4 060010402 System Programming Question Bank Unit 1: Introduction 1. Write the decimal equivalent for each integral power of 2 from 2! to 2!". 2. Convert the following

More information

THE UNIVERSITY OF TRINIDAD & TOBAGO

THE UNIVERSITY OF TRINIDAD & TOBAGO THE UNIVERSITY OF TRINIDAD & TOBAGO FINAL ASSESSMENT/EXAMINATIONS DECEMBER 2012 Course Code and Title: Microprocessor Architecture & Interfacing Programme: Computer Engineering Technician Date and Time:

More information

Introduction to Assembly Language Programming (Instruction Set) 1/18/2011 1

Introduction to Assembly Language Programming (Instruction Set) 1/18/2011 1 Introduction to Assembly Language Programming (Instruction Set) 1/18/2011 1 High Level Language Compiler Assembly Language Assembler Machine Code Microprocessor Hardware 1/18/2011 2 8085A Instruction Set

More information

Second Part of the Course

Second Part of the Course CSC 2400: Computer Systems Towards the Hardware 1 Second Part of the Course Toward the hardware High-level language (C) assembly language machine language (IA-32) 2 High-Level Language g Make programming

More information

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI UNIT I THE 8085 & 8086 MICROPROCESSORS. PART A (2 Marks)

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI UNIT I THE 8085 & 8086 MICROPROCESSORS. PART A (2 Marks) MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI-621213. UNIT I THE 8085 & 8086 MICROPROCESSORS PART A (2 Marks) 1. Give the significance of SIM and RIM instruction available in 8085. [NOV/DEC 2006] Instruction

More information

UNIVERSITY OF CALIFORNIA, RIVERSIDE

UNIVERSITY OF CALIFORNIA, RIVERSIDE Final Page 1 of 7 UNIVERSITY OF CALIFORNIA, RIVERSIDE Computer Science Department CS61 Machine Organization & Assembly Language Final September 1, 2000 53 Name: Solution Key Student ID#: Please print legibly

More information

CS401 - Computer Architecture and Assembly Language Programming Glossary By

CS401 - Computer Architecture and Assembly Language Programming Glossary By CS401 - Computer Architecture and Assembly Language Programming Glossary By absolute address : A virtual (not physical) address within the process address space that is computed as an absolute number.

More information

x86 architecture et similia

x86 architecture et similia x86 architecture et similia 1 FREELY INSPIRED FROM CLASS 6.828, MIT A full PC has: PC architecture 2 an x86 CPU with registers, execution unit, and memory management CPU chip pins include address and data

More information

Summer 2003 Lecture 14 07/02/03

Summer 2003 Lecture 14 07/02/03 Summer 2003 Lecture 14 07/02/03 LAB 6 Lab 6 involves interfacing to the IBM PC parallel port Use the material on wwwbeyondlogicorg for reference This lab requires the use of a Digilab board Everyone should

More information

The 80386SX Processor Bus and Real-Mode Instruction Set

The 80386SX Processor Bus and Real-Mode Instruction Set EECE 379 : DESIGN OF DIGITAL AND MICROCOMPUTER SYSTEMS 2000/2001 WINTER SESSION, TERM 1 The 80386SX Processor Bus and Real-Mode Instruction Set This chapter describes the signals and operation of the Intel

More information

PHY4635/5635 Spring Lecture 8: Program Control Instructions

PHY4635/5635 Spring Lecture 8: Program Control Instructions PHY4635/5635 Spring 2009 Lecture 8: Program Control Instructions Short, Near and Far Jumps Short jump: jump is within +127 to -128 bytes from the address following the jump. Relative jumps : moves with

More information

IBM PC Hardware CPU 8088, Pentium... ALU (Arithmetic and Logic Unit) Registers. CU (Control Unit) IP.

IBM PC Hardware CPU 8088, Pentium... ALU (Arithmetic and Logic Unit) Registers. CU (Control Unit) IP. IBM PC Hardware CPU 8088, 8086 80286 80386 80486 Pentium... ALU (Arithmetic and Logic Unit) Registers CU (Control Unit) IP Memory ROM BIOS I/O RAM OS Programs Video memory BIOS data Interrupt Vectors Memory

More information

Digital Forensics Lecture 4 - Reverse Engineering

Digital Forensics Lecture 4 - Reverse Engineering Digital Forensics Lecture 4 - Reverse Engineering Deciphering Code Structures Akbar S. Namin Texas Tech University Spring 2017 Goal: Learn about the most common logical and control flow constructs used

More information

Computer Organization and Architecture, Pt. 2

Computer Organization and Architecture, Pt. 2 Computer Organization and Architecture, Pt. 2 Charles Abzug, Ph.D. Department of Computer Science James Madison University Harrisonburg, VA 22807 Voice Phone: 540-568-8746, E-mail: CharlesAbzug@ACM.org

More information

Meet & Greet! Come hang out with your TAs and Fellow Students (& eat free insomnia cookies)

Meet & Greet! Come hang out with your TAs and Fellow Students (& eat free insomnia cookies) Meet & Greet! Come hang out with your TAs and Fellow Students (& eat free insomnia cookies) When : Friday, Sept. 29th. 5-6 pm Where : 3rd Floor Atrium, CIT CS33 Intro to Computer Systems X 1 Copyright

More information

Summer 2003 Lecture 15 07/03/03

Summer 2003 Lecture 15 07/03/03 Summer 2003 Lecture 15 07/03/03 Initialization of Variables In the C (or C++) programming language any variable definition can have an optional initializer for the variable. How and when the initialization

More information

INSTRUCTION SET OF 8085

INSTRUCTION SET OF 8085 INSTRUCTION SET OF 8085 Instruction Set of 8085 An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor

More information

EE2007 Microprocessor systems.

EE2007 Microprocessor systems. EE2007 Microprocessor systems Tutorial 1 Semester 1 AY 2010-11 Ganesh Iyer ganesh.vigneswara@gmail.com (facebook, gtalk) http://ganeshniyer.com About Me I have 3 years of Industry work experience in Bangalore,

More information

PESIT Bangalore South Campus

PESIT Bangalore South Campus INTERNAL ASSESSMENT TEST 2 Date : 02/04/2018 Max Marks: 40 Subject & Code : Microprocessor (15CS44) Section : IV A and B Name of faculty: Deepti.C Time : 8:30 am-10:00 am Note: Note: Answer any five complete

More information

Logic Instructions. Basic Logic Instructions (AND, OR, XOR, TEST, NOT, NEG) Shift and Rotate instructions (SHL, SAL, SHR, SAR) Segment 4A

Logic Instructions. Basic Logic Instructions (AND, OR, XOR, TEST, NOT, NEG) Shift and Rotate instructions (SHL, SAL, SHR, SAR) Segment 4A Segment 4A Logic Instructions Basic Logic Instructions (AND, OR, XOR, TEST, NOT, NEG) Shift and Rotate instructions (SHL, SAL, SHR, SAR) Course Instructor Mohammed Abdul kader Lecturer, EEE, IIUC Basic

More information

Ex : Write an ALP to evaluate x(y + z) where x = 10H, y = 20H and z = 30H and store the result in a memory location 54000H.

Ex : Write an ALP to evaluate x(y + z) where x = 10H, y = 20H and z = 30H and store the result in a memory location 54000H. Ex : Write an ALP to evaluate x(y + z) where x = 10H, y = 20H and z = 30H and store the result in a memory location 54000H. MOV AX, 5000H MOV DS, AX MOV AL, 20H MOV CL, 30H ADD AL, CL MOV CL, 10H MUL CL

More information

Instructions Involve a Segment Register (SR-field)

Instructions Involve a Segment Register (SR-field) BYTE 1 = 11000111 2 = C7 16 BYTE 2 = (MOD)000(R/M) = 100000112 = 83 16 BYTE 3 = 34 16 and BYTE 4 = 12 16 BYTE 5 = CD 16 and BYTE 6 = AB 16 The machine code for the instruction is: MOV [BP+DI+1234H], 0ABCDH

More information

Microprocessor Architecture

Microprocessor Architecture Microprocessor - 8085 Architecture 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration

More information

8086 Hardware Specification

8086 Hardware Specification Content: Segment 5 8086 Hardware Specification 8086 Modes of operation. Pin diagram and pin function of 8086. 8284A Clock generator operation and pin functions. Prepared By: Mohammed Abdul Kader Lecturer,

More information

Assembly Language: Overview!

Assembly Language: Overview! Assembly Language: Overview! 1 Goals of this Lecture! Help you learn:" The basics of computer architecture" The relationship between C and assembly language" IA-32 assembly language, through an example"

More information

Selection and Iteration. Chapter 7 S. Dandamudi

Selection and Iteration. Chapter 7 S. Dandamudi Selection and Iteration Chapter 7 S. Dandamudi Outline Unconditional jump Compare instruction Conditional jumps Single flags Unsigned comparisons Signed comparisons Loop instructions Implementing high-level

More information

UNIT 1 REFERENCE 1 PREPARED BY S.RAVINDRAKUMAR, LECT/ECE, CHETTINAD COLLEGE OF ENGG AND TECH, KARUR

UNIT 1 REFERENCE 1 PREPARED BY S.RAVINDRAKUMAR, LECT/ECE, CHETTINAD COLLEGE OF ENGG AND TECH, KARUR UNIT 1 REFERENCE 1 PROGRAMMING THE 8085 DEVELOPMENT OF PROGRAM A program is a sequence of instructions written to tell a computer to perform a specific function. The instructions are selected from the

More information

Subject Code: Model Answer Page No: /25

Subject Code: Model Answer Page No: /25 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

CPU. Fall 2003 CSE 207 Digital Design Project #4 R0 R1 R2 R3 R4 R5 R6 R7 PC STATUS IR. Control Logic RAM MAR MDR. Internal Processor Bus

CPU. Fall 2003 CSE 207 Digital Design Project #4 R0 R1 R2 R3 R4 R5 R6 R7 PC STATUS IR. Control Logic RAM MAR MDR. Internal Processor Bus http://www.engr.uconn.edu/~barry/cse207/fa03/project4.pdf Page 1 of 16 Fall 2003 CSE 207 Digital Design Project #4 Background Microprocessors are increasingly common in every day devices. Desktop computers

More information

CS 261 Fall Mike Lam, Professor. x86-64 Control Flow

CS 261 Fall Mike Lam, Professor. x86-64 Control Flow CS 261 Fall 2018 Mike Lam, Professor x86-64 Control Flow Topics Condition codes Jumps Conditional moves Jump tables Motivation We cannot translate the following C function to assembly, using only data

More information

MIPS Programming. A basic rule is: try to be mechanical (that is, don't be "tricky") when you translate high-level code into assembler code.

MIPS Programming. A basic rule is: try to be mechanical (that is, don't be tricky) when you translate high-level code into assembler code. MIPS Programming This is your crash course in assembler programming; you will teach yourself how to program in assembler for the MIPS processor. You will learn how to use the instruction set summary to

More information

LABORATORY 8: USING BIOS ROUTINES FOR KEYBOARD INPUT AND DISPLAY OUTPUT

LABORATORY 8: USING BIOS ROUTINES FOR KEYBOARD INPUT AND DISPLAY OUTPUT LABORATORY 8: USING BIOS ROUTINES FOR KEYBOARD INPUT AND DISPLAY OUTPUT NAME: STUDENT ID#: Objectives Learn how to: Use the read keyboard and display character BIOS routines. Display prompt messages on

More information

COMP 110/L Lecture 10. Kyle Dewey

COMP 110/L Lecture 10. Kyle Dewey COMP 110/L Lecture 10 Kyle Dewey switch Outline switch Problem if is verbose when checking many conditions. Problem if is verbose when checking many conditions. if (x == 5) { return foo ; else if (x ==

More information

Basic characteristics & features of 8086 Microprocessor Dr. M. Hebaishy

Basic characteristics & features of 8086 Microprocessor Dr. M. Hebaishy Basic characteristics & features of 8086 Microprocessor Dr. M. Hebaishy Digital Logic Design Ch1-1 8086 Microprocessor Features: The 8086 microprocessor is a 16 bit microprocessor. The term 16 bit means

More information

SOFTWARE ARCHITECTURE 5. COMPILER

SOFTWARE ARCHITECTURE 5. COMPILER 1 SOFTWARE ARCHITECTURE 5. COMPILER Tatsuya Hagino hagino@sfc.keio.ac.jp slides URL https://vu5.sfc.keio.ac.jp/sa/ 2 Programming Language Programming Language Artificial language to express instructions

More information

4 Categories Of 8085 Instructions That Manipulate Data

4 Categories Of 8085 Instructions That Manipulate Data 4 Categories Of 8085 Instructions That Manipulate Data 4 I OW of 8257 isconnected to the MEMR of system bus. A4 A15 lines to List categories of8085 instructions that manipulate data. Ans. 8085instruction,

More information

Babu Madhav Institute of Information Technology, UTU

Babu Madhav Institute of Information Technology, UTU 5 Years Integrated M.Sc.(IT) Semester 4 060010309 : DSE3 Microprocessor Programming and Interfacing Question Bank 1. Write an assembly language program to check whether the given number is odd or even.

More information

Chapter 3. Assembly Language Programming with 8086

Chapter 3. Assembly Language Programming with 8086 Chapter 3 Assembly Language Programming with 8086 UNIT - III Assembly Language Programming with 8086- Machine level programs, Machine coding the programs, Programming with an assembler, Assembly Language

More information

CS-202 Microprocessor and Assembly Language

CS-202 Microprocessor and Assembly Language CS-202 Microprocessor and Assembly Language Lecture 2 Introduction to 8086 Assembly Language Dr Hashim Ali Spring - 2019 Department of Computer Science and Engineering HITEC University Taxila!1 Lecture

More information

Instruction Set Instruction set of 8085 can be classified in following groups: Data Transfer Instructions These instructions can perform data transfer operations between Registers of 8085 e.g. MOV 8085

More information

CG2007 Microprocessor systems.

CG2007 Microprocessor systems. CG2007 Microprocessor systems Tutorial 1 Semester 2 AY 2011-12 Ganesh Iyer ganesh.vigneswara@gmail.com http://ganeshniyer.com About Me I have 3 years of Industry work experience in Bangalore, India. I

More information

Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, Second Semester: 2016/2017 Dept. of Computer Engineering Course Title: Microprocessors Date: 12/06/2017

More information

Review addressing modes

Review addressing modes Review addressing modes Op Src Dst Comments movl $0, %rax Register movl $0, 0x605428 Direct address movl $0, (%rcx) Indirect address movl $0, 20(%rsp) Indirect with displacement movl $0, -8(%rdi, %rax,

More information

The Boot: Getting ready for the OS

The Boot: Getting ready for the OS The Boot: Getting ready for the OS LISHA/UFSC Prof. Dr. Antônio Augusto Fröhlich guto@lisha.ufsc.br http://www.lisha.ufsc.br/guto March 2011 March 2011 (http://www.lisha.ufsc.br) 1 Where are we now? BIOS

More information

CSE P 501 Exam 8/5/04 Sample Solution. 1. (10 points) Write a regular expression or regular expressions that generate the following sets of strings.

CSE P 501 Exam 8/5/04 Sample Solution. 1. (10 points) Write a regular expression or regular expressions that generate the following sets of strings. 1. (10 points) Write a regular ression or regular ressions that generate the following sets of strings. (a) (5 points) All strings containing a s, b s, and c s with at least one a and at least one b. [abc]*a[abc]*b[abc]*

More information

Class Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2

Class Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2 Class Notes CS400 Part VI Dr.C.N.Zhang Department of Computer Science University of Regina Regina, SK, Canada, S4S 0A2 C. N. Zhang, CS400 83 VI. CENTRAL PROCESSING UNIT 1 Set 1.1 Addressing Modes and Formats

More information

Counters & Time Delays. Microprocessors & Interfacing 1

Counters & Time Delays. Microprocessors & Interfacing 1 Counters & Time Delays Microprocessors & Interfacing 1 Counters A loop counter is set up by loading a register with a certain value Then using the DCR (to decrement) and INR (to increment) the contents

More information

Section 002. Read this before starting!

Section 002. Read this before starting! Points missed: Student's Name: _ Total score: /100 points East Tennessee State University -- Department of Computer and Information Sciences CSCI 2150 Computer Organization Final Exam for Fall Semester,

More information

Week 11 Programmable Interrupt Controller

Week 11 Programmable Interrupt Controller Week 11 Programmable Interrupt Controller 8259 Programmable Interrupt Controller The 8259 programmable interrupt controller (PIC) adds eight vectored priority encoded interrupts to the microprocessor.

More information

3.0 Instruction Set. 3.1 Overview

3.0 Instruction Set. 3.1 Overview 3.0 Instruction Set 3.1 Overview There are 16 different P8 instructions. Research on instruction set usage was the basis for instruction selection. Each instruction has at least two addressing modes, with

More information

Architecture & Instruction set of 8085 Microprocessor and 8051 Micro Controller

Architecture & Instruction set of 8085 Microprocessor and 8051 Micro Controller of 8085 microprocessor 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration 8-bit

More information