ASIX USB-to-LAN Applications Layout Guide

Transcription

1 ASIX USB-to-LAN Applications Revision 1.0 Dec. 11th,

2 Revision Date Description /12/11 New release. ASIX USB-to-LAN Applications Revision History 2

3 Content 1. Introduction Layer PCB Design USB line USB Layout Notes PCB (FR4 material) and impedance Trace route for USB2.0 PHY and Connector Ethernet line Ethernet Layout Notes Power and Ground Planes EMI Considerations ESD Considerations Thermal Considerations Improve the Cooling Plane Improve the Air Convection Disable the on-chip regulator...14 Figures Figure 1. A Sample 4-Layer PCB Design of the USB-to-LAN boards...4 Figure 2. The Trace Route between the AX88772A/AX88172A and the USB connector...7 Figure 3. The Trace Route between the AX88178/AX88772 and the USB connector...7 Figure 4. The Chassis/Digital Ground Planes of the USB-to-LAN boards...9 Figure 5. A Sample Digital/Analog Power Planes of the AX88772A/AX88172A boards...10 Figure 6. A Sample Digital/Analog Power Planes of the AX88178/AX88772 boards...10 Figure 7. A Sample Magnetic Circuit of Single RJ-45 Connector for ESD Considerations...12 Figure 8. A Sample Magnetic Circuit of Separate Magnetic + RJ-45 Connector for ESD Considerations 13 Figure 9. A Sample PCB Layout for ESD Considerations...13 Figure 10. AX88772A/AX88172A On-Chip Regulator Disabled Reference Circuit...14 Figure 11. AX88772 On-Chip Regulator Disabled Reference Circuit...15 Figure 12. AX88178 On-Chip Regulator Disabled Reference Circuit

4 1. Introduction ASIX Electronics provides a couple of USB 2.0 to Gigabit/Fast Ethernet controllers that are the high performance and highly integrated ASIC which enables low cost, small form factor, and simple plug-and-play Gigabit/Fast Ethernet network connection capability for desktop, notebook PC, Ultra-Mobile PC, docking station, game console, digital-home appliances, and any embedded systems using popular USB port. The USB 2.0 to Gigabit/Fast Ethernet controllers have an USB interface to communicate with USB Host Controller and are compliant with USB specification V1.1 and V2.0. The USB 2.0 to Gigabit/Fast Ethernet controllers implement Gigabit/Fast Ethernet LAN function based on IEEE 802.3, 802.3u and 802.3ab (for AX88178) standards and integrate an on-chip Gigabit/Fast Ethernet PHY to simplify system design. The following are the ASIX USB-to-LAN solutions ( for your reference. AX USB2.0 to 10/100/1000M Gigabit Ethernet Controller with GMII Interface AX88172A -- Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller with MII interface AX88772A -- Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller AX USB2.0 to 10/100M Fast Ethernet Controller This layout guide provides some important information about the PCB layout of the ASIX USB-to-LAN applications Layer PCB Design We strongly suggest users to design their USB-to-LAN applications with 4-layer PCB boards. The 4-layer PCB design will be able to avoid some potential EMI, thermal, etc. issues on your USB-to-LAN boards. The following is a sample 4-Layer PCB design of the USB-to-LAN boards for your reference. Layer Description 1 Component (main) USB item, D+/D- signals 2 Ground Ground plane (include AGND and DGND). 3 Power Power plane (include AVCC and DVCC). 4 Component Magnetic/other items & signals Figure 1. A Sample 4-Layer PCB Design of the USB-to-LAN boards 4

5 3. USB line This section describes some general USB signal layout guideline for the USB 2.0 to Gigabit/Fast Ethernet applications USB Layout Notes 1. The differential signals, D+/D- should be routed with minimum trace length. Layout consideration should carefully avoid the nearby clock or noisy digital signals being routed too close to the D+/D- signals. 2. The USB differential signals between USB connector and DP (DPRS) / DM (DMRS) should be routed on the same component side on PCB, adjacent to the layer for ground plane. Avoid routing these differential signals through some vias or through ground plane to inadvertently affect the impedance control on these high-speed differential traces. 3. Any 90-degree turn in trace routing should be accomplished with two 135-degree turns as shown in example below. Worst Better 4. Avoid routing the D+ and D- near crystal, clock synthesizer, transformer, and other IC with switching noise from digital signals. 5. Avoid routing the D+ and D- near the edge of PCB or power planes. 6. The trace spacing between D+ and D- is 8 mils. 7. Keep the trace length of D+ and D- as equal as possible. 5

6 3-2. PCB (FR4 material) and impedance 1. W = 8 mils 2. S (D+ to D-) = 8 mils 3. T = Thickness of the trace = 1 ounce copper 4. D (Ground Separation) 20 mils 5. H (Dielectric thickness, distance of trace from the ground plane. Board thickness) 63 mils 6. The USB differential signals, D+/D-, should carefully maintain impedance control on PCB, the ideal differential impedance value between the pair should be 90 ohm. 6

7 3-3. Trace route for USB2.0 PHY and Connector Figure 2. The Trace Route between the AX88772A/AX88172A and the USB connector Figure 3. The Trace Route between the AX88178/AX88772 and the USB connector 7

8 4. Ethernet line This section describes some general Ethernet layout guideline for the USB 2.0 to Gigabit/Fast Ethernet applications Ethernet Layout Notes 1. The crystal/oscillator clock and the switching noise from digital signals should be far away from TX+/-, RX+/- pairs. 2. The trace length from the USB-to-LAN controller to the transformer should not be longer than 5 inches, keep the trace as straight as possible, and keep it parallel for differential pairs. 3. Keep TX, RX differential signals running symmetric, equal length, and closely. The trace spacing D1 between TX+ and TX- or between RX+ and RX- pair should be in 8 ~ 10 mils. The better spacing D2 between TX+/- and RX+/- pairs should be larger than 200 mils but could be smaller than 200 mils if your application is really difficult to meet this requirement. In this case, you should do some detailed testing to qualify the network function of your application. 4. Keep the trace length difference between TX+ and TX- (or RX+ and RX-) in 700 mils. 5. Keep RX+/- signal on the top layer, the RX+/- signal should avoid any vias, if possible. 6. Avoid right angle signal trace. Worst Better 7. Avoid signals over power plane. 8. The USB-to-LAN controller, transformer and RJ-45 should be placed as close as possible. 9. The termination resistors 49.9Ω and capacitors of TX± and RX± pairs should be placed near the transformer side and should be shorter than 400 mils. 8

9 5. Power and Ground Planes 5-1. Isolate the RJ-45 connector chassis ground and digital ground. Figure 4. The Chassis/Digital Ground Planes of the USB-to-LAN boards 9

10 5-2. Isolate all digital/analog power planes. Figure 5. A Sample Digital/Analog Power Planes of the AX88772A/AX88172A boards Figure 6. A Sample Digital/Analog Power Planes of the AX88178/AX88772 boards Note: The above figures are just some examples of the Digital/Analog Power Planes of the USBto-LAN boards. You can implement the digital/analog power planes based on the real requirement of your target application. 10

11 6. EMI Considerations 6-1. The chosen connector must be shielded so that EMI integrity of the design is not compromised. The shield must be electrically connected to chassis ground to extend the chassis barrier for high frequency emissions. If an unshielded connector were used, the EMI would pass through the nylon material of the connector. The shield will also prevent less external EMI from entering the chassis To reduce electromagnetic emissions and susceptibility, it is imperative that traces from the transceiver to the magnetic sand from the magnetic to the RJ-45 be routed as differential pairs. The objective is to close the loop area formed by the two conductors. The radiated field from the loop or the voltage picked up by the loop by external fields is governed by the field strength and the area formed by the two conductors. Reasonable board design uses 5~10 mils trace widths separated by 10 mils. Transmit differential pairs should be routed adjacent to a VDDO power plane. 11

12 7. ESD Considerations This section describes some information about the ESD design guideline. Users can refer to the following circuit to avoid the ESD issue. The high-energy pulses can cause abnormal system behavior and/or damage the silicon chips. The high energy can enter the system through the RJ-45 cable. There are eight wires in the RJ-45 cable and are grouped into 4 pairs as 2 active pairs (pin 1,2 & 3,6) and 2 unused pairs (pin 4,5 & 7,8). If the high energy enters the system through the active pairs (pin 1,2 & 3,6) of RJ-45 cable, the Ethernet transformer will isolate the high energy. The unwanted high energy will be redirected to Chassis ground through a high voltage capacitor (2KV). If the high energy enters the system through the unused pairs (pin 4,5 & 7,8) of RJ-45 cable, these pins are connected to Chassis ground through a high voltage capacitor (2KV) so the unwanted high energy will be redirected to Chassis ground too. Note: The following figures are just some examples of the magnetic circuit for the ESD considerations. Please refer to the respective AX88x72A/AX88772/AX88178 reference schematics for correct magnetic circuit. Figure 7. A Sample Magnetic Circuit of Single RJ-45 Connector for ESD Considerations 12

13 Figure 8. A Sample Magnetic Circuit of Separate Magnetic + RJ-45 Connector for ESD Considerations You should isolate the chassis ground plane and digital ground plane through the 1M resistor and 0.1uF capacitor. Figure 9. A Sample PCB Layout for ESD Considerations 13

14 8. Thermal Considerations This section describes some information about how to reduce the operating temperature on the USB-to-LAN applications Improve the Cooling Plane There are two major heat sources on the USB-to-LAN applications. One is the USB-to-LAN controller and the other one is the external 5V to 3.3V regulator. You can connect the VCC/GND pins of the USB-to-LAN controller to the respective power/ground planes to increase the cooling effect and reduce the operating temperature of the USB-to-LAN controller. Please refer to Figure 3 & 4 for the ground/power planes of the USB-to- LAN boards. You can also add a cooling plane for the external 5V to 3.3V regulator to reduce the operating temperature of the external 5V to 3.3V regulator Improve the Air Convection If the USB-to-LAN controller was implemented on the embedded system, you can put the USB-to-LAN controller at the location with good air convection to reduce the operating temperature of the USB-to-LAN controller Disable the on-chip regulator Disabling the on-chip regulator of the USB-to-LAN controller is an alternative solution to reduce the operating temperature of the USB-to-LAN controller itself. However, this solution may or may not improve the operating temperature of your overall USB-to-LAN boards, depending on how the actual 1.8V power supply is generated. Figure 10. AX88772A/AX88172A On-Chip Regulator Disabled Reference Circuit 14

15 Figure 11. AX88772 On-Chip Regulator Disabled Reference Circuit Figure 12. AX88178 On-Chip Regulator Disabled Reference Circuit 15

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