Virtual Memory (2) 1
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- Elvin French
- 5 years ago
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1 Virtual Memory (2) 1
2 Changelog 1 Changes made in this version not seen in first lecture: 21 November 2017: 1-level example: added final answer of memory value, not just location 21 November 2017: two-level example: answer was 0x0A not 0xBA 21 November 2017: do we really need a complete copy?: even size of memory regions between copies 21 November 2017: swapping components: add (if modified) as condition on when we swap out
3 exercise: 64-bit system 2 my desktop: 39-bit physical addresses; 48-bit virtual addresses 4096 byte pages
4 exercise: 64-bit system 2 my desktop: 39-bit physical addresses; 48-bit virtual addresses 4096 byte pages top 16 bits of address not used for translation
5 exercise: 64-bit system 2 my desktop: 39-bit physical addresses; 48-bit virtual addresses 4096 byte pages exercise: how many page table entries? exercise: how large are physical page numbers?
6 exercise: 64-bit system 2 my desktop: 39-bit physical addresses; 48-bit virtual addresses 4096 byte pages exercise: how many page table entries? 2 48 /2 12 = 2 36 entries exercise: how large are physical page numbers? = 27 bits
7 exercise: 64-bit system 2 my desktop: 39-bit physical addresses; 48-bit virtual addresses 4096 byte pages exercise: how many page table entries? 2 48 /2 12 = 2 36 entries exercise: how large are physical page numbers? = 27 bits page table entries are 8 bytes (room for expansion, metadata) would take up 2 39 bytes?? (512GB??)
8 3
9 exam and conflicts 4 final exam 7 December 2017 Gilmer 130 fill out conflict form (today, please?) if you can t make it linked off schedule also Collab announcement
10 rotate HW and cache blocking 5 many of you seemed to think you were doing just loop unrolling but generally changed the order of memory accesses in the process basically cache blocking // unroll + cache blocking for (int i =...; i += 2) for (int j =...) { f(i + 0, j); f(i + 1, j); } // unroll loop in i only // (probably not very helpful) for (int i =...; i += 2) { for (int j =...) f(i, j); for (int j =...) f(i + 1, j); }
11 page table tricks 6 page tables let operating systems do magic with memory key idea: OS doesn t need to crash on a fault! instead: change page tables and rerun memory access similar idea to trap-and-emulate
12 space on demand 7 Program Memory Used by OS Stack Heap / other dynamic Writable data Code + Constants
13 space on demand 7 Program Memory Used by OS Stack used stack space (12 KB) Heap / other dynamic Writable data Code + Constants wasted space? (huge??)
14 space on demand 7 Program Memory Used by OS Stack used stack space (12 KB) OS would like to allocate space only if needed Heap / other dynamic Writable data wasted space? (huge??) Code + Constants
15 allocating space on demand 8 %rsp = 0x7FFFC // requires more stack space A: pushq %rbx B: movq 8(%rcx), %rbx C: addq %rbx, %rax... VPN valid? physical page 0x7FFFB x7FFFC 1 0x200DF 0x7FFFD 1 0x x7FFFE 1 0x x7FFFF 1 0x12345
16 allocating space on demand 8 %rsp = 0x7FFFC // requires more stack space A: pushq %rbx page fault! B: movq 8(%rcx), %rbx C: addq %rbx, %rax... VPN valid? physical page 0x7FFFB x7FFFC 1 0x200DF 0x7FFFD 1 0x x7FFFE 1 0x x7FFFF 1 0x12345 pushq triggers exception hardware says accessing address 0x7FFFBFF8 OS looks up what s should be there stack
17 allocating space on demand 8 %rsp = 0x7FFFC // requires more stack space A: pushq %rbx B: movq 8(%rcx), %rbx C: addq %rbx, %rax... restarted VPN valid? physical page 0x7FFFB 1 0x200D8 0x7FFFC 1 0x200DF 0x7FFFD 1 0x x7FFFE 1 0x x7FFFF 1 0x12345 in exception handler, OS allocates more stack space OS updates the page table then returns to retry the instruction
18 allocating space on demand 9 note: the space doesn t have to be initially empty only change: load from file, etc. instead of allocating empty page loading program can be merely creating empty page table everything else can be handled in response to page faults no time/space spent loading/allocating unneeded space
19 page tricks generally 10 deliberately make program trigger page/protection fault but don t assume page/protection fault is an error have seperate data structures represent logically allocated memory e.g. addresses 0x7FFF8000 to 0x7FFFFFFFF are the stack might talk about Linux data structures later (book section 9.7) page table is for the hardware and not the OS
20 hardware help for page table tricks 11 information about the address causing the fault e.g. special register with memory address accessed harder alternative: OS disassembles instruction, look at registers (by default) rerun faulting instruction when returning from exception precise exceptions: no side effects from faulting instruction or after e.g. pushq that caused did not change %rsp before fault e.g. instructions reordered after faulting instruction not visible
21 swapping 12 our textbook presents virtual memory to support swapping using disk (or SSD, ) as the next level of the memory hierarchy OS allocates space on disk DRAM is a cache for disk
22 swapping versus caching 13 cache block physical page fully associative every virtual page can be stored in any physical page replacement is managed by the OS normal cache hits happen without OS common case that needs to be fast
23 swapping components 14 swap in a page exactly like allocating on demand! OS gets page fault invalid in page table check where page actually is (from virtual address) read from disk eventually restart process swap out a page OS marks as invalid in the page table(s) copy to disk (if modified)
24 HDD/SDDs are slow 15 HDD reads and writes: milliseconds to tens of milliseconds minimum size: 512 bytes writing tens of kilobytes basically as fast as writing 512 bytes SSD writes and writes: hundreds of microseconds designed for writes/reads of kilobytes (not much smaller)
25 HDD/SDDs are slow 15 HDD reads and writes: milliseconds to tens of milliseconds minimum size: 512 bytes writing tens of kilobytes basically as fast as writing 512 bytes SSD writes and writes: hundreds of microseconds designed for writes/reads of kilobytes (not much smaller)
26 HDD/SDDs are slow 15 HDD reads and writes: milliseconds to tens of milliseconds minimum size: 512 bytes writing tens of kilobytes basically as fast as writing 512 bytes SSD writes and writes: hundreds of microseconds designed for writes/reads of kilobytes (not much smaller)
27 swapping timeline program A pages program B pages page fault program A 16
28 swapping timeline program A pages OS needs to choose page to replace program B pages hopefully copy on disk is already up-to-date? loaded evicted page fault start read program A OS 16
29 swapping timeline program A pages first step of replacement: mark evicted page invalid in page table program B pages loaded evicted page fault start read program A OS 16
30 swapping timeline program A pagesother processes can run while reading pageprogram B pages OS will get interrupt when disk is done loaded evicted page fault start read interrupt program A OS 16
31 swapping timeline program A pages process A s page table updated and restarted from point of fault program B pages loaded evicted page fault start read interrupt program A OS 16
32 swapping decisions 17 write policy replacement policy
33 swapping decisions 18 write policy replacement policy
34 swapping is writeback 19 implementing write-through is hard when fault happens physical page not written when OS resumes process no chance to forward write HW itself doesn t know how to write to disk write-through would also be really slow HDD/SSD perform best if one writes at least a whole page at a time
35 implementing writeback 20 need a dirty bit per page ( was page modified ) often kept in the page table! option 1 (most common): hardware sets dirty bit in page table entry (on write) bit means physical page was modified using this PTE option 2: OS sets page read-only, flips read-only+dirty bit on fault
36 swapping decisions 21 write policy replacement policy
37 replacement policies really matter 22 huge cost for miss on swapping (milliseconds!) many millions of computations on modern processor much much worse than even L3 caches replacement policy implemented in software a lot more room for fancy policies
38 LRU replacement? 23 problem: need to identify when pages are used ideally every single time not practical to do this exactly HW would need to keep a list of when each page was accessed, or SW would need to force every access to trigger a fault
39 approximating LRU 24 one policy: not recently used OS periodically marks all pages as unreadable/writeable when page fault happens: make page accessible again put on list of used pages OS replaces pages not on used list tiebreaker: when was page last on used list?
40 hardware help for not-recently-used 25 hardware usually implements accessed bit in page table entry whenever page is read/written hardware sets this bit (if not set) makes it easier (faster?) for OS to maintain used list OS can periodically scan/clear accessed bit instead of marking pages invalid temporarily construct lists of used pages
41 accessed/dirty bits 26 information about how a page table entry was used indirectly about underlying physical page kept in page table entries themselves
42 accessed/dirty bits 26 information about how a page table entry was used indirectly about underlying physical page kept in page table entries themselves multiple page table entries refer to same page separate valid/accessed bits for each OS needs to consolidate them all
43 mmap 27 Linux/Unix has a function to map a file to memory int file = open("somefile.dat", O_RDWR); // data is region of memory that represents file char *data = mmap(..., file, 0); // read byte 6 from somefile.dat char seventh_char = data[6]; // modifies byte 100 of somefile.dat data[100] = 'x'; // can continue to use 'data' like an array
44 swapping almost mmap 28 access mapped file for first time, read from disk (like swapping when memory was swapped out) write mapped memory, write to disk eventually (like writeback policy in swapping) use dirty bit extra detail: other processes should see changes all accesses to file use same physical memory
45 fast copies 29 Unix mechanism for starting a new process: fork() creates a copy of an entire program! (usually, the copy then calls execve replaces itself with another program) how isn t this really slow?
46 do we really need a complete copy? 30 bash new copy of bash Used by OS Used by OS Stack Stack Heap / other dynamic Writable data Code + Constants Heap / other dynamic Writable data Code + Constants
47 do we really need a complete copy? 30 bash new copy of bash Used by OS Used by OS Stack Stack Heap / other dynamic Heap / other dynamic Writable data Writable data Code + Constants Code + Constants shared as read-only
48 do we really need a complete copy? 30 bash new copy of bash Used by OS Used by OS Stack Stack Heap / other dynamic Heap / other dynamic Writable data Writable data Code + Constants can t be shared? Code + Constants
49 trick for extra sharing 31 sharing writeable data is fine until either process modifies the copy can we detect modifications? trick: tell CPU (via page table) shared part is read-only processor will trigger a fault when it s written
50 copy-on-write and page tables 32 VPN valid? write? physical page 0x x x x x x x x200DF 0x x200AF
51 copy-on-write and page tables 32 VPN valid? write? physical page 0x x x x x x x x200DF 0x x200AF VPN valid? write? physical page 0x x x x x x x x200DF 0x x200AF copy operation actually duplicates page table both processes share all physical pages but marks pages in both copies as read-only
52 copy-on-write and page tables 32 VPN valid? write? physical page 0x x x x x x x x200DF 0x x200AF VPN valid? write? physical page 0x x x x x x x x200DF 0x x200AF when either process tries to write read-only page triggers a fault OS actually copies the page
53 copy-on-write and page tables 32 VPN valid? write? physical page 0x x x x x x x x200DF 0x x200AF VPN valid? write? physical page 0x x x x x x x x200DF 0x x300FD after allocating a copy, OS reruns the write instruction
54 exercise: 64-bit system 33 my desktop: 39-bit physical addresses; 48-bit virtual addresses 4096 byte pages exercise: how many page table entries? 2 48 /2 12 = 2 36 entries exercise: how large are physical page numbers? = 27 bits page table entries are 8 bytes (room for expansion, metadata) would take up 2 39 bytes?? (512GB??)
55 huge page tables 34 huge virtual address spaces! impossible to store PTE for every page how can we save space?
56 holes 35 Used by OS Stack most pages are invalid Heap / other dynamic Writable data Code + Constants
57 saving space 36 basic idea: don t store (most) invalid page table entries use a data structure other than a flat array want a map lookup key (virtual page number), get value (PTE) options?
58 saving space 36 basic idea: don t store (most) invalid page table entries use a data structure other than a flat array want a map lookup key (virtual page number), get value (PTE) options? hashtable actually used by some historical processors but never common
59 saving space 36 basic idea: don t store (most) invalid page table entries use a data structure other than a flat array want a map lookup key (virtual page number), get value (PTE) options? hashtable actually used by some historical processors but never common tree data structure but not quite a search tree
60 search tree tradeoffs 37 lookup usually implemented in hardware lookup should be simple lookup should not involve many memory accesses doing two memory accesses is already very slow
61 two-level page tables two-level page table for pages (16-bit VPN) second-level page tables first-level page table for VPN 0x0-0xFF for VPN 0x100-0x1FF for VPN 0x200-0x2FF for VPN 0x300-0x300 for VPN 0xFF00-0xFFFF PTE for VPN 0x00 PTE for VPN 0x01 PTE for VPN 0x02 PTE for VPN 0x03 PTE for VPN 0xFF actual data for pa (if PTE valid) PTE for VPN 0x300 PTE for VPN 0x301 PTE for VPN 0x302 PTE for VPN 0x303 PTE for VPN 0x3FF 38
62 two-level page tables two-level page table for pages (16-bit VPN) second-level page tables first-level page table for VPN 0x0-0xFF for VPN 0x100-0x1FF for VPN 0x200-0x2FF for VPN 0x300-0x300 for VPN 0xFF00-0xFFFF PTE for VPN 0x00 PTE for VPN 0x01 PTE for VPN 0x02 PTE for VPN 0x03 PTE for VPN 0xFF invalid entries represent big holes PTE for VPN 0x300 PTE for VPN 0x301 PTE for VPN 0x302 PTE for VPN 0x303 PTE for VPN 0x3FF actual data for pa (if PTE valid) 38
63 two-level page tables two-level page table for pages (16-bit VPN) second-level first-level page page tables table actual data for pa PTE for VPN 0x00 physical page # VPN range PTE for valid VPN kernel 0x01 write (if PTE valid) (of next page table) first-level page0x0000-0x00ff table PTE for1 VPN 00x02 1 0x x0100-0x01FF PTE for0 VPN 0x03 for VPN 0x0-0xFF 0 1 0x x0200-0x02FF x00000 for VPN 0x100-0x1FF 0x0300-0x03FF PTE for 1 VPN 1 0xFF 0 0x33454 for VPN 0x200-0x2FF for VPN 0x300-0x300 0x0400-0x04FF PTE 1for VPN 1 0x xFF043 PTE for VPN 0x301 for VPN 0xFF00-0xFFFF 0xFF00-0xFFFF PTE 1for VPN 1 0x xFF045 PTE for VPN 0x303 PTE for VPN 0x3FF 38
64 two-level page tables two-level page table for pages (16-bit VPN) second-level first-level page page tables table actual data for pa PTE for VPN 0x00 physical page # VPN range PTE for valid VPN kernel 0x01 write (if PTE valid) (of next page table) first-level page0x0000-0x00ff table PTE for1 VPN 00x02 1 0x x0100-0x01FF PTE for0 VPN 0x03 for VPN 0x0-0xFF 0 1 0x x0200-0x02FF x00000 for VPN 0x100-0x1FF 0x0300-0x03FF PTE for 1 VPN 1 0xFF 0 0x33454 for VPN 0x200-0x2FF for VPN 0x300-0x300 0x0400-0x04FF PTE 1for VPN 1 0x xFF043 PTE for VPN 0x301 for VPN 0xFF00-0xFFFF 0xFF00-0xFFFF PTE 1for VPN 1 0x xFF045 PTE for VPN 0x303 PTE for VPN 0x3FF 38
65 two-level page tables two-level page table for pages (16-bit VPN) second-level first-level page page tables table actual data for pa PTE for VPN 0x00 physical page # VPN range PTE for valid VPN kernel 0x01 write (if PTE valid) (of next page table) first-level page0x0000-0x00ff table PTE for1 VPN 00x02 1 0x x0100-0x01FF PTE for0 VPN 0x03 for VPN 0x0-0xFF 0 1 0x x0200-0x02FF x00000 for VPN 0x100-0x1FF 0x0300-0x03FF PTE for 1 VPN 1 0xFF 0 0x33454 for VPN 0x200-0x2FF for VPN 0x300-0x300 0x0400-0x04FF PTE 1for VPN 1 0x xFF043 PTE for VPN 0x301 for VPN 0xFF00-0xFFFF 0xFF00-0xFFFF PTE 1for VPN 1 0x xFF045 PTE for VPN 0x303 PTE for VPN 0x3FF 38
66 two-level page tables two-level page table for pages (16-bit VPN) second-level a second-level page tablespage table actual data for pa PTE for VPN 0x00 physical page # VPN PTE for valid VPN kernel 0x01 write (if PTE valid) (of data) first-level page table 0x300 PTE for 1VPN 0x x x301 PTE for 1VPN 0x03 for VPN 0x0-0xFF 1 0 0x4A9DE 0x x5C001 for VPN 0x100-0x1FF 0x303 PTE for 0 VPN 0xFF 0 0 0x00000 for VPN 0x200-0x2FF for VPN 0x300-0x300 0x304 PTE for 1 VPN1 0x3000 0x6C223 PTE for VPN 0x301 for VPN 0xFF00-0xFFFF 0x3FF PTE for 0 VPN0 0x3020 0x00000 PTE for VPN 0x303 PTE for VPN 0x3FF 38
67 two-level page tables two-level page table for pages (16-bit VPN) second-level a second-level page tablespage table actual data for pa PTE for VPN 0x00 physical page # VPN PTE for valid VPN kernel 0x01 write (if PTE valid) (of data) first-level page table 0x300 PTE for 1VPN 0x x x301 PTE for 1VPN 0x03 for VPN 0x0-0xFF 1 0 0x4A9DE 0x x5C001 for VPN 0x100-0x1FF 0x303 PTE for 0 VPN 0xFF 0 0 0x00000 for VPN 0x200-0x2FF for VPN 0x300-0x300 0x304 PTE for 1 VPN1 0x3000 0x6C223 PTE for VPN 0x301 for VPN 0xFF00-0xFFFF 0x3FF PTE for 0 VPN0 0x3020 0x00000 PTE for VPN 0x303 PTE for VPN 0x3FF 38
68 two-level page tables two-level page table for pages (16-bit VPN) second-level page tables first-level page table for VPN 0x0-0xFF for VPN 0x100-0x1FF for VPN 0x200-0x2FF for VPN 0x300-0x300 for VPN 0xFF00-0xFFFF PTE for VPN 0x00 PTE for VPN 0x01 PTE for VPN 0x02 PTE for VPN 0x03 PTE for VPN 0xFF actual data for pa (if PTE valid) PTE for VPN 0x300 PTE for VPN 0x301 PTE for VPN 0x302 PTE for VPN 0x303 PTE for VPN 0x3FF 38
69 two-level page table lookup 39 virtual address VPN split into two parts (one per level)
70 two-level page table lookup 39 page table base register 0x10000 virtual address PTE size +
71 two-level page table lookup page table base register 0x10000 virtual address cause fault? PTE size valid, etc? + 1st PTE addr. split PTE parts data or instruction cache physical address 39
72 two-level page table lookup page table base register 0x10000 virtual address cause fault? PTE size valid, etc? PTE size + 1st PTE addr. split PTE parts page size + 2nd PTE addr. physical address data or instruction cache 39
73 two-level page table lookup page table base register 0x10000 virtual address cause fault? cause fault? PTE size valid, etc? PTE size valid, etc? + 1st PTE addr. split PTE parts page size + 2nd PTE addr. split PTE parts physical address data or instruction cache 39
74 two-level page table lookup page table base register 0x10000 virtual address cause fault? cause fault? PTE size + 1st PTE addr. valid, etc? split PTE parts page size PTE size + 2nd PTE addr. data or instruction cache valid, etc? split PTE parts physical address 39
75 two-level page table lookup page table base register 0x10000 virtual address cause fault? cause fault? PTE size + 1st PTE addr. valid, etc? split PTE parts page size PTE size + 2nd PTE addr. data or instruction cache valid, etc? split PTE parts physical address 39
76 two-level page table lookup page table base register 0x10000 virtual address cause fault? cause fault? PTE size + 1st PTE addr. valid, etc? split PTE parts first-level page table lookup page size PTE size + 2nd PTE addr. data or instruction cache valid, etc? split PTE parts physical address 39
77 two-level page table lookup page table base register 0x10000 virtual address cause fault? cause fault? PTE size + 1st PTE addr. valid, etc? split PTE parts page size PTE size + 2nd PTE addr. data or instruction cache valid, etc? split PTE parts second-level page table lookup physical address 39
78 two-level page table lookup page table base register 0x10000 virtual address cause fault? cause fault? PTE size + 1st PTE addr. valid, etc? split PTE parts first-level page size PTE size + 2nd PTE addr. data or instruction cache valid, etc? split PTE parts second-level physical address 39
79 two-level page table lookup page table base register 0x10000 virtual address cause fault? cause fault? PTE size + 1st PTE addr. valid, etc? split PTE parts page size PTE size + 2nd PTE addr. data or instruction cache valid, etc? split PTE parts physical address 39
80 two-level page table lookup page table base register 0x10000 virtual address cause fault? cause fault? PTE size + 1st PTE addr. valid, etc? split PTE parts page size MMU PTE size + 2nd PTE addr. data or instruction cache valid, etc? split PTE parts physical address 39
81 another view 40 VPN part 1 VPN part 2 page offset first-level page table page table entry page table entry second-level page table physical page page table base register
82 multi-level page tables 41 VPN split into pieces for each level of page table top levels: page table entries point to next page table usually using physical page number of next page table bottom level: page table entry points to destination page validity and permission checks at each level
83 note on VPN splitting 42 textbook labels it VPN 1 and VPN 2 and so on these are parts of the virtual page number (there are not multiple VPNs)
84 splitting addresses for levels 43 x bit physical address; 32-bit virtual address 2 12 byte page size 2-levels of page tables; each page table is one page 4 byte page table entries how is address 0x split up?
85 splitting addresses for levels 43 x bit physical address; 32-bit virtual address 2 12 byte page size 12-bit page offset 2-levels of page tables; each page table is one page 4 byte page table entries how is address 0x split up?
86 splitting addresses for levels 43 x bit physical address; 32-bit virtual address 2 12 byte page size 12-bit page offset 2-levels of page tables; each page table is one page 4 byte page table entries 2 12 /4 = 2 10 PTEs/page table; 10-bit VPN parts how is address 0x split up?
87 splitting addresses for levels x bit physical address; 32-bit virtual address 2 12 byte page size 12-bit page offset 2-levels of page tables; each page table is one page 4 byte page table entries 2 12 /4 = 2 10 PTEs/page table; 10-bit VPN parts how is address 0x split up? 10-bit VPN part 1: (0x48); 10-bit VPN part 2: (0x345); 12-bit page offset: 0x678 43
88 1-level example 6-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 other bits; page table base register 0x20; translate virtual address 0x30 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 CB 0B CB 0B 0x38-B DC 0C DC 0C 0x3C-F EC 0C EC 0C 44
89 1-level example 6-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 other bits; page table base register 0x20; translate virtual address 0x30 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 CB 0B CB 0B 0x38-B DC 0C DC 0C 0x3C-F EC 0C EC 0C 0x30 = PTE addr: 0x = 0x26 PTE value: 0xD6 = PPN 110, valid 1 M[ ] = M[0x30] 44
90 1-level example 6-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 other bits; page table base register 0x20; translate virtual address 0x30 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 CB 0B CB 0B 0x38-B DC 0C DC 0C 0x3C-F EC 0C EC 0C 0x30 = PTE addr: 0x = 0x26 PTE value: 0xD6 = PPN 110, valid 1 M[ ] = M[0x30] 44
91 1-level example 6-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 other bits; page table base register 0x20; translate virtual address 0x30 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 CB 0B CB 0B 0x38-B DC 0C DC 0C 0x3C-F EC 0C EC 0C 0x30 = PTE addr: 0x = 0x26 PTE value: 0xD6 = PPN 110, valid 1 M[ ] = M[0x30] 44
92 2-level example 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused page table base register 0x20; translate virtual address 0x131 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 45
93 2-level example 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused page table base register 0x20; translate virtual address 0x131 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 0x131 = x = 0x24 PTE 1 value: 0xD4 = PPN 110, valid 1 45
94 2-level example 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused page table base register 0x20; translate virtual address 0x131 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 0x131 = x = 0x24 PTE 1 value: 0xD4 = PPN 110, valid 1 PTE 2 addr: = 0x36 PTE 2 value: 0xDB 45
95 2-level example 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused page table base register 0x20; translate virtual address 0x131 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 0x131 = x = 0x24 PTE 1 value: 0xD4 = PPN 110, valid 1 PTE 2 addr: = 0x36 PTE 2 value: 0xDB PPN 110; valid 1 M[ (0x31)] = 0x0A 45
96 2-level example 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused page table base register 0x20; translate virtual address 0x131 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 0x131 = x = 0x24 PTE 1 value: 0xD4 = PPN 110, valid 1 PTE 2 addr: = 0x36 PTE 2 value: 0xDB PPN 110; valid 1 M[ (0x31)] = 0x0A 45
97 2-level example 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused page table base register 0x20; translate virtual address 0x131 physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 0x131 = x = 0x24 PTE 1 value: 0xD4 = PPN 110, valid 1 PTE 2 addr: = 0x36 PTE 2 value: 0xDB PPN 110; valid 1 M[ (0x31)] = 0x0A 45
98 2-level exercise (1) 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused; page table base register 0x08; translate virtual address 0x0FB physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 46
99 2-level exercise (1) 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused; page table base register 0x08; translate virtual address 0x0FB physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 0x0F3 = PTE 1: 0xBB at 0x0B PTE 1: PPN 101 (5) valid 1 PTE 2: 0xF0 at 0x2F PTE 2: PPN 111 (7) valid = 0x3B 0x0C 46
100 2-level exercise (1) 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused; page table base register 0x08; translate virtual address 0x0FB physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 0x0F3 = PTE 1: 0xBB at 0x0B PTE 1: PPN 101 (5) valid 1 PTE 2: 0xF0 at 0x2F PTE 2: PPN 111 (7) valid = 0x3B 0x0C 46
101 2-level exercise (1) 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused; page table base register 0x08; translate virtual address 0x0FB physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 0x0F3 = PTE 1: 0xBB at 0x0B PTE 1: PPN 101 (5) valid 1 PTE 2: 0xF0 at 0x2F PTE 2: PPN 111 (7) valid = 0x3B 0x0C 46
102 2-level exercise (1) 9-bit virtual addresses, 6-bit physical; 8 byte pages, 1 byte PTE page tables 1 page; PTE: 3 bit PPN (MSB), 1 valid bit, 4 unused; page table base register 0x08; translate virtual address 0x0FB physical addresses bytes 0x x x08-B AA BB 0x0C-F CC DD EE FF 0x10-3 1A 2A 3A 4A 0x14-7 1B 2B 3B 4B 0x18-B 1C 2C 3C 4C 0x1C-F 1C 2C 3C 4C physical addresses bytes 0x20-3 D0 D1 D2 D3 0x24-7 D4 D5 D6 D7 0x28-B 89 9A AB BC 0x2C-F CD DE EF F0 0x30-3 BA 0A BA 0A 0x34-7 DB 0B DB 0B 0x38-B EC 0C EC 0C 0x3C-F FC 0C FC 0C 0x0F3 = PTE 1: 0xBB at 0x0B PTE 1: PPN 101 (5) valid 1 PTE 2: 0xF0 at 0x2F PTE 2: PPN 111 (7) valid = 0x3B 0x0C 46
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