Digital System Design Lecture 2: Design. Amir Masoud Gharehbaghi
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1 Digital System Design Lecture 2: Design Amir Masoud Gharehbaghi
2 Table of Contents Design Methodologies Overview of IC Design Flow Hardware Description Languages Brief History of HDLs Sharif University of Technology 2
3 Design Methodologies Ad-hoc Structured Top-Down Bottom-Up Mixed Sharif University of Technology 3
4 Ad-hoc Design Small Scale Designs Come up with a block diagram Place chips on board Wire parts and components Hope or Pray it works Large Scale Designs Partition Design Develop Library Configure Design Test Partial Design Develop More Libraries Configure More Designs... Complete Design Sharif University of Technology 4
5 Why Structured Design? Over a million-transistor designs cannot be done easily Today s designs require better tools Today s designs require better planning Today s designs require better strategy How to manage Step-by-step design Use of Simulation Use of Synthesis Sharif University of Technology 5
6 Design Methodologies (cont.) Top-Down Refine Specification successively Decompose each component into small components Lowest-level primitive components Over-sold methodology - only works with plenty of experience Sharif University of Technology 6
7 Design Methodologies (cont.) Bottom-Up Build-up from primitive components Combined to form more complex components Risk wrong interpretation of specifications Sharif University of Technology 7
8 Design Methodologies (cont.) Mixed Mostly top-down, but also bits of bottom-up Reality: need to know both top level and bottom level constraints Sharif University of Technology 8
9 Overview of IC Design From Concept to Silicon Concept Algorithm Design Verification must be done at each phase Architecture Design Logic/Circuit Design Physical Design Tape-out Sharif University of Technology 9
10 Overview of IC Design (cont.) Concept Novel Idea or Product Concept Algorithm Design Proving Idea Behavior Analysis Algorithm Optimization & Transformations Sharif University of Technology 10
11 Overview of IC Design (cont.) Architecture Design Design of Hardware Components Optimization for Minimum Resource Logic/Circuit Design Design of Hardware Components Tradeoffs among Area/Delay/Power Further Improvements from logic-level to circuit level Sharif University of Technology 11
12 Overview of IC Design (cont.) Physical Design Target to a Foundry Process Layout according to Routing Layers RC Model for Transistors Initial Floorplan Estimate Die Size Estimate Routing Complexity Finial Floorplan Sharif University of Technology 12
13 Overview of IC Design (cont.) Tape-out Fabrication Period Gate Array Routing Layers and Contacts are required Full-Custom or Cell-Based All Masks must be designed A lot of test after manufacturing is needed before design is ready for market Sharif University of Technology 13
14 Overview of IC Design (cont.) Verification Validation of Design in each Phase Formal Simulation Equivalence Checking between two phases Physical Design Verification DRC: Design Rule Check ERC: Electrical Rule Check LVS: Layout vs. Schematic Sharif University of Technology 14
15 Hardware Description Languages (HDLs) Describe Hardware at different levels of abstraction Structural Netlist of modules (hierarchical) Textual replacement of Schematic Behavioral/Functional Describe what module does, not how Use Synthesis to generate Hardware Sharif University of Technology 15
16 HDLs Specifications Timing Concurrency Simulation Semantics Sharif University of Technology 16
17 Why Using HDLs? Very difficult to design directly on hardware Exploring different design options Easier Cheaper Lower time and cost than prototyping CAD support from concept to silicon Sharif University of Technology 17
18 Key Features of HDLs HDLs have high-level programming language constructs HDLs allow designers to describe their designs at different levels of abstraction HDLs allow designers to describe functionality as well as timing HDLs are concurrent languages in nature Sharif University of Technology 18
19 A Brief History of HDLs Sharif University of Technology 19
20 CDL Computer Design Language Developed in 1965 Simulator in 1975 Features: Some high-level statements, condition Simple logical and arithmetic operations Academic language (not industrial) Data-flow level (no hierarchy support) Sharif University of Technology 20
21 ISPS Instruction Set Processor Specification First Idea in 1971 ISPL in 1976 ISPS in 1981 Single level of abstraction Upper than data-flow Processor instruction set No hierarchy support Sharif University of Technology 21
22 AHPL A Hardware Programming Language Three versions: AHPL-I: 1970 AHPL-II: 1978 AHPL-III: 1979 Features: Data-flow and structural level Full EDA tool support Unfamiliar syntax Sharif University of Technology 22
23 VHDL VHSIC HDL: Very High Speed Integrated Circuit Hardware Description Language Initiated by DARPA (research center of DoD) in a workshop in 1981 DARPA documentation released in 1983 VHDL 7.2 released in 1985 ITAR restrictions were lifted from VHDL Sharif University of Technology 23
24 VHDL (cont.) IEEE Standard in 1987 IEEE Std ANSI Standard in 1988 Added Support for RTL Design VITAL: VHDL Initiative Towards ASIC Library Revised version in 1993 IEEE Std Final review added mixed-signal support to VHDL in > VHDL-AMS IEEE Std Sharif University of Technology 24
25 Verilog Verifying Logic Phil Moorby from Gateway Design Automation in 1984 to 1987 Absorbed by Cadence Verilog-XL simulator from GDA in 1986 Synopsis Synthesis Tool in 1988 In 1990 became open language OVI: Open Verilog International Sharif University of Technology 25
26 Verilog (cont.) IEEE Standard in 1995 IEEE Std Last revision in 2001 IEEE Std Ongoing work for adding Mixed-signal constructs: Verilog-AMS System-level constructs: SystemVerilog Sharif University of Technology 26
27 VHDL vs. Verilog All abstraction levels Designed for documentation ADA based constructs NO PLI (Programming Language Interface) All Abstraction Levels Designed for hardware design C and ADA based constructs Powerful PLI Sharif University of Technology 27
28 VHDL vs. Verilog (cont.) Complex Grammar Hard to learn for beginners Describe a system (everything) Lots of data types High-level data types Pointer Alias Easy Language Easy to learn for beginners Describe digital systems Few data types Hardware related types Wire register Sharif University of Technology 28
29 VHDL vs. Verilog (cont.) User-defined package and library Reuse code from package Full design parameterization More easier to handle large designs No user-defined packages Reuse using include Simple parameterization No language construct for design file handling Sharif University of Technology 29
30 VHDL vs. Verilog (cont.) Sharif University of Technology 30
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