Optimal SoC Test Interface for Wafer and Final Tests

Transcription

1 Manusript for of the Korea Test Conferene 1 Optial SoC Test Interfae for Wafer and Final Tests Jaehoon Song, Byeongjin Ki, Kibeo Ki, Minhul Ki and Sungju Park Abstrat The throughput of wafer testing an be signifiantly iproved by allowing ulti-site test through the redued pin ount testing (RPCT. Nonetheless, owing to the redued nuber of test ports with the lengthy test patterns serialized for the RPCT, the throughput of the final test is even degraded. In this paper, an effiient RPCT for wafer test is introdued for syste-on-a-hips (SoC with IEEE 1500 wrapped ores, and then the RPCT is transfored to full pin test interfae for the final pakage test. A atheatially analyzed guideline is provided to adopt the RPCT for SoCs ebedding odules that require too lengthy san test patterns. Experients show the effetiveness of our tehnique in globally iproving the test throughput with an unusual ase where the throughput was even degraded with the RPCT for wafer test. Ⅰ. Introdution Advaned seiondutor tehnologies have ade it possible to design a Syste-on-Chip (SoC whih is an integrated iruit (IC design tehnique integrating all oponents of a syste on a single hip. The tie to design an SoC is redued by using reusable intelletual property (IP odules and the anufaturing ost has dereased with the advaneent in nano-sale proessing tehnology. However, the ost of anufaturing test beoes inreasingly high owing to expensive autoati test equipent (ATE being neessary to apture diverse type of defets arisen fro the high density SoCs. Aordingly, uh effort has been ade by IP providers, SoC integrators, and produt test engineers to redue the test osts. Soe researh has foused on reduing the test appliation tie by opressing the test patterns for various fault odels shifted into the iruit via san hains [1]. Redued pin ount testing (RPCT tehniques have been adopted to redue strutural test osts in a anufaturing environent [-9]. In traditional RPCT, the IC pins for san in/out are ontated along with other lok and ontrol signals, while all funtional I/O pins are aessed via the boundary san hain []. A design-for-test (DFT for I/O delay testing was proposed by ontating very few pads and applying test patterns via the boundary san hain [3]. Beause only a liited nuber of tester pins are onneted to the I/O pads, probles with tester ipedane athed to IC I/O are eliinated, and early detetion of I/O delay defets at wafer level alleviates unneessary pakaging osts. In ost SoCs every digital IC pins beoe ultiplexed with parallel san pins, hene the traditional RPCT is likely to provide not enough gain. Enhaned RPCT, whih ipleent serial/parallel onversion of san data, perits not all san pins to be ontated by the ATE, resulting in substantial iproveent in the throughput for water testing [4]. The RPCT is extended to allow appliation of at-speed test patterns using low ost testers aiding in ulti-site testing onjuntion with test opression tehniques [1]. Siultaneous bidiretional signaling that allows data to ove in both diretions, and a two wire interfae for ouniating JTAG signals between a ontroller and target IC have been developed [5,6]. A high speed redued pin ount JTAG interfae between a JTAG ontroller and target IC was proposed for devie debug operations and also for devie test operations [6]. By testing a wafer die with only four onnetions: two for signals and two for power, the test ost on a probe ard an be signifiantly saved by extending the leaning yles for ontat resistane as well as peritting ore ulti-site test [7]. The throughput of RPCT for both wafer and final tests have been globally and preisely analyzed by onsidering the various effets of test tie, index tie, abort-on-fail and re-test after ontat fails [8]. Although the overall benefit of ulti-site testing for wafer and final tests is learly positive, it is shown that the wafer test interfae for RPCT brings negative ipat to the final test. Analog test wrappers have been developed for effiient aessibility using a digital test aess ehanis, thereby to obviate the need for expensive ixed-signal

2 ATEs as well as to be siply adopted to any RPCT tehnique []. This paper introdues a highly redued pin ount test for an SoC with IEEE 1500 wrapper apable of deteting delay defets. An analysis, taking into aount various paraeters for ATE, probe, and the arhiteture of an SoC, is provided in adopting the RPTC for wafer test. The throughput of wafer test is drastially iproved in RPCT ode while the throughput of final test is not degraded by peritting full pin test, thereby the global test throughput is signifiantly inreased. The rest of this paper is organized as follows. In setion, we briefly review the IEEE 1500 wrapper and introdue a RPCT for wafer test. Final pakage test with axial test hannels is desribed in setion 3 along with the design of test interfae for RPCT and full pin test. Experiental results are presented in setion 4 followed by the onlusion in setion 5. Ⅱ. Highly Redued Pin Count Test for an SoC with IEEE 1500 Wrapper standard does not expliitly speify the aess ehanis, in general the signals fro the IEEE TAP ontroller are siply interfaed with the IEEE WPI [0:] d[0] d[1] d[] d[3] d[4] lk se WSI d[0] d[1] d[] d[3] d[4] se lk san hain 0 san hain 1 WBY WIR WSC WRSTN SeletWIR CaptureWR ShiftWR UpdateWR WRCK q[0] q[1] q[] Fig. 1. Exaple ore and its IEEE 1500 wrapper WPO [0:] q[0] q[1] q[] WSO The IEEE 1500 wrapper onsists of wrapper instrution register (WIR, wrapper bypass register (WBY and wrapper boundary register (WBR. There are two test aess terinals defined. One is andatory wrapper serial port (WSP and the other is wrapper parallel port (WPP. In general, the IEEE TAP ontroller beoes the ain ontrol soure for the ebedded ore test. Fig. 1 shows an exaple of an IEEE 1500 wrapped ore with a san hain [11]. It inludes a parallel test doain through WPI and WPO as well as a serial test doain through WSI and WSO. Aording to different test odes, test paths are diversely reonfigurable using ultiplexers. Depending upon the available san input and output ports, internal san hains an be diretly onneted to external WPI and WPO ports, or indiretly onneted through internal input and output WBRs. San hains are ontrolled by se and lk signals, and Wrapper Serial Control (WSC signals anipulate the IEEE 1500 wrapper instrution, bypass, and boundary registers. Although the IEEE 1500 Ⅲ. Design of Test Interfae for RPCT and Full Pin Test In this setion, the throughputs for both wafer and final tests are evaluated onsidering various effets of ATE, probe, and test patterns. Then a hybrid test interfae supporting RPCT and full pin test is proposed. 1. Estiation of the Test Throughput for Wafer and Final Tests The total test tie spent on SoCs to be tested in parallel is the su of the index tie t i and the test appliation tie t a. The index tie, whose typial value is t i = 0.7s, is the tie to position the probe to ake ontat with the bonding pads of the SoCs under test [8]. The test onsists of a ontat test and a anufaturing test. The probability p of a single terinal to pass the ontat test is referred to as the ontat yield, and typial ontat test tie t = s. The probability p of an

3 Manusript for of the Korea Test Conferene 3 SoC to pass the anufaturing test is referred as the yield, and the anufaturing test tie t depends on the RPCT test interfae, test data volue and SoC internal struture. The total test tie for wafer test an be written as t wt = ti + ta = ti + t + t (1 In high volue prodution testing, the test is aborted as soon as the first failing test vetor is observed. This abort-onfail strategy redues the test tie signifiantly for single site testing, however this positive effet an be faded out in the ulti-site testing as it is unlikely that all n sites will fail siultaneously for the test to be aborted. For the RPCT of k test pins, the ontat probability that at least one SoC will pass the ontat test is for eah target SoC. Therefore, the throughput for wafer test gradually iproves with inreasing test sites, however, the throughput for final test is redued by using the RPCT interfae adopted for wafer test [8]. In this paper, a hybrid SoC test interfae as shown in Fig. is introdued to ahieve axial throughput in final test as well. For wafer test, all the san hains are linked as serial wrapper hain as shown in Fig. 3 to support H-RPCT ode. For final test, san hains are onneted to san test pins to support parallel san testing as shown in Fig. 4. TAM In WPI WSI IEEE 1500 Wrapper IEEE 1500 Wrapper IEEE 1500 Wrapper WPO WSO TAM Out P k n = 1 (1 p ( WSC Glue logi IEEE TAP The probability that at least one SoC will pass the test is written as TDI TRST TMS TCK Fig... Hybrid SoC Test Arhiteture for Wafer and Final Test TDO P n = 1 (1 p (3 WSI san hain san hain WSO all wrapper input ells all san hains all wrapper output ells Hene the total test appliation tie an be desribed as t = t + P P t (4 a Fig 3. RPCT ode : Serial Wrapper Chain san hain(s For the final test, the index tie t i is a funtion of n sites (for SoCs urrently eight sites are available and 18 sites are available for eory testing [8]. In the sequel, the total test tie an be desribed as WPI san hain(s san hain(s Fig4. Full Pin Test ode: Parallel Wrapper Chain WPO t = t ( n + t + t (5 ft i The throughput for wafer and final tests an be estiated as follows; 3600 n D = (6 ( t i + t a In the IEEE 1500 wrapper in Fig. 1, wrapper ells and san hains an be onfigured as shown Fig. 3 or Fig. 4 by setting ultiplexers aording to test odes (wafer test or final test. Two different forats of san test patterns need to be provided for this hybrid test interfae, fully serialized patterns for wafer test, and patterns parallelized to ultiple san hains for final test. The equations illustrate that the throughput is highly dependent on the ontated test pins and test appliation tie. Guideline in Adopting RPCT for Wafer Test Even for wafer test, the throughput ay derease depending upon the test appliation tie, ontat pin ounts, nuber of

4 sites, ontat yield, and anufaturing yield. Certain aspets, suh as the nuber of san hains, the length of san test patterns, and TAM arhiteture are ipliitly involved in estiating the test appliation tie. Aong the different TAM arhitetures naely Daisy hain, Multiplexing, Distributed, and TestRail, in our experient the TestRail interfae, whih in general results in the least test appliation tie, is ipleented on ITC0 benhark iruits [16]. It was observed that by taking the RPCT, the throughput of wafer test is even dereased for the iruit a5867. The test tie for eah odule in two benharks are opared in Fig. 5. Test Tie (# of test loks Test Tie (# of test loks.5e+06.0e E E E E E+09.5E+09.0E E E E E odule < p8 > odule < a5867 > Fig 5. Test Tie for Eah Module in P8 and a5867 It is noted that a5867 ebeds a odule of whih the test appliation tie is partiularly longer than any other benhark SoCs. A guideline is drawn in aking a deision to adopt the RPCT interfae for wafer test. An inequality equation is used suh that the throughput of wafer test with RPCT has to be not less than the throughput with full pin test. ( t i + t t ( t i _ r + t t 3600 n _ r k _ r n _ r (1 (1 p (1 (1 p _ f 3600 n _ f k _ f n _ (1 (1 p f (1 (1 p n _ r n _ f (7 The paraeters n_r, t_r, and k_r indiate the nuber of sites, test appliation tie, and nuber of ontat test pins, respetively in the RPCT. Paraeters n_f, t_f, and k_f indiate the nuber of sites, test appliation tie, and nuber of ontat test pins, respetively in the full pin test. Sine the paraeters t i, t, p, and p keep the sae values for both RPCT and full pin test, ontat pin ounts and test appliation tie are key paraeters taken into aount in adopting RPCT for different SoCs. Espeially test appliation ties t_r and t_f, whih are losely related with the SoC internal arhiteture and DFT, have to be losely looked into for RPCT ipleentation. The effetiveness of the hybrid SoC test interfae is experientally verified in the following setion. Ⅳ. Experiental Results In this paper, a hybrid test interfae tehnique is introdued to perit either RPCT or full pin test to axiize the test throughput for wafer test and final test. A highly redued pin ount test tehnique [9], whih takes only five test pins for SoCs with IEEE 1500 wrapped ores, is adopted for ITC 0 SoC benharks [16] to evaluate the effetiveness of our tehnique. For an ATE with 51 test hannels, hannel utilizations (CU have been estiated in Table 1. After alulating the nuber of hips tested in parallel on the target ATE, the CU for eah SoC is derived by taking ative test hannels against the total hannels. As an be seen fro the last olun of the Table 1, the CU is iproved up to 0.5%. The throughput for wafer test is analyzed in Table, where the ontat yield Y is assued as 1 and anufaturing yield Y as The throughput of H-RPCT is iproved up to 3150%, whereas only for the benhark a5867 the throughput is dereased by 76%. As entioned in the previous setion, various paraeters affeting the throughput ust be preisely analyzed in aking a deision to adopt the RPCT tehnique for wafer test. The throughput of final test is degraded by taking the RPCT interfae as indiated in [8], but the throughput an be sustained by taking full pin test ode in our hybrid test interfae arhiteture. Therefore, the global optiization of the throughput for wafer and final tests an be ahievable with

5 Manusript for of the Korea Test Conferene 5 our tehnique. Table 1. Channel Utilizations of full pin test and RPCT for ATE with 51 hannels SoC Benh- TestRail-Full-Pins H-RPCT arks TPC a b CU d CU CU N S TPC N Ip (% S (% (% u d d h g f q p p p t a a TPC: Test pin ount b N: # of SoCs tested siultaneously (= # of sites CU: Channel Utilization d CU Ip : Iproved Channel Utilization wafer test and final test. In general RPCT is known to be effiient to iprove the throughput for wafer test, however final test is plagued by the RPCT interfae not fully utilizing full pin test apability. In this paper, hybrid test interfae for SoCs is introdued to perit RPCT for wafer test and full pin test for final test. The forat of test vetors needs to be transfored to support serial and parallel appliation aordingly. It was observed that the RPCT does not always iprove the throughput even for wafer test, thereby a atheatial guideline is provided onsidering various paraeters in ATE and SoC. By preisely analyzing SoC test arhiteture and ATE environents, it is believed that our tehnique an ontribute to redue the anufaturing test ost signifiantly. Aknowledgeents Table. Test throughput iproved by adopting the RPCT interfae TestRail-Full- H-RPCT SoC Pins Iprove Benhd (% arks Ns N s throughpu t (Y = 0.95 u d d h g f q p p p t a Ⅳ. Conlusion throughput (Y = In the anufaturing test, test interfae on an SoC and assoiated test vetors are onsistently used throughout This work was supported by grant No. (R (008 fro the Basi Researh Progra of the Korea Siene & Engineering Foundation. Referene [1] J. Jahangiri, N. Mukherjee, C. Wu-Tung, S. Mahadevan, and R. Press, Ahieving High Test Quality with Redued Pin Count Testing, Proeedings of IEEE Asian Test Syposiu, pp , 005 [] H. Hashepour, F. J. Meyer, and F. Lobardi, Analysis and Evaluation of Multisite Testing for VLSI, IEEE Transations on Instruentation and Measureent, Vol. 54, pp , 005 [3] P. Gillis, F. Woytowih, K. MCauley, and U. Baur, Delay Test of Chip I/O Using LSSD Boundary San, Proeedings of IEEE International Test Conferene, pp , 1998 [4] H. Vranken, T. Waayers, H. Fleury, and D. Lelouvier, Enhaned Redued Pin-Count Test for Full-San Design, Proeedings of IEEE International Test Conferene, pp , 001 [5]

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