A Fine Pitch MEMS Probe Card with Built in Active Device for 3D IC Test

Transcription

1 OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached Time (ps) Date: Wednesday Mar. 3, 2010 Time: 14:16:09 V [U3.1 (at pin)] V ol t ag e -mv - A Fine Pitch MEMS Probe Card with Built in Active Device for 3D IC Test Florent Cros Lakshmikanth Namburi Yong Hong Ting Hu Robert Smith ADVANTEST Lakshmi.nambury@advantest.com Gary Maier Van Thanh Truong Hsichang Liu Katsuyuki Sakuma IBM Silicon Valley Test Conference 2013 gmaier@us.ibm.com 1

2 Overview Probe Card Architecture 3D Silicon Technology: Role of Test Probing Challenges & Benefits of Active Probe Card The Probing Solution Test Results Summary Acknowledgements 2

3 Active MEMS Probe Card Architecture IBM Active Si Space Transformer Silicon Space Transformer Wire-bonds Low Force MEMS Probes µc4 bonding (50um Pitch) C4 bonding (150um Pitch) Ceramic Space Transformer Interposer PCB 3

4 Active MEMS Probe Card Challenges and Benefits Examples of current / future Challenges Silicon and Packaging Technology Scaling New Test Insertions and More Test Partitioning Benefits of using an Active Probe Card Mitigate Rising Cost of Test (COT) Extend ATE and Bench Instrumentation Inter-strata In-Out (ISIO) Buffering / Performance Testing Chip to Probe Centric Design for Test (DFT) 4

5 3D Silicon Technology : Test then Stack Why test before stacking? Design verification / Defect isolation Reduces yield loss Enables integration of chips from different suppliers Stack, Then Test, Can be Achievable With Available Technologies Traditional Probe Test, Then Stack, Need for Active Probe Card Active Probe 3d IC C2W or W2W 5 3D IC 3D IC 3d IC Socket or Laminate Tester on chip 3d IC

6 < 15 mm Active MEMS Probe Card Over 1300 IO s 50µm min pitch 5,000 Powers and Grounds Four (4) power planes < 6 mm V93k platform Probe head with Active die and MEMS Probes Top down view of the Active die and MEMS Probes

7 Active MEMS Probe Card Detail of the Active PC, at 50um (minimum) pitch MEMS probes Example of a Fine Pitch MEMS Probe Operating OD: 15µm Scrub Length: 10-15µm Force: 0.2 gf Silicon Valley Test Conference

8 Active MEMS Probe Cross-Section MEMS Probe µc4 Bonding Interconnect µpillars Active Circuitry TSVs SEM: typical cross section of an Active die with MEMS probes 8

9 Low Force MEMS Probe Why MEMS? Wafer Scale manufacturing Lithographic scaling and planarization No probe-count limitations Short probe length for better electrical performance Low Force? Optimized high tip pressure (tip design) and scrubbing action (spring design) to achieve adequate CRES performance. Minimal damage to all test contact surfaces Enables inline product test 25um Example of a scrub mark on a 25um uc4

10 CRES on uc4 Contact resistance on µc4 lead free solder bumps at -10C, 25C, and 85C Examples of Mean CRES* Value per Die, 52 channels, 100mA current: 14µm OD at -10C: <1.8 14µm OD at 25C: <0.6 14µm OD at 85C: <1.5 *CRES each channel = Resistance on bumps (Path + CRes) Resistance on Gold (Path + CRes) 10

11 Functional Testing Wafer Test Flow External IO and Inter-strata IO ( ISIO ) DC Pin Testing Power Supply Shorts and Standby Current Structural ATPG Scan and Logic Test Array Built In Self Test ( ABIST ) Performance Inter-strata Input / Output ( ISIO ) Test 3D Wafer Level edram and ISIO AC Characterization Fmax, Vmin / Vmax Stack Power / Thermal Logic, edram, and ISIO Performance Measurements 11

12 Global Clock Period edram and ISIO Performance Test edram, logic, etc. is 100 % tested through TSV, ISIO, C2C interconnects, Prestack for KGS 400ps FAIL 500ps PASS 600ps 0.8V 0.9V 1.0V 1.1V 1.2V 1.3V V DD Fmax = 2.2 GHz, Vrange =.7v to 1.4v 12 12

13 Dynamic Power and Thermal Monitoring Active Probe Card monitors die Thermal and Power Sensors dynamically Active MEMS Probe enables Very Fast Response Time for Power Switching, Voltage Regulation, and Clock Controls Flexible for Adaptive Test, Sequential Testing, and Chip Test Partitioning Instant Temperature Control by Active Probe Card reducing switching activity Temperature Rise due to high switching activity Example of a thermal 13 map during testing

14 Circuit Delay Change (%) Due to Power Dissipation Performance Variation Localization Performance variation can be quickly measured and isolated with Active MEMS probe measurement systems for AC yield learning at wafer test Chip edram Chip edram Chip edram 14 Relative Location of Performance Sensor/circuitry on the DUT 14

15 Summary Bonded MEMS Probes to a thin Active Die with TSV, attached to a complex space transformer stack to form a fully functional probe card Demonstrated full DC and AC functional testing on 3D chips with 50µm pitch µpillars at the Wafer Level 15

16 Acknowledgements Gary Maier / IBM SRDC project lead, test development Matt Wordeman / IBM Research 3D Circuit Design, Architect Joel Silberman / IBM Research 3D Floor Planning, Physical Design, Simulation Van Thanh Truong / IBM Bromont Packaging, probe BA Luc Guerin / IBM Bromont Packaging, probe BA Thuy Tran Quinn / IBM 3D wafer finishing ( probe, test wafer ) Eric Perfecto / IBM Chip Interconnect development Katsuyuki Sakuma / IBM Packaging, Probe BA R & D Michael Gaynes / IBM Under Fill Research Steve Wright / IBM Probe, SOC, 3D Integration Research Hsiang Liu / IBM Construction Analysis Norman Robson Dan Berger Subu Iyer Robert Smith / AAI Technical Lead Florent Cros / AAI Sr. Manager Process Integration Lakshmikanth Namburi / AAI Sr. Director of R&D Yong Hong / AAI Probe Applications Engineering Manager Ting Hu / AAI Sr. Design Engineer Feng Lo / Lithography Manager Michael Chang / R&D Engineer Shahram Mehdizadeh / Sr. Plating Engineer Jane Tran / Packaging Engineer AAI Manufacturing & Quality Teams Greg Medrick / AAI General Manager, Advanced Probe Cards 16