l Some materials from various sources! Soma 1! l Apply a signal, measure output, compare l 32-bit adder test example:!

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1 Acknowledgements! Introduction and Overview! Mani Soma! l Some materials from various sources! n Dr. Phil Nigh, IBM! n Principles of Testing Electronic Systems by S. Mourad and Y. Zorian! n Essentials of Electronic Testing by M.L. Bushnell and V.D. Agrawal! n Dr. Satnam Singh, Microsoft Research! n VLSI Test Principles and Architectures by L.T. Wang, C.W. Wu and X. Wen! Soma 1! Soma 2! Motivation! l Does the system work?! n design verification issues: functional, timing! n manufacturing test issues! l How much does it cost to test?! l Field service cost and reduction via test! l Product quality enhancement! l Cost of failures: computers, biomedical devices, airplanes, etc.! Test procedure! l Apply a signal, measure output, compare with simulated results or specs! l 32-bit adder test example:! n 2 64 tests = 1.85 x tests! n 1 GHz test speed: 1 test each 1 ns! n test time = 1.85 X sec = years! l Test vector : a specific input/output set! Soma 3! Soma 4! Major digital test issues! l Test time: exponential for exhaustive test! l Test cost: exponential for exhaustive test! l Finite-state machine (FSM) test:! n exponential in terms of number of states! n sequential test issues: depending on past states! l A system works in only one way but fails in numerous ways! Reduction of test cost! l One way is to reduce number of tests! l Select only a subset of tests:! n how to select! n how good is this subset! n how confident is the engineer in discovering all the possible problems! n notion of faults and fault coverage as a measure of test quality! Ø Fault = abstract model of physical failures! Soma 5! Soma 6!

2 Quality of a test set! l How to evaluate the quality of a test set! l Cost of test! n Number of tests! n Some tests are more expensive than others (static vs. at-speed)! l Fault coverage! n Concept of fault simulation! l Tradeoff quality vs. cost! l Exhaustive test! Major types of test! l Pseudo-exhaustive test! n Test subsystems exhaustively, not entire system! n Partitioning methods and interface tests! l Pseudorandom test! l Deterministic test! n Targeting specific faults! l Timing test and other functional tests! l Characterization test! Soma 7! Soma 8! Test generation issues! l Given a system, how to automatically generate tests?! n number of tests, fault coverage, test generation time (algorithm complexity)! n Pseudo-random generation! l Specification-based test generation! l Structure-based test generation! l Parametric test generation (e.g. clock speed test)! Test application issues! l On-line vs. off-line test! n System in use during test: on-line test! l On-chip vs. off-chip test! n Higher bandwidth tests on chip! n Test resource partitioning! l General test system components:! n Fixture: cables, loadboards, connectors! n Hardware: tester, instrumentation! n Software: test algorithms, FFT, etc.! Soma 9! Soma 10! Test application hardware! l Characteristics: speed, bandwidth, signal transition management, timing management, driver electronics, sensor electronics! l Clock speed, number of I/O! l Cost: $2M to $5M for a reasonable test system! l Instrumentation: $20K - $500K (for specific parameters, e.g. clock jitter)! l Types of tests performed: static, at-speed, current-based tests (IDDQ), timing, etc.! Test application software! l Interface with simulation to download test vectors! l Test planning tools! Ø models of pin-electronic drivers/sensors! Ø models of load board, cables, fixtures, etc.! Ø test resources availability! Ø Virtual test software to verify test plan before actual test! l Test development tools! Ø creating test programs for specific testers! l Post-processing for parameter extraction (spectrum, jitter, s-parameters, etc.)! Soma 11! Soma 12!

3 Design and test! Design flow without DFT! l Theoretical vs. experimental issues! l Fast, Cheap, Good: pick any two! l Lack of test planning during design! n Optimizing speed, area, power! l Time-to-market pressure! n Time-to-volume, time-to-money, etc.! l Design-for-test (DFT): add circuits to! n increase product quality! n make test easier and cheaper! n help fault location and diagnosis! Floor Planning Concept RTL Logic Sysnthesis Gate Technology Mapping Layout Mask Data Manufacturing Product Testing Good product l DFT tradeoffs! Soma 13! from Principles of Testing Electronic Systems by S. Mourad and Y. Zorian Soma 14! Libraries Design flow with DFT! low DFT RTL Logic DFT Gate Test Pattern Generation Fault Coverage? high Gate Technology Mapping Layout Parameter Extraction Manufacturing Product Test Application Good Produ ct Libraries DFT: test point insertion! l Simplest DFT methods! l Select test points to help:! n monitor critical signals! n fault diagnosis in case of failures! l How?! n what makes a good test point?! n additional cost of I/O! n multiplexing techniques and trade-offs! from Principles of Testing Electronic Systems by S. Mourad and Y. Zorian Soma 15! Soma 16! l Test generation! CAD tools for test! n combinational logic, memory, etc.! n scan-based systems for sequential logic! n systems automatically synthesized (e.g. Synopsys)! n in-house tools for general test generation! l Virtual test tools (e.g. LabView)! n mainly for test application! CAD tools for test (2)! l Fault simulation tools! l Testability analysis tools! n for test point selection! n to indicate design-for-test additions! l Most commercial tools are somewhat adequate! l In-house tools customized to products! Soma 17! Soma 18!

4 Recent test issues! l Mixed-signal test! n including ADC, DAC, PLL! l Memory test (RAM / ROM)! l Programmable device test (FPGA)! l Parametric test! n device testing and parameter extraction! l RF test (frequency > 5 GHz)! n PLL, transceivers! l Design-for-calibration! l Hardware security! System test issues! l Board test and product test:! n mixed technologies: CMOS, TTL, sensors, etc.! n package effects! n manufacturing problems and quality control! n interface failures! l System-on-a-chip (SOC) test! l Core-based system test! l Test standards for system test:! n IEEE Std (digital), (mixed-signal)! Soma 19! Soma 20! SOC components and test issues! Reliability test! l Working past time t=0.! l Prediction of mean time to failure (MTTF), mean time to repair, mean time before failure, etc.! l Failure mechanisms, field service cost.! l Test types: thermal cycling, mechanical stress, moisture, radiation, etc.! Soma 21! Soma 22! Hardware security! l Offshore fabrication / fabless design houses! l Insertion of malicious circuits! l Infringement of circuit IPs! l Interference during circuit operations! l Methods to ensure hardware security come from test methods! Test economics! l Overall product cost: key factor! l Cost / profit components:! n Time-to-market (design)! n Product performance (design)! n Defect level and yield (test)! n Market delay due to prototype failures (test)! n Cost of test per unit (design and test)! n Cost of failure, repair, etc. (maintenance)! n Quality! Soma 23! Soma 24!

5 Time-to-market economics! from Principles of Testing Electronic Systems by S. Mourad and Y. Zorian Time to Market Loss of Revenues!T Time (Months) Soma 25! Example of test cost! l ATE: GHz, analog instruments,1,024 digital pins! n $1.2M + 1,024 x $3,000 = $4.272M! l Running cost (five-year linear depreciation)! n Depreciation + Maintenance + Operation! n $0.854M + $0.085M + $0.5M = $1.439M/year! l Test cost (24 hour ATE operation)! n $1.439M/(365 x 24 x 3,600) = 4.5 cents/second! l Other examples in test economics materials! Soma 26! Conclusion! l Test is a major process in system design and manufacturing! l Test cost and test problems impact profits! l Need comprehensive and creative approaches:! n DFT balanced between design and test! n Test partitioning! n Reduction of test costs! n Improving overall quality! Soma 27!