Rolling Up Solutions of Wafer Probing Technologies Joey Wu

Transcription

1 Rolling Up Solutions of Wafer Probing Technologies Joey Wu Manager, Global Marketing

2 Drivers of Semiconductor Industry

3 Source: Yole, 2016

4 Source: Yole, 2016

5 Source: Yole, 2016

6 Source: Yole, 2016

7 Form-factor Performance Cost Source: Yole, 2016

8 Demand Drives Resolutions

9 Probe Card Categories, VLSI Defined By Application Memory Non-memory 5 Blade 2 Vertical Needle By Technology 1 Epoxy/ Cantilever Vertical 3 4 Micro-pogo 3D MEMS Advanced MEMS 5 2D MEMS 1 Other Advanced 6 Membrane 6 High Density Cantilever Other

10 Drivers of Wafer Probing Test Industry Performance Parallelism Test, Higher Pin Count. Low Contact Force, High CCC. KGD, KGS. Performance Speed and Frequency, Faster Data Rate. Signal and Power Integrate, PDN. 2 Sided Probing Form factor Finer Pitch, Higher Density Decreasing Pad/Bump size Cost Form Factor Cost Cost of Probe Card (per pin, per card, per Touchdown) Cost of Ownership throughout tests

11 Infrastructures of Probe Development Single Pin Needle Array Full Card Electrical Assistance Tool Probe Analysis System OD OD Checker Station DD Workstation Station Pressure Sensor Real Time Recorder

12 Infrastructures Probe Analysis Contact Gram Force (g) Applied Over Driver (um) Contact Resistance (Ω)

13 Performance Form Factor C.O.O Demand- Fine Pitch LCD Driver Wafer Test Challenge: Output Pin Pitch Gold Bump 4 Rows Staggered: 9/18/27/36

14 Performance Form Factor C.O.O Demand- Fine Pitch Cobra with Enhanced CCC Supporting 80um pitch with 1.5mil Cobra, toward to 50um with 1.0mil Keys: Low Force, Hi-CCC, Lifetime, Parallel Test, CpC$, CpT$... P80um Cobra 80um OD 10% Force Drop

15 Demand- Fine Pitch MEMS Gt-V Performance Form Factor C.O.O Precise probe dimension control, support down to 40um pitch, with consistent probe character, and higher CCC to conventional processes. 36um 24um P80um MEMS Flat Tip Force Curve 80um OD CCC Curve 10% Wedge Point Tip 0 um 80 um 100 u C.C.C. OD 80um Point Tip Lighten Contact Force Higher CCC

16 Performance Form Factor C.O.O Demand Probe Mark Control Typical Buckling Needle Challenges: Predicable probe mark size. Predicable needle contact force. Y X Y/X Ratio

17 To Control Probe Mark Less Lateral Force 3D S F 3D Mask MEMS Process Appearance P 3D Mask 3D Spiral Spiral C

18 To Control Probe Mark Linear d-f Character

19 Performance Form Factor C.O.O Demand Probe Mark Control 3DS MEMS Pogo Y X Y/X Ratio

20 Performance Form Factor C.O.O Demand Probe Mark Control Y X Y/X Ratio 2.0 Cobra Y/X Ratio DS 0.5 Predicable um OD

21 Demand- Time To Market Design Tape-out Wafer Fab. Wafer Test Final Test Challenges: Shortening response time. Rapid engineering run. Design changes. Test coverage approach. Quick, Better, Saving 8~10 WKs 3~4 WKs Design Tape-out Probe Card Mid-Bond Processes 2~3 WKs Probe Card Final Test

22 To Relax Engineering Run Stress Performance Form Factor C.O.O Hand Wired Custom Substrate Universal PCB Guider PH Concerns: Wire count constraint. Hand-wired, time-depend. Slim wire is delicate. Propagation performance... This Way? That Way? either neither how about BOTH? Concerns: Lead time. Cost

23 Performance Form Factor C.O.O To Relax Engineering Run Stress- Flexible MLO Universal PCB Guider PH Customized PCB MLO PH FMLO PH Universal PCB PCB Scale Substrate Wiring Pad Via Thin-Film Scale Chip Pattern Component Pad FMLO (Wafer Site)

24 Performance Form Factor C.O.O To Relax Engineering Run Stress- Flexible MLO ref. on 2k Pin ST FMLO MLO Lead-Time 5WK 9WK Design Change 1WK * 9WK Performance 100 MHz 100 MHz *= Redundancy Ready Widen Soldering Pad Sturdy/Coaxial Wire Closing Components to DUT Universal Mother Board Redundant Routine Design

25 Demand- Extending Package Substrate Value Fact: Thin package substrate of chip can be the interface of probe card. Thickness of Package SB from Customers, MPI 100% 80% t <1 mm Challenges: Thinner Substrate.(0.18mm) Parallelism Test Performance Durability 60% 40% 20% 0% t 2~1 mm t > 2.0 mm

26 Performance Form Factor C.O.O To Extending Package Substrate Value- MSBoC Fact: Multi PKG Substrates on Carrier able to help on your throughput. Saving the wait of make a customize SB. (Typ. 3.0 : 6.5 WKs) Customized PCB MSBoC PH MSBoC PKG SB (C4 Redefined) Ceramic Carrier

27 Performance Form Factor C.O.O MSBoC Mechanical Performance Probing Payload PKG SB PB

28 Performance Form Factor C.O.O MSBoC Electrical Performance PKG ST: Time Data Rate Frequency Domain PKG SB MSBoC-SPI MSBoC ST: Time Data Rate Fact: MSBoC acts similar propagation performance compare to package SB.

29 Summary Performance Form Factor Cost Flexibility Flexibility is to well understand the voice of industry to create breaking tools and extending the value of adapted resources. Believed the solutions will helping chipmakers gain more competitiveness to successes. Thank you!

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