IBM "Broadway" 512Mb GDDR3 Qimonda
|
|
|
- Dayna Mathews
- 6 years ago
- Views:
Transcription
1 ffl Wii architecture ffl Wii components ffl Cracking Open" the Wii 20 1 CMPE112 Spring 2008 A. Di Blas 112 Spring 2008 CMPE Wii Nintendo
2 ffl Architecture very similar to that of the ffl Fully backwards compatible with Game- ffl Approximately 1.5 to 2 times faster than the ffl Few details available 20 3 CMPE112 Spring 2008 A. Di Blas Wii architecture Architecture GameCube Cube. GameCube
3 20 4 CMPE112 Spring 2008 A. Di Blas Wii architecture Wii System architecture Napa ATI "Holliwood" 24MB Mem 1 T SRAM Audio DSP Bluetooth Trans. Broadcom 3MB edram (FB) GPU Vegas I/O, Mem CTRL "Starlet" ARM core (?) IBM "Broadway" PowerPC WiFi Transceiver Broadcom 16 Mbits SDRAM Elpida Video Audio Video Encoder 512Mb GDDR3 Qimonda 4Gb NAND Flash Samsung Optical Disk
4 ffl CPU: PowerPC-based "Broadway" processor, ffl GPU: ATI "Hollywood" GPU, 90 nm CMOS, ffl Broadcom BCM4318 Wi-Fi/Ethernet trans. ffl Broadcom BCM2045 Bluetooth device con- ffl Audio/video Encoder 20 5 CMPE112 Spring 2008 A. Di Blas Wii architecture Wii system blocks: Processors 90 nm SOI CMOS, 729 MHz 243 MHz. MCM module made of 2 chips: Vegas": GPU, 3MB embedded DRAM for memory and framebuffer, I/O and texture memory controller Napa": 24 MB of 1-T SRAM, Audio DSP Starlet": an ARM 926 core (where?) nected via USB (remotes)
5 ffl 24 MB 1T-SRAM integrated into GPU ffl 64 MB "external" GDDR3 SDRAM ffl 3 MB embedded GPU texture memory and framebuffer ffl 512 MB NAND Flash memory 20 6 CMPE112 Spring 2008 A. Di Blas Wii architecture Wii system blocks: Memories
6 20 7 CMPE112 Spring 2008 A. Di Blas Wii components Wii CPU IBM Broadway", evolution of the IBM Gekko" from the GameCube, based on the PowerPC 750CX. Very few official details have been released to the public by Nintendo or IBM. IBM Gekko":
7 ffl PowerPC G3 based 3-way superscalar RISC core at 485 MHz ffl 32-bit Integer unit ffl 64-bit double precision FPU, usable as 2 32-bit SIMD for 1.9 GFLOPS ffl Roughly 50 new SIMD instructions, geared towards 3D graphics ffl 64-bit enhanced 60 bus to GPU/chipset at 162 MHz clock with 1.3 GB/s ffl 64 KB 8-way associative L1 cache (32/32 KB instruction/data). 256 KB ffl 1125 D-MIPS (dhrystone 2.1) ffl 180 nm IBM six layer, copper-wire process. 43 mm die ffl 1.8 V for logic and I/O. 4.9 W dissipation ffl mm PBGA package with 256 pins 20 8 CMPE112 Spring 2008 A. Di Blas Wii components IBM Gekko specs peak bandwidth on-die, 2-way associative L2 cache
8 ffl PowerPC core at 729 MHz, in-order, six-way superscalar One system register unit ffl Bus to main memory: 243 MHz, 64 bits (1.9 GB/s peak) ffl 32-KB 8-way set-associative L1 instruction cache ffl 32-KB 8-way set-associative L1 data cache (up to 16 KB scratch pad) ffl DMA unit with 15-entry DMA request queue ffl Write-gather buffer for writing graphics command lists to the GPU ffl Internal 256-KB 2-way set-associative L2 integrated cache 20 9 CMPE112 Spring 2008 A. Di Blas Wii components IBM Broadway specs Two 32-bit integer units (IU) One FPU: SP, DP, 2xSP. Fixed-point to FP conversion on the fly. One branch unit supports static and dynamic branch prediction. One load/store unit
9 ffl Very few official details have been released by Nintendo, ATI, or IBM. ffl A simple revision of the 162 MHz Nintendo GameCube GPU, just clocked ffl Multi-chip Module (MCM) made of: ffl But also has an embedded ARM 926 core, Starlet CMPE112 Spring 2008 A. Di Blas Wii components Wii GPU: ATI Hollywood" 50% faster Vegas (similar to GameCube Flipper") Napa (similar to GameCube Splash")
10 20 11 CMPE112 Spring 2008 A. Di Blas Wii components Hollywood (and Broadway) under the cover Broadway (left) and Hollywood (right) with Vegas (above) and Napa (below).
11 20 12 CMPE112 Spring 2008 A. Di Blas Wii components Another MCM: Intel's Quad Core Core 2 Extreme
12 ffl Graphics pipeline ffl 3 MB embedded DRAM for textures (same as GC) ffl With 24 MB of external graphics memory (on Napa) (same as GC) ffl I/O and memory controller CMPE112 Spring 2008 A. Di Blas Wii components Wii GPU: Vegas 243 MHz clock (GameCube 162 MHz) Unknown number of vertex and pixel pipelines DirectX 7 with some DirectX 8 extensions Fixed-function pipelines or very limited programmability
13 ffl Hi-speed DRAM, 486 MHz Already used in the GameCube ffl 486 MHz ffl 3.9 GB/s peak bandwidth between Vegas and memory on Napa CMPE112 Spring 2008 A. Di Blas Wii components Wii GPU: Napa 24 MB of 1-T SRAM, from MoSys. About half the size of 6T-SRAM, than half the power. less
14 ffl ARM926 core ffl AES and SHA-1 hardware engines ffl Boot ROM ffl OTP key/hash area CMPE112 Spring 2008 A. Di Blas Wii components Wii GPU: Starlet
15 ffl NAND Flash memory access, filesystem ffl DVD subsystem ffl Authentication (RSA, EC, SHA1, HMAC-SHA1) and ffl USB HCD (generic USB interface), Keyboard driver, Ethernet driver ffl WiFi ffl TCP/IP ffl SD card ffl GPIO (Sensor bar, drive LED, power LED, etc) ffl Audio/Video encoder (I2C) bus CMPE112 Spring 2008 A. Di Blas Wii components Starlet: Functions encryption/decryption (AES, RSA, EC)
16 ffl WiFi = IEEE b Direct Sequence ffl 5-layer TCP/IP model: CMPE112 Spring 2008 A. Di Blas Wii components WiFi/Ethernet chip 5 : Application layer (HTTP, FTP, DHCP, SSH, etc.) Layer 4 : Transport layer (TCP, etc.) Layer 3 : Network/Internet layer (IP, etc.) Layer 2 : Data link layer (WiFi, Ethernet, ATM, Bluetooth, etc.) Layer 1 : Physical layer (Ethernet physical layer, Bluetooth physical Layer RS-232, twisted-pair, etc.) layer,
17 ffl Bluetooth is used for short-distance communication (remotes) ffl Bluetooth = wireless USB ffl WiFi = wireless Ethernet CMPE112 Spring 2008 A. Di Blas Wii components Bluetooth/USB chip
18 ffl Optical Disc Drive (ODD), single and dual layer Wii disks ffl Maximum read speed 7.9 MB/s (DVDx6) ffl 12 cm Wii optical disk: 4.7 GB single layer, 8.5 GB dual layer ffl 8 cm GameCube disk supported ffl DVD video optional CMPE112 Spring 2008 A. Di Blas Wii components Optical disk
19 20 20 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: All parts From TechRepublic.com
20 20 21 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: Top open From TechRepublic.com
21 20 22 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: GameCube connectors From TechRepublic.com
22 20 23 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: WiFi antennas From TechRepublic.com
23 20 24 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: Optical drive From TechRepublic.com
24 20 25 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: Optical drive main chip From TechRepublic.com
25 20 26 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: Motherboard From TechRepublic.com
26 20 27 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: Motherboard without heat sink From TechRepublic.com
27 20 28 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: Other side From TechRepublic.com
28 20 29 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: The NAND flash From TechRepublic.com
29 20 30 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: The audio-video encoder From TechRepublic.com
30 20 31 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: Bluetooth chip From TechRepublic.com
31 20 32 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: The CPU From TechRepublic.com
32 20 33 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: The GPU From TechRepublic.com
33 20 34 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: The GDDR3 From TechRepublic.com
34 20 35 CMPE112 Spring 2008 A. Di Blas Cracking open the Wii Cracking open the Wii: The voltage regulator From TechRepublic.com
This Unit: Putting It All Together. CIS 501 Computer Architecture. What is Computer Architecture? Sources
This Unit: Putting It All Together CIS 501 Computer Architecture Unit 12: Putting It All Together: Anatomy of the XBox 360 Game Console Application OS Compiler Firmware CPU I/O Memory Digital Circuits
Unit 11: Putting it All Together: Anatomy of the XBox 360 Game Console
Computer Architecture Unit 11: Putting it All Together: Anatomy of the XBox 360 Game Console Slides originally developed by Milo Martin & Amir Roth at University of Pennsylvania! Computer Architecture
This Unit: Putting It All Together. CIS 371 Computer Organization and Design. What is Computer Architecture? Sources
This Unit: Putting It All Together CIS 371 Computer Organization and Design Unit 15: Putting It All Together: Anatomy of the XBox 360 Game Console Application OS Compiler Firmware CPU I/O Memory Digital
This Unit: Putting It All Together. CIS 371 Computer Organization and Design. Sources. What is Computer Architecture?
This Unit: Putting It All Together CIS 371 Computer Organization and Design Unit 15: Putting It All Together: Anatomy of the XBox 360 Game Console Application OS Compiler Firmware CPU I/O Memory Digital
Evolution of CPUs & Memory in Video Game Consoles. Curtis Geiger & Matthew Meehan
Evolution of CPUs & Memory in Video Game Consoles Curtis Geiger & Matthew Meehan 1 ST GENERATION Magnavox Odyssey first console, released 1972 No CPU or Memory entirely made up of transistors, resistors,
Xbox 360 Architecture. Lennard Streat Samuel Echefu
Xbox 360 Architecture Lennard Streat Samuel Echefu Overview Introduction Hardware Overview CPU Architecture GPU Architecture Comparison Against Competing Technologies Implications of Technology Introduction
CONSOLE ARCHITECTURE
CONSOLE ARCHITECTURE Introduction Part 1 What is a console? Console components Differences between consoles and PCs Benefits of console development The development environment Console game design What
Kevin Meehan Stephen Moskal Computer Architecture Winter 2012 Dr. Shaaban
Kevin Meehan Stephen Moskal Computer Architecture Winter 2012 Dr. Shaaban Contents Raspberry Pi Foundation Raspberry Pi overview & specs ARM11 overview ARM11 cache, pipeline, branch prediction ARM11 vs.
EyeCheck Smart Cameras
EyeCheck Smart Cameras 2 3 EyeCheck 9xx & 1xxx series Technical data Memory: DDR RAM 128 MB FLASH 128 MB Interfaces: Ethernet (LAN) RS422, RS232 (not EC900, EC910, EC1000, EC1010) EtherNet / IP PROFINET
Embedded Systems: Architecture
Embedded Systems: Architecture Jinkyu Jeong (Jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu)
Computer Architecture. Introduction. Lynn Choi Korea University
Computer Architecture Introduction Lynn Choi Korea University Class Information Lecturer Prof. Lynn Choi, School of Electrical Eng. Phone: 3290-3249, 공학관 411, lchoi@korea.ac.kr, TA: 윤창현 / 신동욱, 3290-3896,
EMBEDDED HARDWARE. Core Board. ARM7 Development board. ARM7 Evaluation Board. Page 1 of 5
Core Board * Size: 71.2mm *50.8mm * Industrial grade 32-bit RISC micro-controller * Mass storage device support * Industrial grade 16C550 Serial Interface * 10/100M Industrial Ethernet interface * USB
PowerPC TM 970: First in a new family of 64-bit high performance PowerPC processors
PowerPC TM 970: First in a new family of 64-bit high performance PowerPC processors Peter Sandon Senior PowerPC Processor Architect IBM Microelectronics All information in these materials is subject to
Quick Reference Card. Timing and Stack Verifiers Supported Platforms. SCADE Suite 6.3
Timing and Stack Verifiers Supported Platforms SCADE Suite 6.3 About Timing and Stack Verifiers supported platforms Timing and Stack Verifiers Supported Platforms SCADE Suite Timing Verifier and SCADE
Original PlayStation: no vector processing or floating point support. Photorealism at the core of design strategy
Competitors using generic parts Performance benefits to be had for custom design Original PlayStation: no vector processing or floating point support Geometry issues Photorealism at the core of design
Multimedia in Mobile Phones. Architectures and Trends Lund
Multimedia in Mobile Phones Architectures and Trends Lund 091124 Presentation Henrik Ohlsson Contact: henrik.h.ohlsson@stericsson.com Working with multimedia hardware (graphics and displays) at ST- Ericsson
Hardware Overview. Steve Rabin Senior Software Engineer Software Development Support Group
Hardware Overview Steve Rabin Senior Software Engineer Software Development Support Group Agenda Platform goals System architecture CPU, GPU, memory, audio, disc Briefly Wii Remote and Nunchuk WiiConnect24
A Closer Look at the Epiphany IV 28nm 64 core Coprocessor. Andreas Olofsson PEGPUM 2013
A Closer Look at the Epiphany IV 28nm 64 core Coprocessor Andreas Olofsson PEGPUM 2013 1 Adapteva Achieves 3 World Firsts 1. First processor company to reach 50 GFLOPS/W 3. First semiconductor company
System Configuration Guide
System Guide Technical Specification Model number Processor Chipset Memory Internal HDD/SSD Type Mountable memory Maximum size Error detection/correction Number of slots Mountable HDD Maximum size Maximum
registers data 1 registers MEMORY ADDRESS on-chip cache off-chip cache main memory: real address space part of virtual addr. sp.
Cache associativity Cache and performance 12 1 CMPE110 Spring 2005 A. Di Blas 110 Spring 2005 CMPE Cache Direct-mapped cache Reads and writes Textbook Edition: 7.1 to 7.3 Second Third Edition: 7.1 to 7.3
Spring 2011 Prof. Hyesoon Kim
Spring 2011 Prof. Hyesoon Kim PowerPC-base Core @3.2GHz 1 VMX vector unit per core 512KB L2 cache 7 x SPE @3.2GHz 7 x 128b 128 SIMD GPRs 7 x 256KB SRAM for SPE 1 of 8 SPEs reserved for redundancy total
Introduction to the Personal Computer
Introduction to the Personal Computer 2.1 Describe a computer system A computer system consists of hardware and software components. Hardware is the physical equipment such as the case, storage drives,
Intelop. *As new IP blocks become available, please contact the factory for the latest updated info.
A FPGA based development platform as part of an EDK is available to target intelop provided IPs or other standard IPs. The platform with Virtex-4 FX12 Evaluation Kit provides a complete hardware environment
1. Microprocessor Architectures. 1.1 Intel 1.2 Motorola
1. Microprocessor Architectures 1.1 Intel 1.2 Motorola 1.1 Intel The Early Intel Microprocessors The first microprocessor to appear in the market was the Intel 4004, a 4-bit data bus device. This device
SoC Platforms and CPU Cores
SoC Platforms and CPU Cores COE838: Systems on Chip Design http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University
DevKit7000 Evaluation Kit
DevKit7000 Evaluation Kit Samsung S5PV210 Processor based on 1GHz ARM Cortex-A8 core Onboard 512MByte DDR2 and 512MByte NAND Flash 4 UART, 4 USB Host, USB Device, Ethernet, Audio, TF, RTC,... Supports
ECE 571 Advanced Microprocessor-Based Design Lecture 20
ECE 571 Advanced Microprocessor-Based Design Lecture 20 Vince Weaver http://www.eece.maine.edu/~vweaver vincent.weaver@maine.edu 12 April 2016 Project/HW Reminder Homework #9 was posted 1 Raspberry Pi
ECE 571 Advanced Microprocessor-Based Design Lecture 18
ECE 571 Advanced Microprocessor-Based Design Lecture 18 Vince Weaver http://www.eece.maine.edu/ vweaver vincent.weaver@maine.edu 11 November 2014 Homework #4 comments Project/HW Reminder 1 Stuff from Last
PowerPC 740 and 750
368 floating-point registers. A reorder buffer with 16 elements is used as well to support speculative execution. The register file has 12 ports. Although instructions can be executed out-of-order, in-order
AT-501 Cortex-A5 System On Module Product Brief
AT-501 Cortex-A5 System On Module Product Brief 1. Scope The following document provides a brief description of the AT-501 System on Module (SOM) its features and ordering options. For more details please
1. AMD Ryzen 2nd Generation processors 2. AMD Ryzen with Radeon Vega Graphics processors 3. AMD Ryzen 1st Generation processors
CPU AM4 Socket: 1. AMD Ryzen 2nd Generation processors 2. AMD Ryzen with Radeon Vega Graphics processors 3. AMD Ryzen 1st Generation processors (Please refer "CPU Support List" for more information.) Chipset
Gamecube Hacking. 1. Gamecube Hardware - what you can read everywhere. 2. Gamecube Hardware - a bit more details
Gamecube Hacking 1. Gamecube Hardware - what you can read everywhere 2. Gamecube Hardware - a bit more details 3. Homebrew - how to get your code to the cube 4. The boot process (and how to hack it) 5.
3U CompactPCI Intel SBCs F14, F15, F17, F18, F19P
3U CompactPCI Intel SBCs F14, F15, F17, F18, F19P High computing and graphics performance with forward compatibility for a wide range of industrial applications. 1 Content Processor roadmap Technical data
SA-1500: A 300 MHz RISC CPU with Attached Media Processor*
and Bridges Division SA-1500: A 300 MHz RISC CPU with Attached Media Processor* Prashant P. Gandhi, Ph.D. and Bridges Division Computing Enhancement Group Intel Corporation Santa Clara, CA 95052 Prashant.Gandhi@intel.com
UMBC. Rubini and Corbet, Linux Device Drivers, 2nd Edition, O Reilly. Systems Design and Programming
Systems Design and Programming Instructor: Professor Jim Plusquellic Text: Barry B. Brey, The Intel Microprocessors, 8086/8088, 80186/80188, 80286, 80386, 80486, Pentium and Pentium Pro Processor Architecture,
PRODUCT PREVIEW TNETV1050 IP PHONE PROCESSOR. description
C55x DSP Operating at 125 MHz, Providing up to 250 MIPS MIPS32 4KEc 32-Bit RISC Processor, Operating at 165 MHz, Providing up to 223 Dhrystone MIPS On-Chip Peripherals Include: External Memory Interface
ECE 471 Embedded Systems Lecture 3
ECE 471 Embedded Systems Lecture 3 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 10 September 2018 Announcements New classroom: Stevens 365 HW#1 was posted, due Friday Reminder:
CPU AM4 Socket: 1. AMD Ryzen processor. (Please refer "CPU Support List" for more information.) Chipset 1. AMD X470. Memory
CPU AM4 Socket: 1. AMD Ryzen processor (Please refer "CPU Support List" for more information.) Chipset 1. AMD X470 Memory 1. 4 x DDR4 DIMM sockets supporting up to 64 GB of system memory 2. Dual channel
Product Technical Brief S3C2412 Rev 2.2, Apr. 2006
Product Technical Brief S3C2412 Rev 2.2, Apr. 2006 Overview SAMSUNG's S3C2412 is a Derivative product of S3C2410A. S3C2412 is designed to provide hand-held devices and general applications with cost-effective,
LabSim Mapping Matrix
LabSim Mapping Matrix A+ Guide to Hardware Managing, Maintaining, and Troubleshooting Fourth Edition (220-601) Mapping: Chapters to LabSims Chapter Page Number LabSim Chapter 1 Pages 2-3 Pages 3-6 Pages
TABLE OF CONTENTS 1. INTRODUCTION 1.1. PREFACE KEY FEATURES PERFORMANCE LIST BLOCK DIAGRAM...
Table of Contents TABLE OF CONTENTS 1. INTRODUCTION 1.1. PREFACE... 1-1 1.2. KEY FEATURES... 1-1 1.3. PERFORMANCE LIST... 1-3 1.4. BLOCK DIAGRAM... 1-4 1.5. INTRODUCE THE PCI - BUS... 1-5 1.6. FEATURES...
Parallel Computing: Parallel Architectures Jin, Hai
Parallel Computing: Parallel Architectures Jin, Hai School of Computer Science and Technology Huazhong University of Science and Technology Peripherals Computer Central Processing Unit Main Memory Computer
KeyStone C66x Multicore SoC Overview. Dec, 2011
KeyStone C66x Multicore SoC Overview Dec, 011 Outline Multicore Challenge KeyStone Architecture Reminder About KeyStone Solution Challenge Before KeyStone Multicore performance degradation Lack of efficient
Introduction to Microprocessor
Introduction to Microprocessor Slide 1 Microprocessor A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic device That reads binary instructions from a storage device
(Please refer "CPU Support List" for more information.)
CPU 1. Support for Intel Core X series processors in the LGA2066 package 2. L3 cache varies with CPU (Please refer "CPU Support List" for more information.) Chipset 1. Intel X299 Express Chipset Memory
Computer Systems Architecture I. CSE 560M Lecture 19 Prof. Patrick Crowley
Computer Systems Architecture I CSE 560M Lecture 19 Prof. Patrick Crowley Plan for Today Announcement No lecture next Wednesday (Thanksgiving holiday) Take Home Final Exam Available Dec 7 Due via email
FriendlyARM. Mini2440.
FriendlyARM Mini2440 www.friendlyarm.net 1 Introduction...3 1.1 Features...4 2 Hardware Resource...6 2.1 Jumpers and Interfaces...6 2.2 Memory Map...7 2.2.1 Memory Adress Allocation...7 2.3 Power Supply...8
Raspberry Pi 3 Model B
Raspberry Pi 3 Model B Product Name Raspberry Pi 3 Product Description The Raspberry Pi 3 Model B is the third generation Raspberry Pi. This powerful credit-card sized single board computer can be used
Course Introduction. Purpose: Objectives: Content: Learning Time:
Course Introduction Purpose: This course provides an overview of the Renesas SuperH series of 32-bit RISC processors, especially the microcontrollers in the SH-2 and SH-2A series Objectives: Learn the
PERFORMANCE MEASUREMENT
Administrivia CMSC 411 Computer Systems Architecture Lecture 3 Performance Measurement and Reliability Homework problems for Unit 1 posted today due next Thursday, 2/12 Start reading Appendix C Basic Pipelining
Cannon Mountain Dr Longmont, CO LS6410 Hardware Design Perspective
LS6410 Hardware Design Perspective 1. S3C6410 Introduction The S3C6410X is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, lowpower capabilities, high performance Application
Digital Circuits Part 2 - Communication
Introductory Medical Device Prototyping Digital Circuits Part 2 - Communication, http://saliterman.umn.edu/ Department of Biomedical Engineering, University of Minnesota Topics Microcontrollers Memory
PCM-9584 Onboard Intel Pentium M EBX SBC with Audio, VGA 2LVDS and LAN
PCM-9584 Onboard Intel Pentium M EBX SBC with Audio, VGA 2LVDS and LAN Packing List Before you begin installing your card, please make sure that the following materials have been shipped: 1 PCM-9584 all-in-one
PRODUCT SPECIFICATION
A P P E N D I X A PRODUCT SPECIFICATION A-1 Processor Core Logic Processor and Core Logic Mobile Intel Pentium M (Banias), 1.5GHz-1.6GHz, 1 MB L2 with Error Correction Code, or Mobile Intel Pentium M (Dothan),
CS Computer Architecture Spring Lecture 01: Introduction
CS 35101 Computer Architecture Spring 2008 Lecture 01: Introduction Created by Shannon Steinfadt Indicates slide was adapted from :Kevin Schaffer*, Mary Jane Irwinº, and from Computer Organization and
Prod. Order No.: PO-XXXXXXXA. I. Identification. II. Configuration. Processor(s) Case Color: New Background. System Memory
Page 1 of 7 Prod. Order No.: PO-XXXXXXXA I. Identification Customer Name: XXXXXXXXX Customer Account. No.: XXX15 II. Configuration Processor(s) Processor 1 Name: Intel(R) Pentium(R) 4 CPU 3.40GHz Manufacturer:
Intel released new technology call P6P
P6 and IA-64 8086 released on 1978 Pentium release on 1993 8086 has upgrade by Pipeline, Super scalar, Clock frequency, Cache and so on But 8086 has limit, Hard to improve efficiency Intel released new
CS 16: Assembly Language Programming for the IBM PC and Compatibles
CS 16: Assembly Language Programming for the IBM PC and Compatibles Discuss the general concepts Look at IA-32 processor architecture and memory management Dive into 64-bit processors Explore the components
HP PA-8000 RISC CPU. A High Performance Out-of-Order Processor
The A High Performance Out-of-Order Processor Hot Chips VIII IEEE Computer Society Stanford University August 19, 1996 Hewlett-Packard Company Engineering Systems Lab - Fort Collins, CO - Cupertino, CA
CMSC 411 Computer Systems Architecture Lecture 2 Trends in Technology. Moore s Law: 2X transistors / year
CMSC 411 Computer Systems Architecture Lecture 2 Trends in Technology Moore s Law: 2X transistors / year Cramming More Components onto Integrated Circuits Gordon Moore, Electronics, 1965 # on transistors
Age nda. Intel PXA27x Processor Family: An Applications Processor for Phone and PDA applications
Intel PXA27x Processor Family: An Applications Processor for Phone and PDA applications N.C. Paver PhD Architect Intel Corporation Hot Chips 16 August 2004 Age nda Overview of the Intel PXA27X processor
Unit 2: Technology Systems. Computer and technology systems
Unit 2: Technology Systems Computer and technology systems So far Introduction Applications in different industries Issues Sustainability Privacy and copyright Networking Today Learning aim B: Understand
ECE 471 Embedded Systems Lecture 2
ECE 471 Embedded Systems Lecture 2 Vince Weaver http://web.eece.maine.edu/~vweaver vincent.weaver@maine.edu 7 September 2018 Announcements Reminder: The class notes are posted to the website. HW#1 will
Hi3536 H.265 Decoder Processor. Brief Data Sheet. Issue 03. Date
Hi3536 H.265 Decoder Processor Brief Data Sheet Issue 03 Date 2015-04-19 . 2014. All rights reserved. No part of this document may be reproduced or transmitted in any form or by any means without prior
Detailed specifications - ThinkCentre M57 (type 6019, 6066, 6072, 6077, 6087, 9181/ M57p (type 6064, 6067, 6073, 6078, 6088, and 9196)
Страница 1 Detailed specifications - ThinkCentre M57 (type 6019, 6066, 6072, 6077, 6087, 9181/ M57p (type 6064, 6067, 6073, 6078, 6088, and 9196) Applicable countries and regions Architecture Communications
TQ2440 Development Platform Manual
TQ2440 Development Platform Manual 0 Directory Directory... 1 Chapter 1 Introduction... 7 11Appearance of TQ2440 development platform... 7 12Hardware resource of TQ2440... 7 13Software introduction of
Product Technical Brief S3C2413 Rev 2.2, Apr. 2006
Product Technical Brief Rev 2.2, Apr. 2006 Overview SAMSUNG's is a Derivative product of S3C2410A. is designed to provide hand-held devices and general applications with cost-effective, low-power, and
F28HS Hardware-Software Interface: Systems Programming
F28HS Hardware-Software Interface: Systems Programming Hans-Wolfgang Loidl School of Mathematical and Computer Sciences, Heriot-Watt University, Edinburgh Semester 2 2017/18 0 No proprietary software has
IoT Project Proposals
IoT Project Proposals 1 Submit before 31 st March Best 5 proposals will be given Intel Galileo Gen 2 microcontroller boards each 2 Advisory Board will evaluate and select the best project proposals Dr.
The Processor That Don't Cost a Thing
The Processor That Don't Cost a Thing Peter Hsu, Ph.D. Peter Hsu Consulting, Inc. http://cs.wisc.edu/~peterhsu DRAM+Processor Commercial demand Heat stiffling industry's growth Heat density limits small
TABLE OF CONTENTS 1. INTRODUCTION 2. SPECIFICATION 3. HARDWARE INSTALLATION 6EM 1.1. PREFACE KEY FEATURES PERFORMANCE LIST...
6EM TABLE OF CONTENTS 1. INTRODUCTION 1.1. PREFACE...1-1 1.2. KEY FEATURES...1-1 1.3. PERFORMANCE LIST...1-2 1.4. BLOCK DIAGRAM...1-3 1.5. INTRODUCE THE Pentium II Processor & AGP...1-4 1.6 What is AGP?...1-6
IOT-GATE-iMX7 Datasheet
IOT-GATE-iMX7 Datasheet Industrial Internet of Things Gateway Product Specification v.1.3 Capable, compact, affordable: i.mx7 Dual IoT-Gate has been designed to answer demanding IoT application requirements
Advanced Topics In Hardware
Advanced Topics In Hardware You will learn the inner workings of the hardware components introduced in the previous section. Computer Buses: How Information Is Transmitted Carries information between the
FUNCTIONS OF COMPONENTS OF A PERSONAL COMPUTER
FUNCTIONS OF COMPONENTS OF A PERSONAL COMPUTER Components of a personal computer - Summary Computer Case aluminium casing to store all components. Motherboard Central Processor Unit (CPU) Power supply
Technical Specifications
Technical s 6 NOTE: Offerings may vary by region. The following specifications are only those required by law to ship with your computer. For comprehensive specification of your computer go to s section
2D/3D Graphics Accelerator for Mobile Multimedia Applications. Ramchan Woo, Sohn, Seong-Jun Song, Young-Don
RAMP-IV: A Low-Power and High-Performance 2D/3D Graphics Accelerator for Mobile Multimedia Applications Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae,, and Hoi-Jun Yoo oratory Dept. of EECS,
Product Specifications. Shuttle Barebone D10. Self-reliant with a 7 touchscreen display. Feature Highlight.
Self-reliant with a 7 touchscreen display A new touchscreen display integrated into the panel is the revolutionary option for the management of multimedia content and applications. Your finger replaces
TABLE OF CONTENTS 1. INTRODUCTION 2. SPECIFICATION 3. HARDWARE INSTALLATION 6EX 1.1. PREFACE KEY FEATURES PERFORMANCE LIST...
6EX TABLE OF CONTENTS 1. INTRODUCTION 1.1. PREFACE...1-1 1.2. KEY FEATURES...1-1 1.3. PERFORMANCE LIST...1-2 1.4. BLOCK DIAGRAM...1-3 1.5. INTRODUCE THE Pentium II Processor & AGP...1-4 1.6 What is AGP?...
NPE-300 and NPE-400 Overview
CHAPTER 3 This chapter describes the network processing engine (NPE) models NPE-300 and NPE-400 and contains the following sections: Supported Platforms, page 3-1 Software Requirements, page 3-1 NPE-300
PXA270 EPIC Computer with Power Over Ethernet & Six Serial Protocols SBC4670
PXA270 EPIC Computer with Power Over Ethernet & Six Serial Protocols SBC4670 Features RoHS 520MHz Low-power ARM processor w/ 800 x 600 Color LCD Power Over Ethernet and 10/100BASE-T Ethernet GPS module
Memory Systems IRAM. Principle of IRAM
Memory Systems 165 other devices of the module will be in the Standby state (which is the primary state of all RDRAM devices) or another state with low-power consumption. The RDRAM devices provide several
Product Series SoC Solutions Product Series 2016
Product Series Why SPI? or We will discuss why Serial Flash chips are used in many products. What are the advantages and some of the disadvantages. We will explore how SoC Solutions SPI and QSPI IP Cores
Technology in Action. Chapter Topics. Participation Question. Participation Question. Participation Question 8/8/11
Technology in Action Chapter 6 Understanding and Assessing Hardware: Evaluating Your System 1 Chapter Topics To buy or to upgrade? Evaluating your system CPU RAM Storage devices Video card Sound card System
Introduction to Sitara AM437x Processors
Introduction to Sitara AM437x Processors AM437x: Highly integrated, scalable platform with enhanced industrial communications and security AM4376 AM4378 Software Key Features AM4372 AM4377 High-performance
Anatomy of AMD s TeraScale Graphics Engine
Anatomy of AMD s TeraScale Graphics Engine Mike Houston Design Goals Focus on Efficiency f(perf/watt, Perf/$) Scale up processing power and AA performance Target >2x previous generation Enhance stream
A 50Mvertices/s Graphics Processor with Fixed-Point Programmable Vertex Shader for Mobile Applications
A 50Mvertices/s Graphics Processor with Fixed-Point Programmable Vertex Shader for Mobile Applications Ju-Ho Sohn, Jeong-Ho Woo, Min-Wuk Lee, Hye-Jung Kim, Ramchan Woo, Hoi-Jun Yoo Semiconductor System
systems such as Linux (real time application interface Linux included). The unified 32-
1.0 INTRODUCTION The TC1130 is a highly integrated controller combining a Memory Management Unit (MMU) and a Floating Point Unit (FPU) on one chip. Thanks to the MMU, this member of the 32-bit TriCoreTM
Product Technical Brief S3C2416 May 2008
Product Technical Brief S3C2416 May 2008 Overview SAMSUNG's S3C2416 is a 32/16-bit RISC cost-effective, low power, high performance micro-processor solution for general applications including the GPS Navigation
CS/COE0447: Computer Organization
CS/COE0447: Computer Organization and Assembly Language Terminology and Concepts Sangyeun Cho Dept. of Computer Science Five classic components I am like a control tower I am like a pack of file folders
registers data 1 registers MEMORY ADDRESS on-chip cache off-chip cache main memory: real address space part of virtual addr. sp.
13 1 CMPE110 Computer Architecture, Winter 2009 Andrea Di Blas 110 Winter 2009 CMPE Cache Direct-mapped cache Reads and writes Cache associativity Cache and performance Textbook Edition: 7.1 to 7.3 Third
ID 730L: Getting Started with Multimedia Programming on Linux on SH7724
ID 730L: Getting Started with Multimedia Programming on Linux on SH7724 Global Edge Ian Carvalho Architect 14 October 2010 Version 1.0 Mr. Ian Carvalho System Architect, Global Edge Software Ltd. Responsible
COSC 6385 Computer Architecture - Memory Hierarchies (III)
COSC 6385 Computer Architecture - Memory Hierarchies (III) Edgar Gabriel Spring 2014 Memory Technology Performance metrics Latency problems handled through caches Bandwidth main concern for main memory
C900 PowerPC G4+ Rugged 3U CompactPCI SBC
C900 PowerPC G4+ Rugged 3U CompactPCI SBC Rugged 3U CompactPCI SBC PICMG 2.0, Rev. 3.0 Compliant G4+ PowerPC 7447A/7448 Processor @ 1.1 Ghz with AltiVec Technology Marvell MV64460 Discovery TM III System
STM32F429 Overview. Steve Miller STMicroelectronics, MMS Applications Team October 26 th 2015
STM32F429 Overview Steve Miller STMicroelectronics, MMS Applications Team October 26 th 2015 Today - STM32 portfolio positioning 2 More than 30 product lines High-performance 398 CoreMark 120 MHz 150 DMIPS
M-606 Linux ARM9 Single Board Computer User Guide
M-606 Linux ARM9 Single Board Computer User Guide Version 1.0 Copyright Artila Electronics Co., Ltd. All Rights Reserved. Table of Contents 1. Introduction... 1 1.1 Features... 1 1.2 Packing List... 1
PROJECT 4 Architecture Review of the Nintendo GameCube TM CPU. Ross P. Davis CDA5155 Sec /06/2003
PROJECT 4 Architecture Review of the Nintendo GameCube TM CPU Ross P. Davis CDA5155 Sec. 7233 08/06/2003 Introduction In this report, statements or sets of consecutive statements will be backed up by stating
Smartwatches (April 12, 2017) Samsung Gear Live, 2014 Samsung S 3G, 2014 Samsung S3 LTE, November 2016
Smartwatches (April 12, 2017) Samsung Gear Live, 2014 Samsung S 3G, 2014 Samsung S3 LTE, November 2016 1 Samsung Gear Live 2 Samsung Gear Live 1.63 Super AMOLED display with a resolution of 320 x 320 pixels
LeopardBoard Hardware Guide Rev. 1.0
LeopardBoard with VGA Camera Board LeopardBoard Hardware Guide Rev. 1.0 April 5, 2009 Page 1 LeopardBoard.org provides the enclosed product(s) under the following conditions: This evaluation kit is intended
Discretes and MultiMarket ICs DMI BL Power 07/08/2002
Discretes and MultiMarket ICs DMI BL Power 07/08/2002 Sony, Playstation, Nintendo, Gamecube, Microsoft and Xbox are trademarks and property of their respective owners. ASPD / page:2 Technical CPU: Sony
FCQ2 - P2020 QorIQ implementation
Formation P2020 QorIQ implementation: This course covers NXP QorIQ P2010 and P2020 - Processeurs PowerPC: NXP Power CPUs FCQ2 - P2020 QorIQ implementation This course covers NXP QorIQ P2010 and P2020 Objectives