Product Series SoC Solutions Product Series 2016

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1 Product Series

2 Why SPI? or We will discuss why Serial Flash chips are used in many products. What are the advantages and some of the disadvantages. We will explore how SoC Solutions SPI and QSPI IP Cores can be used with SPI / QSPI Flash Memories in microprocessor based SOCs and systems.

3 About Us System on Chip (SOC) Silicon IP and Integration Company Based in Georgia, USA Incorporated in 2000 Specializing in AMBA based AXI and AHB Subsystems Targeting the IoT, M2M and low power/performance device markets Thorough knowledge of ARM Cortex-M0, M3, A5, Dual A9 as well as similar processors from other CPU vendors. Developed ARM based SOCs for over 25 years 1 st ARM design was with VLSI Technology in 1988

4 Why Flash? Microprocessor based SOCs need Flash On-chip Flash is expensive or un-available in the process technology On-chip SRAM is volatile and expensive Often need larger memory for program images Non-volatile Boot source Need Flash Loader program / methodology Why Serial Flash or Why SPI?

5 SPI Flash Enabled Products

6 Serial Flash Advantages Fewer Pins Easy to use Lower power Scalability Wide range of Memory Densities Common footprints allow upgrades without PCB re-layout Less Expensive Product Cost Reduced PCB real estate Smaller devices. Simpler routing Faster acquisition with Dual, Quad and Octal modes Quad and Octal devices balance good performance with power efficiency Clock rates are now typically > 100Mhz.

7 Serial Flash Advantages Flash Throughput (MBytes/S) Parallel Serial bit 16 bit 32 bit single dual quad octal * Based on 90ns access time * Based on 80Mhz serial clock rate

8 Serial Flash Disadvantages Smaller Memory sizes compared to Parallel Flash Programming time is typically longer However, serial Flash has smaller sectors Needs a SPI protocol to read or program Often done in software Requires 2 serial transactions in order to read data word Address word + data word Sometimes requires mode changes between functions Such as reading the ID versus reading Quad Data

9 Typical IoT Chip JTAG Cache or CCM Cortex M3 / M4 (or similar) Interrupt Ctrl FPU Low power / Performance Subsystem SSRAM SSRAM Analog or Mixed Signal PMU DMA Controller MEM Ctrl MEM Ctrl Ethernet MAC Ethernet Phy AHB Multi-matrix SPI,I2C, or UART AHB - APB Bridge Timers SHA, AES, TDES Encryption GPIO APB Bus Watchdog QSPI (XIP) SPI Comm ADC IF 24 bit precision High precision ADC Piezo Vibration Sensor QSPI Flash

10 SOC Advantages using QSPI Lower Power 4 to 8 IO compared to > 32 for parallel flash Large Non-volatile memory source Up to 512M compared to very limited on chip flash Reduced ASIC / SOC IC cost Fewer bond pads = smaller die Cheaper packages Reduced assembly cost Smaller package footprint Good for small embedded products, SIPs or modules

11 QSPI Solutions

12 QSPI IP Core AHB Bus XIP_EN XIP_CFG_* AHB Slave Interface aux_*_status XIP Logic XIP_EN Registers XIP_EN_REQ RX FIFO Up to 256 TX FIFO Up to 256 XIP_EN_OUT master Master Serializer RX SREG TX SREG 4 sclkout ssout (sdatain) sdataoutenmn master sdataout dmaclr dmabreq dmasreq intreq enable DMA Interface Interrupt Control Slave Serializer TX SREG RX SREG 4 4 (sdatain) sdataoutensn extsclkm Master SCLK Generator master HCLK sclkin ssin

13 QSPI Features Features: AMBA AHB or AXI interface Execute-in-place (XIP) functionality for industry-standard Flash device 4 bit to 32 bit serial transmit & receive Software programmable Master or Slave mode Software programmable Master SCLK rate Quad, Dual and Single-bit mode operation Configurable Transmit and Receive FIFOs (up to 256 words) Up to 4 slaves under Master control DMA interface More

14 General Functionality

15 General Functionality

16 QUAD Transaction

17 AHB Execute In Place (XIP) Looks like an Addressable Memory IPC-QSPI-XIP-AHB Core HRDATA Receive FIFO RX Serializer MISO Microprocessor HADDR Execute in Place Finite State Machine MOSI Handles Single and Burst Reads

18 Execute In Place (XIP) Allows AHB or AXI Master to directly read contents from industrystandard Serial Flash devices. Winbond, Macronix, Spansion, and Micron XIP Finite State Machine: Converts AHB read transactions to SPI protocol and transactions needed to read data from Serial Flash. Data Look-ahead (pseudo cache) Reads data in 32bit chucks and continues until the Rx FIFO is half full. If transaction is a burst access then the next FIFO data is read. If transaction is a non-sequential or single access then the FIFO is flushed after the read.

19 Software Support QSPI Boot Loader Copies Flash image to internal SRAM then re-boots Out of the box for Cortex-M0/M3 Mostly C-Code with small amount of Assembly Examples for other processors QSPI Flash Loader Writes an image to external Serial Flash The image is loaded via JTAG or UART to internal SRAM then paged to Flash Handles paging the image

20 What s next?

21 It s Here Already!!! Octal SPI with DTR 8 serial channels to support the industry-standard Octal Flash Parts Double Transfer Rate (DTR) 2x throughput Micron, Macronix, Spansion and Winbond

22 It s Here Already!!! AHB Bus dtr_en AHB Register Interface aux_*_status AHB XIP Interface XIP_EN Registers XIP_CFG_* XIP_EN_REQ RX FIFO 16 x 32 TX FIFO 16 x 40 XIP_EN_OUT Serializer RX SREG TX SREG 90 deg. phase shift 8 dtr_en sclkout ssout (sdatain) sdataout sdataoutenmn dmaclr dmabreq dmasreq enable DMA Interface Interrupt Control DTR Rx Serializer 90 deg. phase shift sdataindqs 2 intreq extsclkm RX SREG (sdatain) 8

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