Getting Started with FPGA Design

Transcription

1 Getting Started with FPGA Design Summary Tutorial TU0116 (v1.3) April 13, 2005 This tutorial gives an overview of how to create an FPGA design. It outlines how to create a schematic and then compile, synthesize, build and program the Xilinx Spartan IIE chip on the daughterboard of the Altium NanoBoard. We will also look briefly at the use of sub sheets and VHDL files in an FPGA design. This tutorial is a very simple circuit design which allows the tutorial to focus on the overall process. It does not attempt to demonstrate the powerful mixed schematic/vhdl high-level design capabilities available in the software. For more sophisticated designs, refer to the many examples in the \Altium2004\Examples folders. The \FPGA Hardware folder has a number of designs that do not include processors (including the mixed schematic/vhdl multi-channel LED chaser). The \FPGA Processors folder and the \Reference Designs folder include processor-based FPGA designs, some that demonstrate a simple feature and others that implement an entire digital system. Before starting the tutorial, connect the NanoBoard to the parallel port of your PC and power up the board by flicking the ON switch. Make sure you have installed the Xilinx tools (web edition) which downloaded from the Xilinx website ( The example used in this tutorial is a Johnson Counter, shown in Figure 1. It can be found in the folder Altium2004\Examples\Tutorials\Getting started with FPGA Design in your Altium Designer installation directory. Refer to this example at any time to get further insight or skip some of the steps. It is important to note that schematic concepts for digital designs under Altium Designer can be different to PCB design concepts. A rule that needs to be explicitly followed when designing FPGAs may not be true for PCB. A Johnson Counter, or twisted ring counter, is a synchronous counter where the inverted output of the last flip-flop is connected to the input of the first flip-flop. When run, this Johnson counter design will light up the LEDs sequentially one digit at a time on the NanoBoard. A clock delay will be included later in the schematic to slow down the LED display, so that the counter can be seen to shift from left to right or right to left. TU0116 (v1.3) April 13,

2 Figure 1. Johnson Counter schematic Creating an FPGA Project To start working with Altium Designer, you first need a project. A project makes managing your source design documents and any generated outputs much easier. For digital FPGA designs, we need to create an FPGA project. To create a new FPGA project: 1. Select File» New» Project» FPGA Project from the menus, or click on Blank Project (FPGA) in the New section of the Files panel. If this panel is not displayed, click on the Files tab. 2. The Projects panel displays a new project file, FPGA_Project1.PrjFpg. 3. Rename the new project file (with a.prjfpg extension) by selecting File» Save Project As. Navigate to where you want to save the project on your hard disk, type the name Johnson_Counter.PrjFpg in the File Name field and click on Save. It is essential that you use underscores ( _ ) rather than spaces in project and document filenames to avoid synthesis errors later in the design flow. Next, we will create a schematic for the design of the Johnson Counter to add to our project file. Creating a Schematic source document Warning: Do not use spaces or dashes (-) in file names or project names. Use underscores if necessary. An FPGA project supports two types of source documents schematic and VHDL. You can mix both types of documents in a project with the use of sheet symbols. However, for FPGA projects, a schematic must be used for the top level document of your project. This is so Vendor FPGA-PCB integration can be supported. 2 TU0116 (v1.3) April 13, 2005

3 The design includes some delay circuitry to slow down the LED display on the NanoBoard. Initially we will create just one schematic sheet for the Johnson counter. Then we will move the delay circuitry to a sub-sheet to show an example of using a hierarchical structure. Finally, we will replace this sub sheet with a VHDL file. To create a single schematic document for the Johnson Counter: You can mix VHDL and Schematic documents with the use of sheet symbols. In the case of VHDL, the sheet entries correspond to the ports of the VHDL document. 1. Select File» New» Schematic, or click on Schematic Sheet in the New section of the Files panel. A blank schematic sheet named Sheet1.SchDoc displays in the design window. 2. Rename the new schematic file (with a.schdoc extension) by selecting File» Save As. Navigate to where you wish to store the schematic on your hard disk, type the name Johnson_Counter.SchDoc in the File Name field and click on Save. Placing parts on the schematic The components we will need for this schematic can be found in a generic integrated library, \Program Files\Altium2004\Library\FPGA\FPGA Generic.IntLib. This library is installed and available from the Libraries panel by default. Generic FPGA library components can be used in any of the target FPGA devices that this system supports. While there are special integrated libraries (*FPGA.INTLIB) available with vendor primitives (available by manufacturer in the \Program Files\Altium2004\Library folder), these are targeted for a specific device, so using them would prevent design portability; use only if really necessary for your design. Refer to the Building an Integrated Library tutorial in the Library Management book (online) for more information about finding and using integrated libraries. Now, let s start designing the schematic for our Johnson Counter. 1. Select FPGA Generic.IntLib from the drop-down list in the Libraries panel. 2. Find the component SR8CLEDB in the Libraries panel. You can browse the Libraries panel by either navigating through the list or typing the name SR8CLEDB (or part of the name) in the Masks edit box below the library name. Select the component in the list and click the Place SR8CLEDB button or simply drag the selected Component Name onto the schematic sheet. 2. You should notice that your cursor now has the component attached to it. Move the cursor into the schematic workspace if you don t see it. Place the component by clicking on the appropriate position on the schematic. Do not worry about setting the correct designators for these components as we will annotate the design later. 3. We also need to use a 8-Bit input bus (J8B_8S), six inverters (INV), one OR gate (OR2N2S) and two flip-flops (FJKC) in our design. Repeat the above steps to place these components as shown in Figure 2. TU0116 (v1.3) April 13,

4 4. We also require some ports that interface with the plug-ins on the NanoBoard. These are located in the FPGA NanoBoard Port-Plugin.IntLib, also a default library available from the Libraries panel. Place DIPSWITCH, TEST_BUTTON, CLOCK_REFERENCE and LED from this library as shown Figure 2 below. Note that these components have a visible parameter named PinNumberDisplay that initially reads as PXX for each pin. When the design is synthesized later in the tutorial, these parameters will be updated to display the pin numbers that these nets connect to on the target FPGA. Figure 2. Johnson Counter schematic with parts placed. 5. Finally, add designators to the design using Tools» Quiet Annotate or Tools» Force Annotate All. Designators will be automatically added to all the components in this schematic. Adding Power Ports Place two GND power ports for ground. 1. Select Place» Power Port or click on the GND icon in the Wiring toolbar. 2. Press TAB to display the Power Port properties dialog. Make sure the Net is set to GND and choose the style Bar from the Style drop-down list. Click OK and place the GND ports. 3. Right-click, or press ESC, to exit placement mode. 4. We also need to add a ground bus power port to the D[7..0] pin of the SR8CLEDB component. Click on the VCC Bus Power Port button in the Wiring Toolbar. Press TAB to display the Power Port properties dialog, change the Net name to GNDBUS[..] and check the Style is set to Bar. Click OK and press the Spacebar to rotate the symbol as you place it. Creating connections We have placed all the components and ports, so now it s time to wire them all together. There are two ways to wire your schematic, explicitly or implicitly. Explicit wiring creates a connection by having a physical wire connecting your two net objects together. Implicit wiring creates a connection from the use of wires and net labels, i.e. connection is implied if two wires share the same net label but are not actually physically connected. 4 TU0116 (v1.3) April 13, 2005

5 Our design will need both wires and buses. Let s place the wires first. Remember not to confuse wires with lines; wires are for connecting and lines are for drawing. 1. To place a wire, select Place» Wire [shortcut P, W] and click on the point on the schematic where you want to start placing (usually at a port or a component pin). Move the cursor to the next point you want your wire segment to connect to and click again. Continue until you have made a connection to another port or component pin. Continue wiring and rightclick, or press ESC, to exit wire placement mode. 2. Wire up the schematic as shown in Figure 3 below, taking careful note of the junctions where wires cross in this schematic. If two wires cross and a junction is present, a connection between these two wires is implied. If there is no junction, there is no connection. In this schematic, auto junctions will occur where wires connect. Ensure your connection is valid when attaching your wires to other wires, component pins and ports. If the cursor turns to a red crosshair over the object you wan t to connect to, then there is valid connection if yo u place a node of the wire there. Figure 3. The Johnson Counter schematic wired up. Naming the connections All the wiring done above is explicit and therefore, technically, no net labels are required. However, it is always a good idea to net label all your connections as it will make your design easier to understand and makes tracking down problems and referencing easier. To net label your connections: 1. Select Place» Net Label [shortcut P, N]. A dotted box will appear floating on the cursor. 2. To edit the net label before it is placed, press the TAB key to display the Net Label dialog. Type the net name in the Net field, e.g. LEFT. Click OK. 3. Place the net label so that the bottom left of the net label (its hotspot ) touches the wire you want to label. The cursor will change to a red cross when the net label touches the wire. 4. Label the other nets. The diagram below gives an indication where the net labels should be placed. They need not be named exactly as shown in Figure 4, as long as they are unique. Right-click or press ESC to exit net label placement mode. TU0116 (v1.3) April 13,

6 Figure 4. The Johnson Counter schematic with net labels added. Using Buses Altium Designer supports the complex use of buses for FPGA designs. Buses can be used to specify not just a group of signals but how each signal in the bus is mapped to its endpoints. When using buses, it is important to remember that you always need to net label any disjoint bus segment. It is also useful to note that a connection from a bus to another object is always resolved from left to right and the bus size of both objects in a connection must be the same. To connect the LED port to SR8CLEDB, we will create bus SQ[7..0] as shown in Figure 5. Schematic infers buses by names. If a net label ends with a number it groups all such net labels together to form an inferred bus for digital designs. This does not apply to ports where such grouping is not desirable. 1. Place a bus by selecting Place» Bus [shortcut P, B] and place the bus, using the same placement technique used when placing a wire. Figure 5. Adding buses and bus entries. 6 TU0116 (v1.3) April 13, 2005

7 2. Place a net label called SQ[7..0] on the bus. Always net label your buses. A bus without a net label even when it is explicitly connected is very ambiguous because there is no net label to clearly specify how each element of the bus is connected to its endpoints. 3. Next, we will add in the bus entries as shown in Figure 5. Select Place» Bus Entry [shortcut P, U] and place the bus entries from wires SQ0 and SQ7 to the SQ[7..0] bus. Use the SPACEBAR while placing to rotate the bus entry, if necessary. Right-click, or press ESC, to exit placement mode. 4. Add another bus to connect the DIP switch port to the J8B_8S part (as shown in Figure 6). Figure 6. Connecting the DIP switch port to J8B_8S using a bus. 5. Save the schematic and save the project. Checking the design A very common mistake is to use a bus style net label (i.e. [ ] ) on a wire. This will not work in Altium Designer, as only buses may have bus style net labels placed on them. Before we proceed with creating a sub sheet for the clock divider, let s check that the schematic is going to plan by compiling the project and running the electrical and graphical checks set in the Error Checking tab of the Options for FPGA Project dialog (Project» Project Options). 1. Select Project» Compile FPGA Project [project_name]. Any Error or Fatal Error messages will automatically appear in the Messages panel. 2. Warnings will also be listed in the Messages panel but you must manually display the panel by clicking on the System tab at the bottom of the design window and selecting Messages (or select View» Workspace Panels» System» Messages from the menus). 3. Double-click on any error message in the Messages panel to display more information about the error in the Compile Errors dialog. The offending entity will be zoomed into and highlighted in the schematic. 4. Resolve any errors and re-compile the project to check. Save the schematic and project file. Configuring your design We have finished designing our Johnson counter, so now we need to specify which FPGA chip we want to use in our design, e.g. the Xilinx Spartan IIE XC2S300E-6PQ208C chip on the NanoBoard daughterboard. We will add a configuration and constraint files to do this. The Constraint file will determine the pin numbering and the device name to be used by the FPGA chip on the NanoBoard. 1. Select Project» Configuration Manager. The Configuration Manager for project dialog appears. Click on the Add button in the Configurations section of the dialog and type a configuration name in TU0116 (v1.3) April 13,

8 the New Configuration Name dialog, e.g. NB_SpartanIIE, and click OK. Configuration names should relate to the target implementation for easy identification. 2. Add a Constraints file to your configuration by clicking on the Add button in the Constraints section and select NB1_6_XC2S300E-6PQ208.Constraint in the Choose Constraint files to add to Project dialog. Constraint files are found in the Altium2004\Library\FPGA folder. Click Open. 3. Select the configuration checkbox back in the Configuration Manager dialog and click OK. 4. A folder named Settings is added to the project and shows the constraint file used in the Constraints Files folder. 5. Save the project file. Targeting the Altera Cyclone device If you are targeting the supplied Altera Cyclone chip, carefully plug it into place on the NanoBoard. 1. Add a new configuration file (Project» Configuration Manager) named, e.g. Altera, to the FPGA project. 2. Add the supplied Altera Constraints file, C:\Program Files\Altium2004\Library\Fpga\NB1_6_EP1C12Q240.Constraint. Make sure the Altera configuration is selected. 3. Proceed to the next section on Using the Devices view to program the FPGA. For more information about configurations and constraints, refer to the Design Portability, Configurations and Constraints article and the Re-targeting the design to the production board application note in the FPGA Hardware Design book (online). We have now finished configuring the Johnson Counter design and it is ready for implementation in an FPGA. The remainder of the design process can take place in the Devices view. Using the Devices view to program the FPGA The Devices view (View» Devices View) allows you to follow through the workflow (from left to right) required to send your program to the FPGA. In this view, you can: Compile the project (and check for errors) Synthesize (create an EDIF netlist) Build (e.g. translate the EDIF files, map the design to the FPGA, Place and Route the FPGA, run a Timing Analysis and then Make the Bit File that can then be used to program the FPGA) Program FPGA (download the bit file to the daughter board s FPGA chip, e.g. the Xilinx Spartan IIE). 8 TU0116 (v1.3) April 13, 2005

9 When this workflow is completed, you will be able to run the program by flicking on and off the DIP switches on the NanoBoard. To download your Johnson Counter design to the FPGA: 1. Make sure your NanoBoard is properly connected and switched on. In the Devices view, click on the Live button and check that the Connected indicator is green. 2. In the Devices view, click on Compile. The red indicator will turn green when a successful compilation takes place. If any error messages display in the Messages panel, go back to your schematics, correct any errors, save the files and recompile. 3. Click on Synthesize. If the synthesis is completed successfully, a folder called Generated [config_name] is created which holds the generated EDIF, VHDL and synthesis log file. The configuration which is used in this example, which we named Johnson, will display in the Devices view underneath the Spartan IIE icon. During synthesis, the source documents are translated into intermediate VHDL files which are then synthesized into EDIF, suitable for vendor Place & Route tools. Errors detected during synthesis are based on errors in the intermediate files, so go back to the source files to fix any problems. Doubleclick on an error in the Messages panel to see the fault in the source documents and intermediary VHDL. You can run all stages of the workflow up to and including the current stage by clicking on the arrow icon located on the left side of the stage button, e.g. clicking on this icon on the Program FPGA button will run all previous stages first. 4. Click on Build. This will step through several processes to ultimately make the Bit file that can be downloaded to the FPGA. You will see the buttons next to the various processes turn green as they are successfully completed. The Build button will turn green when all necessary processes are completed and the Results Summary dialog appears. Click on Close to close the dialog. (The Make PROM File process is not required for this example.) Display the Output panel to view more vendor-related feedback. TU0116 (v1.3) April 13,

10 5. Click on Program FPGA to download the bit file to the daughterboard s Spartan chip. 6. When the Program FPGA process is completed, you will be able to run the program by flicking on and off the following DIP switches on the NanoBoard: switch 1 to display the LEDs shifting to the left switch 2 to display the LEDs shifting to the right switch 3 to end the program. Press the Test/Reset button below the LEDs to reset the program. 7. You will notice that the LEDs are flashing at the same time, which really defeats the purpose of having a Johnson counter! This is because the clock is set at 50MHz by default. We need to slow down the clock by one million times to see the LEDs displaying sequentially. We will add clock dividers to the schematic after we have checked that the program is OK using the Hard Devices instrument. Checking the LEDs using the Hard Devices instrument You can also check that the program is running correctly by looking at the Hard Devices panel of the Instrument Rack. This instrument displays the LEDs by pin number when the program is running. This display does not rely on the NanoBoard s clock and so lower frequencies are not required to see the LEDs displaying in sequence. 1. Double-click on the Spartan-IIE icon in the Hard Devices section of the Devices view. The Instrument Rack Hard Devices appears. 2. Click on the Live Update checkbox. 10 TU0116 (v1.3) April 13, 2005

11 3. Scroll down to display Pin Number P56. The LED icons will light up next to the LED ports as the program is run. Adding a sub sheet for the clock divider Since the NanoBoard clock is running at 50MHz by default, we will need to add six clock dividers which divide by 10 (CDIV10DC50 50% duty cycle version) to the Johnson Counter schematic to slow down the LED display. We will create the clock divider sub-circuit as a sub-sheet to demonstrate how hierarchical designs can be used when programming an FPGA. 1. Open Johnson_Counter.SchDoc and place a sheet symbol to represent the sub sheet we will use for the clock dividers (see Figure 7). Select Place» Sheet Symbol. Press TAB while placing and type in the designator name, e.g. U_Clock_divider and the filename, e.g. Clock_divider.SchDoc, in the Properties tab of the Sheet Symbol dialog. Click OK to close the dialog, then click to position the sheet symbol and click to size it. 2. Add sheet entries named CLK_REF and CLK_OUT to the sheet symbol (Place» Add Sheet Entry) with Input and Output I/O types respectively. Figure 7. Johnson_Counter schematic with sheet symbol for Clock_divider sub sheet placed. 3. Create a sub sheet by selecting Design» Create Sheet from Symbol. Position the cursor over the new sheet symbol and click. Click on No in the Confirm dialog as we do not want to reverse input/output directions. The new schematic document is created and opens displaying the CLK_REF and CLK_OUT ports which have been automatically added. TU0116 (v1.3) April 13,

12 4. Now place six clock divider parts, CDIV10DC50, from the FPGA Generic.IntLib, as shown in Figure 8 below. Once again, do not worry about setting the designators; simply place the parts and select Tools» Annotate Quiet when completed. Figure 8. Clock_divider.SchDoc with placed parts and ports. 5. Save the schematic and project files. 6. Recompile the design to check for any errors. Fix any errors and save. 7. After compiling, you can check the sheet hierarchy of the project by looking in the Projects panel; the project now recognizes the sub-sheet (Clock_divider.SchDoc) as a child of the Johnson_Counter schematic. 8. Go to the Devices view and reprogram the FPGA to see the LED display slowed down enough that it is now seen to be counting from right to left (DIP switch 1) or from left to right (DIP switch 2). Adding a VHDL file for the clock divider Now we will substitute a VHDL file for the clock divider schematic sub sheet in the FPGA project. This VHDL file will slow down the clock rate by one million. The VHDL file is linked to the schematic through the use of a sheet symbol. 1. Add the VHDL file to the project by right-clicking on the FPGA project name in the Projects panel and select Add Existing to Project. Select the VHDL file, Clock_divider.VHD from the Choose Documents to Add to Project dialog. This file is available from the Altium2004\Examples\Tutorials\Getting started with FPGA Design folder. If you were creating the VHDL file from scratch, right-click on the FPGA project name and select Add New to Project» VHDL Document, type in the following code shown in Figure 9 and save the document. 12 TU0116 (v1.3) April 13, 2005

13 Figure 9. Clock_divider.VHD. 2. Next we will create a sheet symbol from the new VHDL file to replace the one that references the schematic sub-sheet Clock_divider.schdoc. With the Johnson_Counter.SchDoc schematic open, create a new sheet symbol by selecting Design» Create Sheet Symbol from Sheet. Select Clock_divider.VHD from the Choose Document to Place dialog and click OK. The sheet symbol appears floating on the cursor. Press TAB to display its Sheet Symbol properties dialog. Click on the Parameters tab to check that the VHDLEntity parameter has been added. Make sure the Visible option is selected and click OK. Click to place the sheet symbol on the Johnson_Counter schematic, just underneath the sheet symbol for Clock_divider.schdoc. If the VHDL file contains multiple entites, the VHDLENTITY parameter specifies which entity you want to instantiate. TU0116 (v1.3) April 13,

14 3. Delete the sheet symbol for Clock_divider.schdoc and move the new sheet symbol for Clock_divider.VHD into its place on the schematic. Make sure the wires connect properly. Figure 10. Clock_divider.VHD sheet symbol placed. 4. Save the schematic document. 5. Remove the Clock_divider.schdoc file from the FPGA project by right-clicking on the document name in the Projects panel and selecting Remove from Project. It is no longer required now that the VHDL file has been added. Save the FPGA project file. 6. Finally, to check that the clock is being slowed down by the delay in the VHDL file, go to the Devices view (View» Devices) and click on Program FPGA to run all the stages of compilation, synthesis, building and programming the FPGA chip. If the FPGA is successfully programmed, you should be able to run the Johnson Counter using the switches as before. 14 TU0116 (v1.3) April 13, 2005

15 Revision History Date Version No. Revision 16-Jan New product release 23-Sep Clock divider components updated 18-Jan Components in Johnson_Counter.SchDoc updated. 13-Apr Updated for Altium Designer Software, hardware, documentation and related materials: Copyright 2005 Altium Limited. All rights reserved. You are permitted to print this document provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, Altium Designer, CAMtastic, Design Explorer, DXP, LiveDesign, NanoBoard, NanoTalk, Nexar, nvisage, P-CAD, Protel, CircuitStudio, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed. TU0116 (v1.3) April 13,