UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180A DIGITAL SYSTEMS I Winter 2015
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1 UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I Winter 2015 LAB 1: Introduction to Quartus II Schematic Capture and ModelSim Simulation This lab provides an introduction to a few of the tools you can use in EEC180A including the Quartus II design software, and the ModelSim simulation software. In this lab, you will use the Quartus II schematic capture tool for design entry and ModelSim to simulate your design. This lab will be done as a self-paced tutorial. I. SCHEMATIC CAPTURE USING QUARTUS II The ECE Department has Altera s Quartus II 13.0SP1 installed on the Windows workstations in To use one of these PCs, you should log in and create a directory for your projects. For example, you can create a folder eec180a in your My Documents folder. Then add a folder lab1 under eec180a for this lab. 1. Start Quartus II. NOTE: If you get the message: "License file is not specified" then do the following: a) Select the option that reads "If you have a valid license file, specify the location of your license file" and click OK. b) In the "License File" setup type the following: 1800@samba2.ece.ucdavis.edu and click OK 2. Click on File > New Project Wizard to start the project wizard. - Click Next once you have read the Introduction page. - On page 1, browse to your working directory such as C:/Users/name/Documents/eec180a/lab1 - Give the project and the top-level design entity the same name, such as lab1. - Click Next to move to page 2 - In this lab, you don t need to Add Files, so click Next to move to page 3. - Under the Device family section, select Cyclone II as the Family. - Under the Target device section, select Specific device selected in Available devices list and choose the device EP2C35F672C6. - Click Next to move to page 4. 1
2 - For Simulation, select the tool ModelSim-Altera from the drop-down box and specify the format as Verilog. (Quartus II will generate a Verilog netlist from your schematic, allowing you to easily simulate your design.) Click Next to move to page 5. - Click Finish once you have reviewed the Summary page. 3. Open a New schematic page: - Click File > New and select Block Diagram/Schematic File and click OK. - Click File > Save As and specify a file name such as lab1. Make sure the box Add file to current project is checked and click Save. 4. Start placing components on your blank schematic page: - Double-click on the blank schematic page to bring up the Symbol dialog box. You can browse through the libraries to view the various components available. - Enter as the Name and click OK. Place the component in the upper middle portion of your schematic. - Place an additional symbol on your schematic in order to build a simple 8-bit counter. One way to do this is to use the Copy and Paste options from the Edit menu, or the keyboard shortcuts. MAKING CONNECTIONS - There are two methods of drawing a net or bus between two pins. - 1) If "Rubberbanding" is on, moving a device so that one pin touches another pin can make a connection. Once this occurs, the pins are connected and moving the devices apart will show a wire or bus. "Rubberbanding" can be turned on or off using the icons on the left side of the screen. (By placing the cursor over each icon, you can display the function of each icon button at the bottom of the screen.) - 2) If "Rubberbanding" is off, a wire must be drawn between the two pins. This is done by moving the cursor to the end of a pin until it changes from an arrow to a +. Dragging the mouse from one pin to another with the LMB pressed will draw a wire. Wire the two components into an 8-bit counter circuit as shown in Fig. 1. Get and place a vcc components on your schematic and wire connect it to complete the circuit. Place input and output components on the schematic as shown in Figure 1. A convenient way to place the output pin components is to place one output part on the schematic. Label the output pin name q0 by double-clicking the pin_name and typing q0. Connect this pin to QA as shown in Figure 1. Then select it and use Ctrl-C and 2
3 Ctrl-V to copy and paste a new output component. This will automatically get the name q1. Next, type Ctrl-V again to get the q2 output pin, etc. MAKING CONNECTIONS BY NAME Although it isn't necessary for this counter circuit, you can also make connections by labeling wires with identical signal names. Wires with the same signal name are considered to be connected by the Altera software if the wires are on the same level of hierarchy. Note that a signal name must be very close to the wire that it is naming, otherwise the Altera software will just interpret it as text rather than a valid net name. Thus, if you move a signal name too far away from its net, it will cease to be a valid net name. You can check if a wire or bus is labeled by clicking on the wire or bus. If the text is highlighted along with the wire or bus, then it is a valid signal name. Label the RCO (Ripple Carry Output) signal which connects to the ENT and ENP (Enable) inputs of the other component as "rco1" as shown in Figure 1. To label the net, click the wire to select it and just type the name. At this point, your schematic should look like the one shown below in Figure Compile your design by clicking on the Start Compilation icon,, on the menu toolbar. (You can also select Processing > Start Compilation.) 6. Your design should compile without Errors, and a pop-up box should confirm that Full Compilation was successful. You can ignore any warnings. Note: If you get an Error , it means two components have the same instance name. You can right-click one of the components and select Properties and give it a unique instance name. 3
4 Figure 1. Initial Schematic II. MODELSIM SIMULATION Once your design has been drawn in Altera s Quartus II, it is important to examine and to verify the functionality of the design. For small scale designs, it might be simpler to directly implement the design rather than simulate its functionality. However, in real world designs, logic circuits are often encompass tens of millions of logic gates making the design impossible to cost effectively implement and test. For this section, you will reuse the counter circuit from Part I, Figure 1. You will set up the simulator environment, and with the design schematic you will compile the Altera simulation model libraries, simulate your Quartus II design, and view the input/output waveforms in ModelSim to ensure correct behavior. Note: There are two parts to the simulation environment setup; the ModelSim simulation tool setup and the schematic capture setup. The ModelSim tool setup is only done one time and will remain in effect for all new and old projects. However, the schematic capture setup must be performed for every project. 1. It does not matter whether you have a project open or not. Set up the ModelSim Tool by clicking on Tools > Options 2. Under the General Tab, click on EDA Tool Options. 4
5 - Find the EDA Tool name, ModelSim-Altera. Enter the path location of the ModelSim-Altera installation of your local machine. For your PC installation following Appendix A below, the path should be: C:\altera\13.0sp1\modelsim_ase\win32aloem - The path to the ModelSim-Altera executable might already be entered from a previous section or by default. Double-check the EDA Tool Options settings as shown in Figure 2, to make sure the path is correct. If the incorrect path is set, an execution error will occur and ModelSim-Altera will not automatically open during project simulation. Figure 2. Tool options setting in Altera Quartus II for Windows OS 3. If the project containing the counter in section I is not open, open it. 4. Click on Assignments > Settings 5. Under the EDA Tool Settings, click Simulation - Make sure that the Tool name is set to ModelSim-Altera. - Under the EDA Netlist Writer Settings, make sure that the Format for output netlist is set to "Verilog HDL". - The output directory where your simulation files are stored will be in a subfolder "simulation/modelsim" - Your settings should look like Figure 3. 5
6 - Click Apply, and then click OK to exit the from the Settings window. Figure 3. Settings dialog box to set up the simulation environment 6. Make sure all previous ModelSim windows are closed. Multiple ModelSim programs running can cause compiling errors. 7. Compile the entire design, and run the Gate Level Simulation by pressing the icon. A pop-up box will appear asking you to select which Timing model to run. From the drop down menu, select "Fast Model" and press Run. 8. ModelSim will open and your design will be automatically transferred to ModelSim. Verify this by looking at "work" folder in the Library list window. If the Library window is not open, select View > Library to open it. Click on the + to expand the work library. You should see your Lab1 project name, which is a Verilog netlist output file, in the work Library. 9. To simulate your design, select Simulate > Start Simulation from the toolbar menu. Click on the Design tab and select your design file in the work library. In Figure 4, the Verilog netlist file, lab1, has been selected. 6
7 Figure 4. Selecting your Verilog netlist output file to simulate 10. Next, click the Libraries tab in the same Start Simulation dialog box. Click the Add button to the left of the Search Libraries (-L) pane. A Select Library dialog box will pop up. Select the down arrow and scroll down through the list of libraries. Select cycloneii_ver, as shown in Figure 5. Figure 5. Selecting the cycloneii_ver library 7
8 11. Click OK to close the dialog box. Your screen will update and show you the "sim- Default", the "Objects", and the "Processes (Active)" window as shown in Figure 6. Figure 6. Simulation windows updated 12. You may or may not have the waveform viewer open. If not, click on View and select Wave. This will display the waveform viewer window. 13. You are now ready to simulate and view the values of the signals in your design. Let's add some signals we want to inspect into the Wave window. With your top-level design file highlighted in the sim-default window, drag and drop the clk, reset, rco, and the q0 to q7 signals from the Objects window into the Wave window. (Another method is to select clk and reset and the other signals in the Objects window, right-click and select Add Wave.) 14. For the simulation to function, you need to set up the input stimulus on the input pins of your design. Right-click on the clk signal, and select Clock... The Define Clock window will pop up and from here we can set parameters of the clock. Set the clock period to 8
9 100000, where picoseconds are the default time units. Leave the other settings at their default values and select OK to close the Define Clock window. 14. Right-click on the reset signal and select Force... The Force Selected Signal window will pop up. This window is used to force signals in your design to logic 0 or logic 1. Enter the digit 1 (one) in the Value field and select Drive in the Kind field. Press OK to save changes and close the window. 15. You are now finished with setting up the input stimulus. Enter 1000 ns time in the simulation toolbar in order to simulate 10 clock cycles, and click the Run icon,, as shown in Figure 7. You can also type in the command line 'run 1000 ns' (without quotes) and the simulation will run for 1000 ns. Another option is to press the F9 hotkey. Figure 7. Simulate Tool Bar with 1000 ns Simulation Time 15. Select View > Zoom > Zoom Full in order to display the full 10 clock cycles in the Wave window. 16. Reset the counter by forcing reset to zero and Run for 1000ns. Then force reset to 1 (one) to allow the counter to count again. Run in increments of 1000ns to observe the count. 17. Continue to simulate your design and change and set reset to zero to determine whether or not your design functions as expected. You can restart your simulation at any time by selecting Simulate/Restart 18. We could continue the simulation now and view the q0-q7 signal individually. However, since these outputs form an 8-bit counter, it is more convenient to group the signals together and view the count value in hexadecimal form. Highlight q7 to q0 by holding the Shift key down as you select each one; right click and select Combine Signals. The Result name could be something like q7_to_q0, and the radix should be hexadecimal. You can right-click on the q7_to_q0 node and select Top Down or Top up to reverse the order of the bits in the group, if necessary. To change the radix, right click on the q7_to_q0 and select Radix>Hexadecimal. Your combined signals should look similar to those of Figure Run the simulation to observe the combined count signals. Observe at what count the rco pulse occurs.. 9
10 Figure 8. Simulation Output 20. Demonstrate to your TA that you can simulate the circuit in ModelSim by demonstrating your simulation and have your TA sign your lab verification sheet. 10
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