Step 1: Downloading the source files

Transcription

1 Introduction: In this lab and in the remainder of the ELEC 2607 labs, you will be using the Xilinx ISE to enter and simulate the designs for your circuits. In labs 3 and 4, you will use ISE to compile your design into a Programmable-Logic Array, which will electrically connect your circuit inside a silicon chip. There are no wires for you to plug in. It makes a circuit you can test with switches and lights. In the Xilinx ISE (or just ISE), you will be using what is called schematic entry. With schematic entry, you just draw the circuit in the computer the same way you draw it out when making a circuit diagram. Symbols for components such as AND gates are placed on a screen and the wires are drawn to connect them. This is similar to lab 1 but avoids that mess of wires, and you can use as many gates as you need of any type. Three types of files you will deal with are: A schematic file (ends in.sch) is the picture you draw on the screen. Specifies which components you use and how they are connected. A symbol file (ends in.sym) specifies how to draw a symbol on the screen and what its input and output connections are. There are prebuilt symbol files for all the gates (NAND, OR ). There is a pre-drawn symbol file for the full adder circuit that you build. It is used in the top level circuit you use when you put together three 1-bit full adders to make a 3-bit adder. This allows you to insert tree squares square labeled full adder in your 3-bit adder circuit, instead of having to draw the full adder circuit three times. Alternately one could say a symbol basically represents a smaller schematic. It specifies which inputs need to be fed into the lower level schematic and what outputs it will generate, so that these can be connected properly in the higher level schematic. A test fixture file (ends in.tf). This supplies input signals to your circuit when we simulate it. A simulation of the circuit with no inputs does nothing. You will observe the output and make sure they agree with what we expect. The test fixture is written in a hardware programming language (Verilog) which is based on C. You can look at the program, but you won t need to understand it until the next lab. You will learn much more about Verilog in ELEC Step 1: Downloading the source files Before you can download the files, you will need to make a directory for them. You can do this on the networked H: drive, which will allow you to access your files from any other computer in the lab. The source files are available on the course website. As the files are compressed in an archive, you will have to uncompress them and move them into your folder. Typically, you do this just by opening the

2 .zip file and moving the files as you would normally. Don t do this quite yet, since Xilinx will create the directory for your project. Step 2: Run the Xilinx ISE and create a new project You can run the Xilinx ISE from the start menu Start -> All programs -> Xilinx Design Tools -> ISE Design Suite > ISE Design Tools -> 64-bit project navigator Or you can run it from appropriate icon on the desktop. The Xilinx ISE groups together files used for the same design in a project. To create a new project, perform the following: File -> New Project. Or just click on the new project button in the start tab of the ISE. First you should enter the path. You should choose a directory for all of the labs in Do not make a directory specifically for lab 2, since the Xilinx ISE will automatically do that when you enter the project name. Next in Project Name, enter a project name. Something descriptive like AdderLab or Lab2 will be appropriate for this lab. Please note that Xilinx will create the project directory automatically.

3 Finally, Top-Level Source Type should be set to Schematic, since we are using schematic entry. You must now fill in the device information EXACTLY as shown below, If you don t, you will find out why it was important when you get to Step 3 and your simulation does not work! We can always change the settings later, but finding out what you messed up later is a pain to figure out. It s much better to save yourself some trouble and get it right now. Make sure: The Family, Device, Package and Speed agree with the figure below. Make sure: Top-Level Source Type = Schematic, If not, back up and fix it in the window you just left Synthesis Tool = XST (VHDL/Verilog) Simulator = Modelsim-SE Verilog; setting this, sets the next next line. Preferred Language = Verilog

4 When Finished. Click Next You will see the Project Summary screen shown, and you can click finish to create your project. This is now the time to move the source files from the.zip file you downloaded (or will download) from the course website into the project folder that Xilinx created. After you have moved the files, right-click on the Empty View space and select Add Source.

5 Then add the following sources: addertest.tf, addertop.sch and fulladder.sch. (You don t need to manually add the.sym files as long as they are in the same directory as the.sch files). Note: if you did not put the files into your project directory, you should use Add Copy of Source instead of Add Source.

6 Step 3: Editting the schematic The ISE should have automatically parsed the files you added and determined the simulation hierarchy. The hierarchy starts with the simulation test bench, which has instantiated an instance of the addertop module, which in turn has instantiated a copy of the fulladder module. You can edit the schematic for the top level view by double clicking the addertop module. To get this screen, make sure you are looking at the design tab, and set the radio button to simulations. By clicking on the + buttons, you can expand the view to see the files in the hierarchy.

7 Make sure these options are selected Open this file Notice how the selected Tab is now the option tabs. There are a few important things to note:

8 When you click on a branch: Select the entire branch (Explained in the Moodle Glossary, under Nets.) Select the line segment (This option is useful to avoid erasing multisegmented lines.) We would strongly suggest selecting the 'Select the line segment' option now. Navigating in the Schematic View As you can see there is a single block in the schematic called fulladder. To complete your circuit you will need 3 or 4 instances (copies) of this block. At this point there is no circuitry inside the block, only connections To edit the schematic inside the block, click on the block. It should be highlighted in red. On the "View" menu select "Push into Symbol" or you can click on the can right-click on the block and select Symbol->Push into symbol button. Alternatively, you To go back you can use the tabs at the bottom of the panel, as shown below or you can use the button. All the open files can be accessed by clicking on the tabs at the bottom of the window. The Following keys will change the zoom: F5: refresh window F6: zoom out full F7: zoom out F8: zoom in F9: zoom to a box (press F9 then draw a box around the area you want to view) Editing the Schematic You now need to add the circuitry inside each of the hierarchical blocks Adding gates to the schematic Click the "Symbols" tab or the button.

9 In the "Categories" list, select "Logic". This will give you a list of gates in the "Symbols" list. Click on the desired gate in the "Symbol" list, then move over to the schematic and click (do not drag and drop). The symbol will be placed on the schematic. and3b1 is a 3-input AND gate with an inverting bubble on one input. Add the remaining gates to the schematic. (For the T-Bird and MIDI labs) Flip-flops can be found in Category "Flip_Flop". Use "fdc" for your flip-flops. Press Esc or click to exit symbol entry mode. Connecting gates on the schematic Drawing wires Click on the button or press Ctrl-W to enter wiring mode. Do Not use the icon This will not make a wire that can be simulated. It is used only for cosmetic drawing. If you hover over a pin on a gate, the cursor will change to four little boxes. You can click to start a wire. Move to the pin on the other gate and click when the cursor changes. Wires that terminate on other wires need to be double-clicked to finish the wire. All pins that you want to label must have wires connected to them. Press Esc or click to exit wiring mode. Labeling wires on the schematic First decide if you want to rename a complete net, the usual, or part of a net (branch), which is usually when the net has two apparently disconnected wires with the same name. In the figure, Branch1 and Branch 2 have the same name (A) so they are connected together. To rename Brfanch2 only, use Select the line segment. Go to The Options Tab to select the proper mode. (The entire branch (net) or a line segment of the branch.) Click on the button or press Ctrl-D to enter labeling mode. On the Options window, enter the wire name in the Name box. (Ignore Select Bus Name) Click on the wire that you want to name in the schematic. To connect to the input or output ports, use the same wire name as the port, OR THE PORT NAME WILL CHANGE! Press Esc or click to exit labeling mode. Use this in the AdderTop schematic to label the three wires coming from the carry outputs of the three adders. By default they are labeled strange names like XLXN_13. Label them c1, c2, and c3 so you will be able to locate them

10 in your simulation. Warning ISE is case sensitive. Adding ports (I/O markers) to the schematic Click on the button or press Ctrl-G to enter port mode. On the "Options" tab, select the type of port (ie: input, output, etc.) Click on the end of the wire you want to add the port to. Ports can only be added to wires (ie: not directly to gate inputs or outputs). To label the port, use the label tool Ctrl-D to give the wire that the port is attached to a name. If a wire is already labeled, the port will assume the wire name when it is added. Press Esc or click. Renaming your files If you mess up and decide to use a new file called say addertopgood, don't. Instead save your old file as addertopbad_1 say and keep the name addertop The Simulator will look for addertop without an illegal name change. Important Note: 1) DO NOT change any of the port names in any schematics. If you do ModelSim will not be able to simulate you design. 2) In addertop, check that the wires from the carrys are labeled c1, c2 and c3. Step 3: Simulating the Adder Schematic Things to do before you run a simulation Use the automatic schematic check 1. In the top menu line, just below the blue title line, select Tools 2. In the dropdown menu select Check Schematic. 3. Look at the lowest box in the window, where the error messages are written, and check that there are no errors. 4. Of course this really means no "easy to find" errors. If you have started a previous ModelSim close it completely before starting again. The second one will appear to start, and will leave you wondering why it does not work. You can run only one at a time. If you changed your schematic after running a previous ModelSim and you have strange happenings, then: - In the Xilinx window, in the top menu bar click on Project - In the pull down menu select Cleanup Project Files - Ignore warnings, you will not delete your schematics.

11 Compiling the libraries and other first-time tasks For various reasons that are outside the scope of this document, the first time you run the simulator, you may have to compile the simulation libraries. Select this option Double-click this option To do this, select the design tab and the simulation view. Click on the XCR3064xl-6pC44 and double click on the Compile HDL simulation Libraries option. You should only need to do this once per library, if at all. In addition, you might get an error message when running a simulation about missing the simulation executable path. In the Edit-> preferences options, go to the Integrated tools category and enter the simulator as you see below:

12 Running the simulation Simulation 1. In the Design Panel, the top line, select the Simulation check circle 2. In the Hierarchy subpanel select testfixture ( addertest.tf) 3. In the Processes panel, click on the plus sign beside "ModelSim Simulator" and then double click on "Simulate Behavioral Model"

13 You might get an warning message similar to what you see below. Since you do not want to abort the simulation, click No. Once you manage to get ModelSim up and going, you should see something similar to the below figure.

14 The box on the right shows the state of various waveforms as time passes. By default, the simulator automatically stops after 100ps, so we want to continue to the end of the simulation. You can do this by going to the Simulate menu and selecting Run-> run All. The simulator will stop once it reaches the $STOP statement. If you hit run-all again, there are no more $STOP statements for it to reach and your circuit will simulate forever. You can stop the simulation by selecting the appropriate command in the simulate menu (Simulate->Break). The box on the left shows you the various modules and hierarchies in your design. The entire adder module is called UUT (Unit under test). Clicking on the + sign will allow you to see the sub-modules. If you used the default names for the blocks, the names will be assigned arbitrarily and may not make sense. You can refer back to the schematic view to get the names of different blocks (right click and go to the device properties). If you select a module, the box to the right shows the wires and nets present in that module. You can select a few of them and add them to your waveform view by right-clicking on them and selecting move->wave->selected wave forms. You will then have to restart your simulation (simulate->run->restart and press ok) and then run-all again.

15 What may come up first is usually Test Fixture program. This is the program that generates the X, Y and C 0, the inputs for the adder. It is written in a language called Verilog which you won t have to understand for awhile. Once the simulation is finished, you will see the test fixture code. To view the waveforms click on the wave tab as shown below. The waveform view generally starts out in a zoomed-in view. To zoom out, you can select the Zoom Full option in the menu bar. There are also options to zoom in and out unconditionally, and to zoom in on the current cursor.

16 If you got this far, then congratulations, you have successfully created and loaded the circuit and ran a simulation. Of course, you will want to know if your circuit works. On the left of the waveform display, you will see labels as shown below. There are four that you need to look at first; these are: c0 is the first carry term that signifies if we are adding or subtracting X210 is a binary representation of our 3-bit X-input Y210 is a binary representation of our 3-bit Y-input SUM is the sum of X210 and Y210 depending on whether we are adding or subtracting. By looking at these waveforms you should be able to confirm if Y(+/-)X = SUM. You can start be comparing your results to the calculations you did in the prelab. Assuming you did them correctly, they can be an indication about whether your circuit is working or not. If you see an error, try to isolate it and determine which bit(s) is in error. This will help you figure out which block is causing the problem. Once you figure that out, fix your schematic and re-simulate. Remember that you must close ModelSim before you resimulate, otherwise you will get a license error. After (and only after) you have confirmed your circuit works, you can ask a TA to give you a check-out. The first question the TA will ask is How do you know it works? It is a good idea to know how to answer this question. If the your circuit works the TA will ask you to print out the required pages which he/she will sign before you get your checkout mark. You must annotate your printout and explain what it means, in your report. What to keep and put in your report For the 3-bit adder lab you need to have a copy of the following 3 things to attach to your final report.

17 Your top level schematic, addertop.sch The adder schematic, fulladder.sch Two print outs of the simulation waveforms from modelsim o A fully zoomed out view showing the complete simulation o A zoomed in view(s) for annotation You don t need to physically print them out, as long as you include them in your report. The zoomed in waveform(s) must show the following 4 test cases working. An Add A Subtract An Add with overflow A Subtract with overflow You must label these diagrams by clearly indicating what the input and outputs of the circuit are. You should also indicate what the expected results are. In your report, it is considerably better to show only the relevant pieces of information. For instance, if you are discussing case 1, show only the inputs and outputs for case 1. If you do this approach, you should still show the entire waveform somewhere.