Avnet, Xilinx ATCA PICMG Design Kit Hardware Manual

Transcription

1 user s guide Avnet, Xilinx ATCA PICMG Design Kit Hardware Manual Avnet Design Services 1 of 18 Rev /15/2004

2

3 Table of Contents 1 Overview Jumpers Personality Module Mechanicals Personality Module Headers Fabric Interface FPGA Fabric Interface FPGA Control Plane Section Processor Cores PLB Arbiter DDR SDRAM Memory Controller BlockRAM (BRAM) Memory Controller PLB2OPB Bridge OPB Arbiter Ethernet MAC UART System ACE MPU Interface I 2 C Interface Controllers General Purpose IO Controller Interrupt Controllers DCR Bridge Fabric Interface FPGA Data Plane Section Aurora Interface Logic Channel Interfaces & FIFOs Address Mapping Logic PICMG Synchronization Clock Interface Power Supply Subsystem VCC3V3_BOOT Power Bus VCC12V_MAIN Power Bus References Avnet Design Services 3 of 18 Rev /15/2004

4 Figures Figure 1: ATCA 4x4 Full-Mesh Line Card Block Diagram... 5 Figure 2: Jumper Locations... 6 Figure 3: 10/100 Ethernet Port Routing... 8 Figure 4: Personality Module Dimensions... 9 Figure 5: Fabric Interface FPGA Control Plane Section Block Diagram Figure 6: Fabric Interface FPGA Data Plane Section Block Diagram Figure 7: Synchronization Clock Interface Logic Figure 8: Power Supply Subsystem Block Diagram Tables Table 1: Jumper Settings... 7 Table 2: Personality Module J1 Header Pinout Table 3: Personality Module J2 Header Pinout Table 4: Personality Module J3 Header Pinout Table 4: Personality Module J3 Header Pinout Table 5: Personality Module J4 Header Pinout Avnet Design Services 4 of 18 Rev /15/2004

5 1 Overview The Full Mesh Line Card is intended to serve as a development platform for PICMG 3.x line cards supporting port rates to 10 Gbps. It includes a Virtex-II Pro based FPGA based fabric interface that also includes all PICMG 3.0 defined card and shelf management functionality. Management firmware executes on one of the Virtex-II Pro s PowerPC processors running an embedded Linux operating system. The card also includes headers to interface to a user defined Personality Module. This module is used to implement application specific line card processing and external interfaces. IO access for this module can be through the front panel, or Rear Transition Modules (RTMs). The Personality Module also has full access to the PICMG 3.0 Update Channel Interface. The card implements a 200W power supply and all PICMG 3.0 defined fusing and protection circuitry. Figure 1: ATCA 4x4 Full-Mesh Line Card Block Diagram Avnet Design Services 5 of 18 Rev /15/2004

6 2 Jumpers Figure 2 shows the jumpers used to configure the card in relation to the other components. Figure 2: Jumper Locations Avnet Design Services 6 of 18 Rev /15/2004

7 Table 1 describes the function of each jumper along with the factory settings. Table 1: Jumper Settings Reference Designation Settings Description JMPR1 1 to 2* Selects the Parallel IV cable header (P115) for JTAG debug. open Selects the Trace header (P109) for JTAG debug. JMPR2 1 to 2* Powers PM I/O pins with 2.5V for applications such as RapidIO or SPI-4 2 to 3 Powers PM I/O pins with 3.3V for applications such as SPI-3 JMPR3 1 to 2 Powers VTRX on the top MGT bank with 2.5V. 2 to 3* Powers VTRX on the top MGT bank with 1.8V. JMPR4 1 to 2 Powers VTRX on the bottom MGT bank with 2.5V. 2 to 3* Powers VTRX on the bottom MGT bank with 1.8V. JMPR5 and 6 1 to 2* Enables the MGT power open Provides path for MGT current measurement JMPR7 and 8 1 to 2* Enables the 12V supply to the Personality Module (PM) connector. open Provides path for PM supply current measurement JMPR9 and 10 1 to 2* Enables the 12V supply to the Rear Transition Module (RTM) connector. open Provides path for RTM supply current measurement JMPR11 and 1 to 2* Enables the 2.5V supply 12 open Provides path for 2.5V supply current measurement JMPR13 and 1 to 2* Enables the 1.5V supply 14 open Provides path for 1.5V supply current measurement JMPR15 1 to 2 Selects 125MHz MGT reference clock frequency 2 to 3 Selects MHz MGT reference clock frequency JMPR16 1 to 2* Loops back TDO to TDI when PM is not installed. 1 to 2* Routes the collision LED signal from the 10/100 PHY to the front panel JMPR17 RJ45 2 to 3 Routes the collision LED signal from the 10/100 PHY to the Personality Module JMPR18 1 to 2* Routes the link LED signal from the 10/100 PHY to the front panel RJ45 2 to 3 Routes the link LED signal from the 10/100 PHY to the Personality Module Routes 10/100 Ethernet port to one of the following interfaces: JMPR19 See Figure ATCA Base Interface 3 Personality Module header J4 Front panel RJ-45 *Indicates factory setting Avnet Design Services 7 of 18 Rev /15/2004

8 3 Personality Module Mechanicals The dimensions of the Personality Module, and its relationship to the baseboard are shown in Figure 3. Figure 3: 10/100 Ethernet Port Routing DIFF PHY TPON DIFF PHY TPIN DIFF PHY TPOP DIFF PHY TPIP Ethernet jumped to the Front Panel DIFF PHY TPON DIFF PHY TPIN DIFF PHY TPOP DIFF PHY TPIP Ethernet jumped to the Personality Module DIFF PHY TPON DIFF PHY TPIN DIFF PHY TPOP DIFF PHY TPIP Ethernet jumped to the Backplane (SHMC) Avnet Design Services 8 of 18 Rev /15/2004

9 Figure 4: Personality Module Dimensions Avnet Design Services 9 of 18 Rev /15/2004

10 4 Personality Module Headers Table 2: Personality Module J1 Header Pinout Pin Pin Pin Name Number Number Pin Name 1 GND 2 GND 3 ATCA_RTM_RX0+ 4 ATCA_RTM_TX0+ 5 ATCA_RTM_RX0-6 ATCA_RTM_TX0-7 GND 8 GND 9 GND 10 GND 11 ATCA_RTM_RX1+ 12 ATCA_RTM_TX0+ 13 ATCA_RTM_RX1-14 ATCA_RTM_TX0-15 GND 16 GND 17 ATCA_RTM_RX2+ 18 ATCA_RTM_TX0+ 19 ATCA_RTM_RX2-20 ATCA_RTM_TX0-21 GND 22 GND 23 GND 24 GND 25 ATCA_RTM_RX3+ 26 ATCA_RTM_TX0+ 27 ATCA_RTM_RX3-28 ATCA_RTM_TX0-29 GND 30 GND 31 GND 32 GND 33 FPGA_TMS 34 FPGA_PM_TDO 35 FPGA_PM_TCK 36 FPGA_PM_TDO 37 FPGA_PROG_B 38 FPGA_INIT 39 ATCA_RTM_GPIO1 40 ATCA_RTM_GPIO2 41 GND 42 GND 43 ATCA_RTM_GPIO3 44 ATCA_RTM_GPIO4 45 ATCA_RTM_GPIO5 46 ATCA_RTM_GPIO6 47 ATCA_RTM_GPIO7 48 ATCA_RTM_GPIO8 49 ATCA_RTM_GPIO9 50 ATCA_RTM_GPIO10 51 GND 52 GND 53 ATCA_RTM_GPIO11 54 ATCA_RTM_GPIO12 55 ATCA_RTM_GPIO13 56 ATCA_RTM_GPIO14 57 ATCA_RTM_GPIO15 58 ATCA_RTM_GPIO16 59 ATCA_RTM_GPIO17 60 ATCA_RTM_GPIO18 61 GND 62 GND 63 ATCA_REFCLK_OUT_EN_N 64 ATCA_REFCLK_A_IN 65 ATCA_REFCLK_OUT 66 ATCA_REFCLK_B_IN 67 GND 68 GND 69 VCC12V_PM 70 VCC12V_PM 71 VCC12V_PM 72 VCC12V_PM 73 VCC12V_PM 74 VCC12V_PM 75 VCC12V_PM 76 VCC12V_PM 77 VCC12V_PM 78 VCC12V_PM 79 GND 80 GND Avnet Design Services 10 of 18 Rev /15/2004

11 Table 3: Personality Module J2 Header Pinout Pin Pin Pin Name Number Number Pin Name 1 GND 2 GND 3 ATCA_UC_RX4+ 4 ATCA_UC_TX4+ 5 ATCA_UC_RX4-6 ATCA_UC_TX4-7 GND 8 GND 9 GND 10 GND 11 ATCA_UC_RX3+ 12 ATCA_UC_TX3+ 13 ATCA_UC_RX3-14 ATCA_UC_TX3-15 GND 16 GND 17 ATCA_UC_RX2+ 18 ATCA_UC_TX2+ 19 ATCA_UC_RX2-20 ATCA_UC_TX2-21 GND 22 GND 23 GND 24 GND 25 ATCA_UC_RX1+ 26 ATCA_UC_TX1+ 27 ATCA_UC_RX1-28 ATCA_UC_TX1-29 GND 30 GND 31 GND 32 GND 33 ATCA_UC_RX0+ 34 ATCA_UC_RX0+ 35 ATCA_UC_RX0-36 ATCA_UC_RX0-37 GND 38 GND 39 FI_TX0+ 40 FI_RX0+ 41 FI_TX0-42 FI_RX0-43 GND 44 GND 45 FI_GPIO_0 46 FI_GPIO_1 47 FI_GPIO_2 48 FI_GPIO_3 49 GND 50 GND 51 FI_GPIO_4 52 FI_GPIO_5 53 FI_GPIO_6 54 FI_GPIO_7 55 GND 56 GND 57 DIFF_FI_GCLK_2P 58 FI_GPIO_8 59 DIFF_FI_GCLK_2N 60 FI_GPIO_9 61 GND 62 GND 63 DIFF_FI_GCLK_0P 64 DIFF_FI_GCLK_1P 65 DIFF_FI_GCLK_0N 66 DIFF_FI_GCLK_1N 67 GND 68 GND 69 DIFF_FI_GPIO_40P 70 CLK_FI_3V3_0 71 DIFF_FI_GPIO_40N 72 CLK_FI_3V3_1 73 GND 74 GND 75 DIFF_FI_GPIO_38P 76 DIFF_FI_GPIO_39P 77 DIFF_FI_GPIO_38N 78 DIFF_FI_GPIO_39N 79 GND 80 GND Avnet Design Services 11 of 18 Rev /15/2004

12 Table 4: Personality Module J3 Header Pinout Pin Pin Pin Name Number Number Pin Name 1 GND 2 GND 3 DIFF_FI_GPIO_36P 4 DIFF_FI_GPIO_37P 5 DIFF_FI_GPIO_36N 6 DIFF_FI_GPIO_37N 7 GND 8 GND 9 GND 10 GND 11 DIFF_FI_GPIO_34P 12 DIFF_FI_GPIO_35P 13 DIFF_FI_GPIO_34N 14 DIFF_FI_GPIO_35N 15 GND 16 GND 17 DIFF_FI_GPIO_33P 18 GND 19 DIFF_FI_GPIO_33N 20 GND 21 GND 22 GND 23 GND 24 GND 25 DIFF_FI_GPIO_31P 26 DIFF_FI_GPIO_32P 27 DIFF_FI_GPIO_31N 28 DIFF_FI_GPIO_32N 29 GND 30 GND 31 GND 32 GND 33 DIFF_FI_GPIO_29P 34 DIFF_FI_GPIO_30P 35 DIFF_FI_GPIO_29N 36 DIFF_FI_GPIO_30N 37 GND 38 GND 39 DIFF_FI_GPIO_27P 40 DIFF_FI_GPIO_28P 41 DIFF_FI_GPIO_27N 42 DIFF_FI_GPIO_28N 43 GND 44 GND 45 GND 46 GND 47 DIFF_FI_GPIO_25P 48 DIFF_FI_GPIO_26P 49 DIFF_FI_GPIO_25N 50 DIFF_FI_GPIO_26N 51 GND 52 GND 53 GND 54 GND 55 DIFF_FI_GPIO_23P 56 DIFF_FI_GPIO_24P 57 DIFF_FI_GPIO_23N 58 DIFF_FI_GPIO_24N 59 GND 60 GND 61 DIFF_FI_GPIO_21P 62 DIFF_FI_GPIO_22P 63 DIFF_FI_GPIO_21N 64 DIFF_FI_GPIO_22N 65 GND 66 GND 67 GND 68 GND 69 DIFF_FI_GPIO_19P 70 DIFF_FI_GPIO_20P 71 DIFF_FI_GPIO_19N 72 DIFF_FI_GPIO_20N 73 GND 74 GND 75 DIFF_FI_GPIO_17P 76 DIFF_FI_GPIO_18P 77 DIFF_FI_GPIO_17N 78 DIFF_FI_GPIO_18N 79 GND 80 GND Avnet Design Services 12 of 18 Rev /15/2004

13 Table 5: Personality Module J4 Header Pinout Pin Pin Pin Name Number Number Pin Name 1 GND 2 GND 3 DIFF_ETH_PM_RX- 4 DIFF_ETH_PM_TX- 5 DIFF_ETH_PM_RX+ 6 DIFF_ETH_PM_TX+ 7 GND 8 GND 9 LEDL_PM 10 LEDC_PM 11 NC 12 NC 13 NC 14 NC 15 NC 16 NC 17 NC 18 GND 19 NC 20 DIFF_FI_GPIO_16P 21 NC 22 DIFF_FI_GPIO_16N 23 GND 24 GND 25 DIFF_FI_GPIO_14P 26 DIFF_FI_GPIO_15P 27 DIFF_FI_GPIO_14N 28 DIFF_FI_GPIO_15N 29 GND 30 GND 31 GND 32 GND 33 DIFF_FI_GPIO_12P 34 DIFF_FI_GPIO_14P 35 DIFF_FI_GPIO_12N 36 DIFF_FI_GPIO_14N 37 GND 38 GND 39 DIFF_FI_GPIO_10P 40 DIFF_FI_GPIO_12P 41 DIFF_FI_GPIO_10N 42 DIFF_FI_GPIO_12N 43 GND 44 GND 45 GND 46 GND 47 DIFF_FI_GPIO_8P 48 DIFF_FI_GPIO_9P 49 DIFF_FI_GPIO_8N 50 DIFF_FI_GPIO_9N 51 GND 52 GND 53 DIFF_FI_GPIO_6P 54 DIFF_FI_GPIO_7P 55 DIFF_FI_GPIO_6N 56 DIFF_FI_GPIO_7N 57 GND 58 GND 59 GND 60 GND 61 DIFF_FI_GPIO_4P 62 DIFF_FI_GPIO_5P 63 DIFF_FI_GPIO_4N 64 DIFF_FI_GPIO_5N 65 GND 66 GND 67 DIFF_FI_GPIO_2P 68 DIFF_FI_GPIO_3P 69 DIFF_FI_GPIO_2N 70 DIFF_FI_GPIO_3N 71 GND 72 GND 73 GND 74 GND 75 DIFF_FI_GPIO_0P 76 DIFF_FI_GPIO_1P 77 DIFF_FI_GPIO_0N 78 DIFF_FI_GPIO_1N 79 GND 80 GND Avnet Design Services 13 of 18 Rev /15/2004

14 5 Fabric Interface FPGA The Fabric Interface FPGA implements not only the data plane functions needed to transfer data across the distributed fabric, but also all management functions defined in the PICMG 3.0 specification. When placed in slots one or two the card is capable of acting as a Shelf Manager. The following sections discuss the control plane and data plane functionality of the FPGA. 5.1 Fabric Interface FPGA Control Plane Section The control plane section of the Fabric Interface FPGA implements management functions for the card. All of these functions are implemented as firmware running on an embedded Linux operating system. The functions that are provided include: IPMI agent Shelf Manager Hardware and software update via ShMC interface Figure 5 shows a block diagram of the Control Plane section of the Fabric Interface FPGA. Figure 5: Fabric Interface FPGA Control Plane Section Block Diagram Avnet Design Services 14 of 18 Rev /15/2004

15 Processor Cores The Virtex-II Pro FPGA includes two 400 Mhz PowerPC 405 processors. One processor is used to implement management functions as shown in Figure 5. It interfaces to the rest of the management subsystem by way of a 64-bit CoreConnect Processor Local Bus (PLB), and a 32-bit On-Chip Peripheral Bus (OPB). The second PowerPC processor is available for applications specific functions PLB Arbiter The PLB Arbiter implements the CoreConnect Processor Local Bus (PLB). It consists of arbitration logic, a watchdog timer, and separate data path logic for address, write data, and read data DDR SDRAM Memory Controller The Double Data Rate (DDR) SDRAM memory controller manages 128 MB of DRAM for the PowerPC processor, and is used as the main code and data store for the Linux operating system. The memory is implemented using discrete devices soldered to the board BlockRAM (BRAM) Memory Controller The BRAM memory controller manages 32 KB of on-chip SRAM for the PowerPC processor. This memory is used as temporary storage during the boot process PLB2OPB Bridge The PLB2OPB Bridge translates PLB transactions into OPB transactions. These transactions are made up of read and write cycles to IO peripherals OPB Arbiter The OPB Arbiter implements the On-Chip Peripheral Bus (OPB). It consists of arbitration logic, a watchdog timer, and separate data path logic for address, write data, and read data Ethernet MAC The 10/100 Ethernet MAC is used to implement the Shelf Management Controller (ShMC) interface. It interacts with the operating system through a standard network driver, and provides an interface for IP based management traffic. This port can also used for debugging and firmware/hardware updates UART The UART is used to implement the RTM serial port interface. It interacts with the operating system through a standard terminal driver. This port can also used for debugging and firmware/hardware updates System ACE MPU Interface The System ACE MPU Interface provides a mechanism for the 405 processor to access the MicroDrive in the CompactFlash socket. It interacts with the operating system through a standard block device driver, and enables the use of the drive as a file system under Linux I 2 C Interface Controllers The FPGA includes three I 2 C interface controllers. Two are used to implement the IPMB interfaces, and the third is used for system monitoring functions. Avnet Design Services 15 of 18 Rev /15/2004

16 General Purpose IO Controller The General Purpose IO (GPIO) controller gives the processor access to IO pins on the FPGA so that they can be read and written under program control. These signals are used to implement the Hardware Address (HA) interface, and the Front Panel Status Interface Interrupt Controllers The Interrupt Controller blocks manage the interrupt signals fed to the processor by providing masking, and prioritization capabilities. There are two controllers, one for standard interrupts, and one for critical interrupts. The controller manages interrupts from the Ethernet MAC, the I 2 C Controllers, and the UART DCR Bridge The DCR Bridge provides a means for the processor to access control registers that are mapped to the CoreConnect DCR bus. This includes registers in the PLB Arbiter, The OPB2PLB and PLB2OPB bridges, and the Interrupt Controllers. 5.2 Fabric Interface FPGA Data Plane Section The Data Plane Section implements a complete, fifteen channel, distributed switch fabric interface. The configuration shipped with the card implements a PICMG 3.1 Ethernet transport, but it can be customized to support other PICMG 3.x transports. Figure 6 shows a block diagram of the Data Plane section of the Fabric Interface FPGA Figure 6: Fabric Interface FPGA Data Plane Section Block Diagram Aurora Interface Logic The Aurora Interface is used to transfer packets between the user-defined logic on the Prototyping Module and the PICMG 3.x fabric. The Aurora Interface uses the Fabric Interface MGT signals for connectivity. Other interfaces can be substituted for this one if desired. One example of an alternative interface is POS-PHY Level 3. In this case the Fabric Interface GPIO signals would be used for connectivity. Avnet Design Services 16 of 18 Rev /15/2004

17 5.2.2 Channel Interfaces & FIFOs The Channel Interfaces implement physical and link layer functions for each channel. In the case of a PICMG 3.1 Ethernet transport, this block consists of a Gigabit Ethernet MAC with a 1000BASE-BX physical layer interface Address Mapping Logic The address mapping logic maps destination address information contained in packets entering the switch interface through the Aurora Interface into destination port numbers. This information is then used to direct the packet into the transmit FIFO for the correct channel interface. In the PICMG 3.1 configuration that is shipped with the card this means mapping a 48-bit Ethernet destination address. 6 PICMG Synchronization Clock Interface The Full Mesh Line Card supports a subset of the PICMG 3.0 Synchronization Clock Interface functions. The Synchronization Clock Interface logic is capable of selecting and routing the MHz system clock to or from the CLK2A and CLK2B clock busses. Figure 7 shows a block diagram of this logic. The PICMG_REFCLK signals are available to the Personality Module through Fabric Interface GPIO Header 2. Figure 7: Synchronization Clock Interface Logic 7 Power Supply Subsystem The Power Supply Subsystem consists of fusing, filtering, and protection circuitry as well as DC to DC converters designed to support the power requirements of both the Fabric Interface FPGA and application specific circuitry implemented on the Personality Module and Rear Transition Module. Figure 8 gives an overview of this subsystem. 7.1 VCC3V3_BOOT Power Bus The power supply for the baseboard circuitry consists of the Boot DC to DC converter, and several smaller voltage converters that supply the various levels needed by the base board circuitry. 7.2 VCC12V_MAIN Power Bus Power for application specific circuitry consists of 151 watts of 12V brought out to the Personality Module headers, and RTM connector. Conversion to the voltages required by the application is performed on these cards. During card initialization, the VCC12V_MAIN Power Bus is disabled until the control plane subsystem negotiates the power requirements of the board with the shelf management subsystem. It is the responsibility of developers of Personality Modules and RTM cards to ensure the following: Avnet Design Services 17 of 18 Rev /15/2004

18 1. The combined power consumption of the Personality Module and the RTM does not exceed the capabilities of the Main DC to DC converter. 2. Signals connected to the baseboard can tolerate being powered down while the Fabric Interface FPGA is powered up. 3. The capacitors are provided to meet the ATCA power hold time requirement based on the additional current draw of the Personality Module or RTM. Figure 8: Power Supply Subsystem Block Diagram 8 References Virtex-II Pro and Virtex-II Pro X FPGA User Guide, 5 August 2004, Xilinx. PICMG 3.0 Short Form Specification, January 2003, PICMG. Avnet Design Services 18 of 18 Rev /15/2004