Microprocessor Memory Mapping. Dr. Cahit Karakuş, February-2018

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1 Microprocessor Memory Mapping Dr. Cahit Karakuş, February-2018

2 Konu Başlıkları CPU Mimarisi Microprocessor Pins and Signals System Bus Bellek Haritası Bellek Arayüzü ve I/O portları Assemble Adres erişim ve Veri Transfer Komutlar

3 Memory

4 Media Storage Main memory (Electronic Memory): Stores data currently being used Is made of semiconductor chips. Secondary Memory magnetic (floppy discs, hard disc ) Optical (CD-ROM, DVD)

5 Arrangement of Memory Cells Each cell has a unique address Longer strings stored by using consecutive cells value = RAM (random access memory)

6 Accessing Data in the Main Memory Instructions and data are stored in the main memory in a serial order. CPU executes instructions one by one top down. An instruction may tell the CPU to jump to particular cell and execute the instruction held in it, or fetch the data stored is that cell. How is this done?

7 System Bus Main memory and CPU are linked using a set of wire: Three wires: address lines, data lines and control lines. Known as address bus, data bus and control bus. System bus

8 Address Space The address space of a computer is the maximum number of cells a computer can hold. The address space is determined by the number of address lines used in a computer. If each cell in a memory is 8-bit, then the memory is called byte addressable: 1 byte long has a unique address

9 Features of the Main Memory Memory Capacity. Access of information Access time Transfer rate

10 Memory Capacity Most computer s memory have 8-bit (1-byte) cells. In this case we have: Address lines N o of cells Capacity N 2^N 2^N * 1 32KB, 256MB and 20GB are used to describe the memory capacity.

11 Capacity Units 1kB = 2 10 = 1024 Byte. 1MB =1024 KB = 2 20 Bytes= 1, 048,576 B. 1GB =1024 MB = 2 30 kb=1, 073,741,824 Bytes.

12 Access Time Access time is taken between the moment when the CPU wants the read/write from/into a cell and the moment when the cell is activated. It is the moment that the CPU takes to activate a cell. 60ns (10-9 sec)

13 Transfer Rate Is the amount of information per second exchanged between the CPU and main memory. Main memory electronic signals Implies fast transfer rate in the scale about 100MB/sec

14 Random Access If the CPU wants to activate particular cell. It does not search for the target cell from top to bottom. It does put the address of the target cell in the address line, then the cell will be activated. This type of accessing information is called Random Access

15 The need for other type of memories. Main memory Fast as all the exchange between CPU and Main memory is done electronically. However, it is volatile. Information lost when the machine is turned off. The need for non-volatile memory: Hold information when the machine is off. i.e. Magnetic disk, optical disk, magnetic tape

16 A Magnetic Disk Storage System Each track contains same number of sectors Location of tracks and sectors not permanent (formatting) Examples: hard disks, floppy disks,...

17 Magnetic Disk Terminology Platter: rigid metal or glass platter Coated with magnetic material. rotating at constant angular velocity Arm: With movable magnetic read/write heads Track: A complete ring of data The disk surface is divided into tracks Sectors: Each track is subdivided into sectors Cylinder (see slides 71-72): A vertical collection of tracks at the same radial position

18 Main memory RAM Low storage capacity Fast (electrical signals) Volatile. Magnetic memory Floppy disk Hard disk Magnetic tape Optical memory CD_ROM disk DVD Summary

19 MEMORY ORGANIZATION Memory Hierarchy Main Memory Auxiliary Memory Associative Memory Cache Memory Virtual Memory Memory Management Hardware` 19

20 Memory Hierarchy The main memory occupies a central position by being able to communicate directly with the CPU and with auxiliary memory devices through an I/O processor A special very-high-speed memory called cache is used to increase the speed of processing by making current programs and data available to the CPU at a rapid rate 20

21 Memory Hierarchy CPU logic is usually faster than main memory access time, with the result that processing speed is limited primarily by the speed of main memory The cache is used for storing segments of programs currently being executed in the CPU and temporary data frequently needed in the present calculations The typical access time ratio between cache and main memory is about 1to7 Auxiliary memory access time is usually 1000 times that of main memory 21

Memory Main memory consists of a number of storage locations, each of which is identified by a unique address The ability of the CPU to identify each location is known as its addressability Each

22 Memory Main memory consists of a number of storage locations, each of which is identified by a unique address The ability of the CPU to identify each location is known as its addressability Each location stores a word i.e. the number of bits that can be processed by the CPU in a single operation. Word length may be typically 16, 24, 32 or as many as 64 bits. A large word length improves system performance, though may be less efficient on occasions when the full word length is not used 22

23 MEMORY HIERARCHY Memory Hierarchy Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the memory system Auxiliary memory Magnetic tapes Magnetic disks I/O processor CPU Main memory Cache memory Register Cache Main Memory Magnetic Disk Magnetic Tape 23

24 Memory Memory is a place to where the programs and data are loaded in order to be executed. RAM ( Random Access Memory ) and ROM ( Read Only Memory ). RAM is read /write memory while ROMisread-onlymemory; RAM is volatile, (the contents are lost when power is removed ) while ROM is nonvolatile (the contents are not lost when power is removed). Dynamic Ram (DRAM), Static RAM (SRAM), Cache, Read only memory (ROM), Flash Memory,...

25 Random-Access Memory (RAM) Static RAM (SRAM) Each cell stores bit with a six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to disturbances such as electrical noise. Faster and more expensive than DRAM. Dynamic RAM (DRAM) Each cell stores bit with a capacitor and transistor. Value must be refreshed every ms. Sensitive to disturbances. Slower and cheaper than SRAM. 25

26 ROM ROM is used for storing programs that are PERMENTLY resident in the computer and for tables of constants that do not change in value once the production of the computer is completed The ROM portion of main memory is needed for storing an initial program called bootstrap loader, witch is to start the computer software operating when power is turned off 26

27 Main Memory Most of the main memory in a general purpose computer is made up of RAM integrated circuits chips, but a portion of the memory may be constructed with ROM chips RAM Random Access memory In tegated RAM are available in two possible operating modes, Static and Dynamic ROM Read Only memory 27

28 Main Memory A RAM chip is better suited for communication with the CPU if it has one or more control inputs that select the chip when needed The Block diagram of a RAM chip is shown next slide, the capacity of the memory is 128 words of 8 bits (one byte) per word 28

29 RAM 29

30 ROM 30

31 Cache memory If the active portions of the program and data are placed in a fast small memory, the average memory access time can be reduced, Thus reducing the total execution time of the program Such a fast small memory is referred to as cache memory The cache is the fastest component in the memory hierarchy and approaches the speed of CPU component When CPU needs to access memory, the cache is examined If the word is found in the cache, it is read from the fast memory If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the word 31

32 Cache memory The performance of cache memory is frequently measured in terms of a quantity called hit ratio When the CPU refers to memory and finds the word in cache, it is said to produce a hit Otherwise, it is a miss Hit ratio = hit / (hit+miss) The basic characteristic of cache memory is its fast access time, Therefore, very little or no time must be wasted when searching the words in the cache The transformation of data from main memory to cache memory is referred to as a mapping process, there are three types of mapping: Associative mapping Direct mapping Set-associative mapping 32

33 Cache memory To help understand the mapping procedure, we have the following example: 33

34 Memory Mapping

35 Memory, I/O Mapping Primary or Main Memory Storage area which can be directly accessed by microprocessor Store programs and data prior to execution Should not have speed disparity with processor Semi Conductor memories using CMOS technology ROM, EPROM, Static RAM, DRAM Secondary Memory Storage media comprising of slow devices such as magnetic tapes and disks Hold large data files and programs: Operating system, compilers, databases, permanent programs etc. Memory mapping, I/O mapping When memory mapping is used for I/O devices, full memory address space cannot be used for addressing memory.

36 Memory Address Generation The BIU has a dedicated adder for determining physical memory addresses Offset Value (16 bits) Segment Register (16 bits) Adder Physical Address (20 Bits)

37 Intel Example Address Calculation If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data? 2 9 Offset: Segment: Address:

38 Segment:Offset Address Logical Address is specified as segment:offset Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address Thus the physical address of the logical address A4FB:4872 is A4FB A9822

40 The Code Segment 0H CS: 0400H 4000H IP 0056H 4056H CS:IP = 400:56 Logical Address Segment Register Memory Offset Physical or Absolute Address 04056H 0FFFFFH The offset is the distance in bytes from the start of the segment. The offset is given by the IP for the Code Segment. Instructions are always fetched with using the CS register. The physical address is also called the absolute address.

41 The Data Segment 0H DS: 05C0 05C00H SI C50H DS:EA Segment Register 05C0 0 Memory Offset Physical Address 05C50H 0FFFFFH Data is usually fetched with respect to the DS register. The effective address (EA) is the offset. The EA depends on the addressing mode.

42 The Stack Segment 0H SS: 0A00 0A000H SP A100H SS:SP Segment Register 0A00 0 Memory Offset Physical Address 0A100H 0FFFFFH The offset is given by the SP register. The stack is always referenced with respect to the stack segment register. The stack grows toward decreasing memory locations. The SP points to the last or top item on the stack. PUSH - pre-decrement the SP POP - post-increment the SP

43 Memory Address Map Memory Address Map is a pictorial representation of assigned address space for each chip in the system To demonstrate an example, assume that a computer system needs 512 bytes of RAM and 512 bytes of ROM The RAM have 128 byte and need seven address lines, where the ROM have 512 bytes and need 9 address lines 43

44 Memory Address Map 44

45 Memory Address Map The hexadecimal address assigns a range of hexadecimal equivalent address for each chip Line 8 and 9 represent four distinct binary combination to specify which RAM we chose When line 10 is 0, CPU selects a RAM. And when it s 1, it selects the ROM 45

46 Direct Mapping Associative memory is expensive compared to RAM In general case, there are 2^k words in cache memory and 2^n words in main memory (in our case, k=9, n=15) The n bit memory address is divided into two fields: k-bits for the index and n-k bits for the tag field 46

47 Direct Mapping 47

48 Direct Mapping 48

49 UYGULAMA -1 10Mbyte, 6Mbyte, 4 Byte 1. Belleğin başlangıç adresi 0 byte: 0 byte 2. Belleğin başlangıç adresi 10 Mbyte: (2^3+2^1) x 2^20 byte 3. Belleğin başlangıç adresi 16 Mbyte: 2^4 x 2^20 byte Boşluğun başlagıç adresi 20 Byte: (2^4 + 2^2) x 2^20 byte

50 Uygulama-1 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A Mbyte FFFFF 2^23+2^ A Mbyte FFFFFF 2^ Mbyte FFFFF 2^24+2^

51 Interfacing Memory and I/O ports

52 Memory Processor Memory Registers inside a microcomputer Store data and results temporarily No speed disparity Cost Primary or Main Memory Memory Store Programs and Data Storage area which can be directly accessed by microprocessor Store programs and data prior to execution Should not have speed disparity with processor Semi Conductor memories using CMOS technology ROM, EPROM, Static RAM, DRAM Secondary Memory Storage media comprising of slow devices such as magnetic tapes and disks Hold large data files and programs: Operating system, compilers, databases, permanent programs etc. 52

53 Memory organization Memory IC s : Byte oriented 8086 : 16-bit Word : Stored by two consecutive memory locations; for LSB and MSB Address of word : Address of LSB Bank 0 : A 0 = 0 Even addressed memory bank Bank 1 : BHE = 0 Odd addressed memory bank 53

Memory organization Operation BHE A 0 Data Lines Used 1 Read/ Write byte at an even address 1 0 D 7 D 0 2 Read/ Write byte at an odd address 0 1 D 15 D 8 3 Read/ Write word at an even

54 Memory organization Operation BHE A 0 Data Lines Used 1 Read/ Write byte at an even address 1 0 D 7 D 0 2 Read/ Write byte at an odd address 0 1 D 15 D 8 3 Read/ Write word at an even address 0 0 D 15 D 0 4 Read/ Write word at an odd address 0 1 D 15 D 0 in first operation byte from odd bank is transferred 1 0 D 7 D 0 in first operation byte from odd bank is transferred 54

55 Memory organization Available memory space = EPROM + RAM Allot equal address space in odd and even bank for both EPROM and RAM Can be implemented in two IC s (one for even and other for odd) or in multiple IC s 55

56 Interfacing SRAM and EPROM Memory interface Read from and write in to a set of semiconductor memory IC chip EPROM Read operations RAM Read and Write In order to perform read/ write operations, Memory access time read / write time of the processor Chip Select (CS) signal has to be generated Control signals for read / write operations Allot address for each memory location 56

of address in hexa In Decimal In kilo In hexa 20

57 Interfacing SRAM and EPROM Typical Semiconductor IC Chip No of Address pins Memory capacity Range of address in hexa In Decimal In kilo In hexa = 10,48, k = 1M to FFFFF 57

58 Interfacing SRAM and EPROM Memory map EPROM s are mapped at FFFFF H Facilitate automatic execution of monitor programs and creation of interrupt vector table RAM are mapped at the beginning; 00000H is allotted to RAM 58

59 Interfacing SRAM and EPROM Monitor Programs Programing 8279 for keyboard scanning and display refreshing Programming peripheral IC s 8259, 8257, 8255, 8251, 8254 etc Initialization of stack Display a message on display (output) Initializing interrupt vector table Note : 8279 Programmable keyboard/ display controller 8257 DMA controller 8259 Programmable interrupt controller 8255 Programmable peripheral interface 59

Data transfer types Microprocessor Ports / Buffer IC s (interface circuitry) I/ O devices Memory mapped Programmed I/ O Data transfer

60 Interfacing I/O and peripheral devices I/O devices For communication between microprocessor and Keyboards, CRT displays, Printers, Compact Discs outside world etc. Data transfer types Microprocessor Ports / Buffer IC s (interface circuitry) I/ O devices Memory mapped Programmed I/ O Data transfer is accomplished controlled by software through an I/O port I/O mapped Interrupt driven I/ O I/O device interrupts the processor and initiate data transfer Direct memory access Data transfer is achieved by bypassing the microprocessor 60

61 I/O read/write The I/O read and write operations are similar to the memory read and write operations. A processor may use: memory mapped I/O (when the address of the I/O device is in the direct memory space, and the sequence to read/write data in the device are the same with the memory read/write sequence) isolated I/O the process is similar, but the processor has a second set of control signals to make the distinction between a memory access and an I/O access (memory locations and I/O devices can be located at the same address, which makes this extra control signal necessary); for I/O operations, the processor holds IO/M (or similar) signal high for the duration of the I/O operation

62 Assemby Addressing

63 Addressing Modes Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack 63

64 Every instruction of a program has to operate on a data. The different ways in which a source operand is denoted in an instruction are known as addressing modes. 1. Register Addressing 2. Immediate Addressing Group I : Addressing modes for register and immediate data 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing Group II : Addressing modes for memory data 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing 11. Relative Addressing 12. Implied Addressing Group III : Addressing modes for I/O ports Group IV : Relative Addressing mode Group V : Implied Addressing 64 mode

65 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing The instruction will specify the name of the register which holds the data to be operated by the instruction. Example: MOV CL, DH The content of 8-bit register DH is moved to another 8-bit register CL (CL) (DH) 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing 11. Relative Addressing 12. Implied Addressing 65

66 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing In immediate addressing mode, an 8-bit or 16-bit data is specified as part of the instruction Example: MOV DL, 08H The 8-bit data (08 H ) given in the instruction is moved to DL (DL) 08 H MOV AX, 0A9FH The 16-bit data (0A9F H ) given in the instruction is moved to AX register (AX) 0A9F H 11. Relative Addressing 12. Implied Addressing 66

67 Memory Access Offset Value (16 bits) Segment Register (16 bits) Adder Physical Address (20 Bits) 67

68 Memory Access To access memory we use these four registers: BX, SI, DI, BP Combining these registers inside [ ] symbols, we can get different memory locations (Effective Address, EA) Supported combinations: [BX + SI] [BX + DI] [BP + SI] [BP + DI] [SI] [DI] d16 (variable offset only) [BX] [BX + SI + d8] [BX + DI + d8] [BP + SI + d8] [BP + DI + d8] [SI + d8] [DI + d8] [BP + d8] [BX + d8] [BX + SI + d16] [BX + DI + d16] [BP + SI + d16] [BP + DI + d16] [SI + d16] [DI + d16] [BP + d16] [BX + d16] BX BP SI DI + disp 68

69 Memory Access 20 Address lines 8086 can address up to 2 20 = 1M bytes of memory However, the largest register is only 16 bits Physical Address will have to be calculated Physical Address : Actual address of a byte in memory. i.e. the value which goes out onto the address bus. Memory Address represented in the form Seg : Offset (Eg - 89AB:F012) Each time the processor wants to access memory, it takes the contents of a segment register, shifts it one hexadecimal place to the left (same as multiplying by ), then add the required offset to form the 20- bit address 16 bytes of contiguous memory 89AB : F012 89AB 89AB0 (Paragraph to byte 89AB x 10 = 89AB0) F012 0F012 (Offset is already in byte unit) AC2 (The absolute address) 69

70 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing Here, the effective address of the memory location at which the data operand is stored is given in the instruction. The effective address is just a 16-bit number written directly in the instruction. Example: MOV BX, [1354H] MOV BL, [0400H] The square brackets around the 1354 H denotes the contents of the memory location. When executed, this instruction will copy the contents of the memory location into BX register. This addressing mode is called direct because the displacement of the operand from the segment base is specified directly in the instruction. 11. Relative Addressing 12. Implied Addressing 70

71 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing 11. Relative Addressing 12. Implied Addressing In Register indirect addressing, name of the register which holds the effective address (EA) will be specified in the instruction. Registers used to hold EA are any of the following registers: BX, BP, DI and SI. Content of the DS register is used for base address calculation. Example: MOV CX, [BX] Operations: EA = (BX) BA = (DS) x MA = BA + EA (CX) (MA) or, (CL) (MA) (CH) (MA +1) Note : Register/ memory enclosed in brackets refer to content of register/ memory 71

72 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing 11. Relative Addressing 12. Implied Addressing In Based Addressing, BX or BP is used to hold the base value for effective address and a signed 8-bit or unsigned 16-bit displacement will be specified in the instruction. In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base value. When BX holds the base value of EA, 20-bit physical address is calculated from BX and DS. When BP holds the base value of EA, BP and SS is used. Example: MOV AX, [BX + 08H] Operations: 0008 H 08 H (Sign extended) EA = (BX) H BA = (DS) x MA = BA + EA (AX) (MA) or, (AL) (MA) (AH) (MA + 1) 72

73 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing 11. Relative Addressing 12. Implied Addressing SI or DI register is used to hold an index value for memory data and a signed 8-bit or unsigned 16-bit displacement will be specified in the instruction. Displacement is added to the index value in SI or DI register to obtain the EA. In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base value. Example: MOV CX, [SI + 0A2H] Operations: FFA2 H A2 H (Sign extended) EA = (SI) + FFA2 H BA = (DS) x MA = BA + EA (CX) (MA) or, (CL) (MA) (CH) (MA + 1) 73

74 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing 11. Relative Addressing In Based Index Addressing, the effective address is computed from the sum of a base register (BX or BP), an index register (SI or DI) and a displacement. Example: MOV DX, [BX + SI + 0AH] Operations: 000A H 0A H (Sign extended) EA = (BX) + (SI) + 000A H BA = (DS) x MA = BA + EA (DX) (MA) or, (DL) (MA) (DH) (MA + 1) 12. Implied Addressing 74

75 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing 11. Relative Addressing 12. Implied Addressing Note : Effective address of the Extra segment register Employed in string operations to operate on string data. The effective address (EA) of source data is stored in SI register and the EA of destination is stored in DI register. Segment register for calculating base address of source data is DS and that of the destination data is ES Example: MOVS BYTE Operations: Calculation of source memory location: EA = (SI) BA = (DS) x MA = BA + EA Calculation of destination memory location: EA E = (DI) BA E = (ES) x MA E = BA E + EA E (MAE) (MA) If DF = 1, then (SI) (SI) 1 and (DI) = (DI) - 1 If DF = 0, then (SI) (SI) +1 and (DI) = (DI)

76 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing These addressing modes are used to access data from standard I/O mapped devices or ports. In direct port addressing mode, an 8-bit port address is directly specified in the instruction. Example: IN AL, [09H] Operations: PORT addr = 09 H (AL) (PORT) Content of port with address 09 H is moved to AL register In indirect port addressing mode, the instruction will specify the name of the register which holds the port address. In 8086, the 16-bit port address is stored in the DX register. Example: OUT [DX], AX 11. Relative Addressing 12. Implied Addressing Operations: PORT addr = (DX) (PORT) (AX) Content of AX is moved to port by DX register. whose address is specified 76

77 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing 11. Relative Addressing 12. Implied Addressing In this addressing mode, the effective address of a program instruction is specified relative to Instruction Pointer (IP) by an 8-bit signed displacement. Example: JZ 0AH Operations: 000A H 0A H If ZF = 1, then EA = (IP) + 000A H BA = (CS) x MA = BA + EA (sign extend) If ZF = 1, then the program control jumps to new address calculated above. If ZF = 0, then next instruction of the program is executed. 77

78 1. Register Addressing 2. Immediate Addressing 3. Direct Addressing 4. Register Indirect Addressing Instructions using this mode have no operands. The instruction itself will specify the data to be operated by the instruction. Example: CLC This clears the carry flag to zero. 5. Based Addressing 6. Indexed Addressing 7. Based Index Addressing 8. String Addressing 9. Direct I/O port Addressing 10. Indirect I/O port Addressing 11. Relative Addressing 12. Implied Addressing 78

79 Kaynaklar While preparing this document has been based on the document on the following web page; Architecture 8086 Microprocessor, The History of The Microprocessor, Bell Labs Technical Journal, Autumn, rise.cse.iitm.ac.in/people/faculty/kama/prof/x86_1.ppt Microprocessor, Atul P. Godse, Deepali A. Gode, Technical publications, Chap 11

Intel 8086 MICROPROCESSOR ARCHITECTURE

Intel 8086 MICROPROCESSOR ARCHITECTURE 1 Features It is a 16-bit μp. 8086 has a 20 bit address bus can access up to 2 20 memory locations (1 MB). It can support up to 64K I/O ports. It provides 14, 16