High-Speed SDR SDRAM Controller Core for Actel FPGAs. Introduction. Features. Product Brief Version 1.0 November 2002

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1 Introduction Complementing the high-speed communication solutions from MorethanIP, the High- Speed SDRAM Controller offers storage extension for memory critical applications. For example with packet-based traffic as in IP networks, storage requirements can become crucial when complete frames need to be stored (e.g. 9Kb Ethernet Jumbo Frames). The Controller implements a burst optimized access scheme, which offers transfer rates up to 4 Gbit/s at 125MHz. All SDRAM device specifics, like row and column multiplexing, page burst handling, page and bank switching are completely hidden from the user application. Power-up initialization, refresh and other management tasks necessary to provide data integrity in the SDRAM are done automatically and also hidden from the user application. The Controller interfaces directly to SDRAM memory devices and provides a simple and easy-to-use split-port user interface (separate read and write ports). It allows for single word accesses as well as arbitrary length bursts emulating a linear memory space with no page or bank boundaries. The SDRAM Controller can easily be connected to other MorethanIP solutions or used as backend for large FIFO applications. Features Interfaces directly to SDRAM memory devices at speeds up to 166MHz or above Programmable timing parameters to adapt for different memory and application speeds 32-bit SDRAM data bus layout, single data rate 32-bit split-port user application interface with simple two signal handshake Single word accesses and arbitrary length burst transfers SDRAM page and bank boundary crossing and burst mode handling completely hidden from the user Automatic and hidden refresh Automatic memory setup and initialization after power up Implementation verified with Micron MT48LC2M32B2 64Mbit (2Mx32) SDRAM Scripts for Synthesis and Simulation (Exemplar, Synplicity, Modelsim) tools provided Delivered in VHDL source code for easy integration and with a platform independent JAVA configuration utility Complete test environment with Micron Vendor model for MT48LC2M32B2 64Mbit SDRAM 1

2 Block Diagram SDRAM SDRAM-Controller SDRAM I/O CONTROL Bank Count ROW & COL Count Page Count State Machine Refresh Counter Power-Up Initialization Address Port Write Port Read Port Addr Ctl Data Ctl Data Ctl Figure 1: Block Diagram Application Overview SDRAM 125MHz High-Speed SDRAM Controller Addr Port Write Port Read Port User Application FPGA Other Figure 2: Application Example 2

3 Memory Device Support Table 1: SDRAM Memory Support Type Layout Speed, CAS Latency 64 Mbit, 2Mx32 MT48LC2M32B2 512 x 32 x 4-8: 125 MHz, CL 3 64 Mbit, 2Mx32 MT48LC2M32B2 512 x 32 x 4-7: 143 MHz, CL 3 64 Mbit, 2Mx32 MT48LC2M32B2 512 x 32 x 4-6: 166 MHz, CL Mbit, 4Mx32 MT48LC4M32B x 32 x 4-7: 143 MHz, CL Mbit, 4Mx32 MT48LC4M32B x 32 x 4-6: 166 MHz, CL 3 Other Memory and Speed combinations available on request Implementation Summary Table 2: Implementation Summary - Axcelerator Axcelerator Device Speed Grade C-Cells R-Cells Complexity Total Utilization RAM Performance AX (5%) 300 (11%) 8% - 195MHz Table 3: Implementation Summary - ProASICplus ProASICplus Device Speed Grade Cells (Total Utilization) Complexity RAM Performance APA300 std 660 (8%) - 74MHz 3

4 Design Kit Overview Table 4: Design Database Overview Design and Simulation Language VHDL / Verilog or netlist for Actel FPGA implementation. Simulation Verification Configurable VHDL Testbench with embedded frame generator and checker, providing an easy to use and robust debugging environment. Comprehensive test environment with Ethernet frame generator and verification models for standard compliant and errored frame generation and automated core behavior verification. Design Tools Simulation Modelsim Version 5.4d or higher Synthesis Implementation Exemplar Leonardo Spectrum 2002c or higher Synplicity Synplify 7.1 or higher Actel Libero IDE (Integrated Design Environment) V2.2 or higher, or Actel Designer R or higher. References Micron SDRAM MT48LC2M32B2, MT48LC4M32B2 4

5 Ordering Code MTIP-SDR_CNTRL-lang-arch Language code Technology code Table 5: Language Code Technology Code BIN VHDL VLOG Table 6: Technology Code Technology Code Target Technology Binary netlist for Actel Axcelerator or ProASICplus FPGAs. Synthesizable generic VHDL source code for Actel Axcelerator or ProASICplus FPGAs or ASIC implementations Synthesizable generic Verilog source code for Actel Axcelerator or ProASICplus FPGAs or ASIC implementations Target Technology GEN Source code option for Actel Axcelerator or ProASICplus FPGAs or ASIC implementations. ACTL Netlist for Actel Axcelerator or ProASICplus FPGAs. 5

6 Contact MorethanIP info@morethanip.com Internet : Europe An der Steinernen Bruecke 1 D Karlsfeld Germany Tel : +49 (0) FAX : +49 (0) North America 2130 Gold Street Ste. 250 Alviso, CA USA Tel : Fax :