ESL design with the Agility Compiler for SystemC

Transcription

1 ESL design with the Agility Compiler for SystemC SystemC behavioral design & synthesis Steve Chappell & Chris Sullivan

2 Celoxica ESL design portfolio Complete ESL design environment Streaming Video Processing Library Algorithm to custom IP component design tool SystemC behavioral design and synthesis Hardware/ software co-design & processor integration Board level integration High performance prototyping & development boards 2

3 Agility Compiler for SystemC SystemC behavioral design and synthesis

4 Agility Compiler SystemC behavioral design and synthesis Bridges the gap between TLM and design implementation Built on Celoxica s 3 rd generation C synthesis technology Only solution that automatically generates IEEE compliant RT level VHDL & Verilog and directly programs FPGA Optimum balance between design automation and designer control 4

5 Agility Compiler overview features SystemC standard compliant using 3 rd generation C-synthesis technology Supports the SystemC synthesizable subset Pure SystemC Extended behavioral synthesis support available Available through agreement RT Level VHDL and Verilog VHDL IEEE compliant Verilog IEEE compliant Actel, Altera, Xilinx FPGA support Including Stratix II and Virtex 4 Optional re-timing synthesis Structural SystemC netlist output for verification 5

6 Agility Compiler GUI Simulation Build Build Targets File/Symbol view Mixed Projects C/C++/SystemC/Handel-C RTL/EDIF Blackbox Info Syntax highlighting 6

7 Synthesizable SystemC (SSC) SSC is: The Minimum subset of SystemC syntactic elements that should be supported by SystemC standard compliant synthesis tools Defined within the SystemC 2.0 and C++ specification Covers Register Transfer and Behavioral Level SystemC syntax Coding guidelines for implementation 7

8 Concurrent Processes in SystemC SC_MODULE (my_module) { sc_in<bool> clk, rst; sc_in<int> in; sc_out<int> out; int temp, result; clk rst my_method } }; void my_method(); void my_thread(); void my_cthread(); SC_CTOR(my_module) { SC_METHOD(my_method); sensitive << in << rst; SC_THREAD(my_thread); sensitive << clk.pos(); SC_CTHREAD(my_cthread, clk.pos()); watching(rst.delayed()==true); in temp my_module my_thread my_cthread result # define SC_MODULE (name) \ struct name: public sc_module out 8

9 SystemC Multiplier Template template<int W1, W2> inline void Multiply(sc_int<W1> &LHS, sc_int<w2> &RHS, sc_int<w1+w2> &Result) { sc_uint<w2> i, RHSCopy; sc_uint<w1+w2> LHSCopy, temp; LHSCopy = LHS; RHSCopy = RHS; temp = 0; i = 0; wait(); //clock cycle boundary while( i < W2) { sc_int<w1+w2> Mask; Mask = RHSCopy.range(0,0); // sign extended to full width if( i == W2-1) temp = temp (LHSCopy & Mask); else temp = temp + (LHSCopy & Mask); LHSCopy = LHSCopy << 1; //shift left RHSCopy = RHSCopy >> 1; //shift right i++; Concurrency: Explicit Timing: Explicit Clocks Types: C++ }; 9 } Result = temp; wait(); //clock cycle boundary Sequential

10 Compiler Loop Unrolling template<int W1, W2> inline void Multiply(sc_int<W1> &LHS, sc_int<w2> &RHS, sc_int<w1+w2> &Result) { sc_uint<w2> i, RHSCopy; sc_uint<w1+w2> LHSCopy, temp; LHSCopy = LHS; RHSCopy = RHS; temp = 0; i = 0; wait(); //clock cycle boundary while( i < W2) { sc_int<w1+w2> Mask; Mask = RHSCopy.range(0,0); // sign extended to full width if( i == W2-1) temp = temp (LHSCopy & Mask); else temp = temp + (LHSCopy & Mask); LHSCopy = LHSCopy << 1; //shift left RHSCopy = RHSCopy >> 1; //shift right i++; }; 10 Result = temp; // wait(); //clock cycle boundary REMOVED } Combinational

11 Refined Implementation template<int W1, W2> inline void Multiply(sc_int<W1> &LHS, sc_int<w2> &RHS, sc_int<w1+w2> &Result) { sc_uint<w2> i; sc_signal< sc_uint<w2> > RHSCopy[W2]; sc_signal< sc_uint<w1+w2> > LHSCopy[W2], temp[w2]; i = 0; while ( true ) { i = 1; RHSCopy[0] = RHS; LHSCopy[0] = LHS; while( i < W2) { sc_int<w1+w2> Mask; Mask = RHSCopy[i].range(0,0); // sign extended to full width if( i == W2-1) temp[i] = temp[i-1] - (LHSCopy[i] & Mask); else temp[i] = temp[i-1] + (LHSCopy[i] & Mask); }; 11 } LHSCopy[i] = LHSCopy[i-1] << 1; //shift left RHSCopy[i] = RHSCopy[i-1] >> 1; //shift right i++; } Result = temp[w2-1]; wait(); //clock cycle boundary Pipelined

12 Verification Agility Compiler top-level design flow SSC Verification Timed Functional Bus Cycle Accurate Clock Cycle Accurate Register Transfer Level 12

13 Synthesis for modeling and verification using the Agility Compiler

14 Transaction Level Modeling (TLM) Basis of contemporary System Level Design techniques No common standard yet! OSCI working group defining precise definition of TLM for SystemC Underlying concepts Describe HW and SW together (with enough detail) Separate functional units from communication Abstract Interfaces Emphasis on functionality of data transfers rather than implementation TLM may be untimed, timed or bus-cycle accurate Applications Architecture and algorithm exploration Functional/Platform modeling Testbenches and fast simulations Transaction based verification 14

15 Bridging the gap between TLM & silicon using the Agility Compiler Algorithmic Simulation Speed Accuracy & Synthesis Transaction Level Models Untimed Functional Timed Functional Bus Cycle Accurate Clock Cycle Accurate Register Transfer Level Hand Refinement Agility Compiler Behavioral synthesis Gate Level RTL Synthesis FPGA 15

16 Verification Agility Compiler SystemC modeling, verification & flow using FPGA prototyping ConvergenSC Verification Verification loop Hardware in-the-loop INCISIVE NC-SystemC OSCI reference simulator 16

17 Agility Compiler rapid prototyping kit for modeling and verification Design software, tools and libraries for SystemC modeling, verification and synthesis Direct to FPGA or ASIC/ SoC prototyping & emulation Xilinx Virtex II FPGA XC2V device OSCI Prototyping and development of very high performance/ high throughput SystemC applications Memory Large memory (32Mb SRAM + DIMM socket for DRAM) Communications Gigabit Ethernet MAC/PHYs 10/100/1000baseT sockets Dual video sub-system -2 * Composite video in -2 * S-Video in/out -2 * VGA out -2 * DVI in/out 12.1 TFT/Touch screen USB 2.0 connection AC97 compatible audio 17

18 Why are we doing this?

19 Japan Market Feedback to OSCI 2004 Synthesis is THE dominant issue 19

20 Demo

21 RC203 COTS prototyping/ development board Major Functionality: Specifically designed for understanding and evaluating the benefits of C-based design and synthesis using Programmable Logic and soft-core processors/ Includes all necessary libraries & drivers for board level integration Xilinx Virtex II FPGA XC2V device Memory 2 * 2Mbytes ZBT SRAM 2 * 4Mbytes ZBT SRAM option Video sub-system Composite video in/out S-Video in/out VGA out Camera In Ethernet 10/100 MAC/PHY AC97 compatible audio Bluetooth 21

22 About Celoxica & conclusion

23 Celoxica s expertise Design tools, IP & services for ESL design System/ algorithm acceleration Co-design partitioning Co-simulation & co-verification (C/ C++/ SystemC/ Handel-C/ Matlab/ HDL) SystemC behavioral synthesis to IEEE compliant RTL VHDL & Verilog and FPGA EDIF Built on 3 rd generation C synthesis technology, proven in customer flows LUT based FPGA ALU & heterogeneous based reconfigurable architectures Custom ASIC & SoC Member of the SystemC synthesis Working Group Proven delivery of C-based design & synthesis tools to the market 23

24 Working with world class solutions Reconfigurable Semiconductors Design Environments 24

25 Conclusion Complete ESL design environment The most comprehensive range of proven Streaming Video ESL Processing design solutions Library Agility Compiler behavioral SystemC Algorithm to custom synthesis IP component design tool Built on proven, 3 rd generation technology Behavioral design and synthesis for SystemC Synthesis for modeling & verification Hardware/ software Rapid prototyping co-design && processor emulation integration kit TLM to foundry production Board level integration IEEE compliant RT Level VHDL & Verilog Actel, Altera, Xilinx FPGA support including High performance prototyping & development boards Stratix II and Virtex 4 25

26 Thank you For more info. www celoxica.com 26