IO Aggregation/De-Aggregation in Mobile & Mobile Influenced Systems to Improve Routing Congestion MIPI Alliance, Inc.

Transcription

1 Ying Chen Abdullah Raouf IO Aggregation/De-Aggregation in Mobile & Mobile Influenced Systems to Improve Routing Congestion

2 Agenda Mobile & mobile-influenced system evolution Low-speed I/O proliferation and standardization efforts System-level challenges Bus topologies (I 2 C, SPI, -I3C, -VGI, etc.) Routing congestions Reducing wires Aggregation / De-aggregation Summary 2

3 Mobile-Influenced: Multiple Modules Multiple Control Busses and s Low Speed Communications SPI SPI PDM PDM I2C UART Sound Wire RFFE s DSI/CSI Pogo Pins DSI/CSI RFFE s Sound Wire I2C UART I3C I2S Congested Inter-Modular Connectivity I2S I3C 3

4 VGI SM : Consolidation Modem Wireless LAN Bluetooth Gigabit Wireless LAN (60-GHz) Wireless LAN Gigabit Wireless LAN Modem WWAN WiFi/BT 60-GHz Bluetooth (60-GHz) PCIe/M-PCIe/ HSIC/USB CLKREQ WAKEUP RESET STATUS ERR CHNL_RDY s: x9 PCIe/M-PCIe/ HSIC/USB CLKREQ WAKEUP RESET EN P_DN s: x5 PCIe/M-PCIe/ HSIC/USB CLKREQ WAKEUP RESET EN P_DN s: x5 SDIO/HSIC/USB/ PCIe/M-PCIe/ HSIC/USB PCIe VGI I/O Lines x2 SDIO/HSIC/USB/ PCIe/M-PCIe/ HSIC/USB PCIe VGI I/O Lines x2 PCIe/M-PCIe/ HSIC/USB VGI I/O Lines x2 Applications Processor (SoC) Applications Processor (SoC) CHG_LED_R CHG_LED_G CHG_LED_B WiFi_ON BT_ON MEM_ACCESS s: x6 PWR_ON VOL_UP VOL_DN HOME BACK LOCK MUTE LID s: x8 PCIe/M-PCIe/ HSIC/USB CLKREQ WAKEUP RESET EN P_ON INT1 INT2 INT3 s: x8 VGI I/O Lines x2 VGI I/O Expander PCIe/M-PCIe/ HSIC/USB VGI I/O Lines x2 Optional Connector Companion / Bridge-Chip Ethernet CHG_LED_R CHG_LED_G CHG_LED_B WiFi_ON BT_ON MEM_ACCESS PWR_ON VOL_UP VOL_DN HOME BACK LOCK MUTE LID Companion High-Speed / Bridge-Chip Hub Ethernet Optional Connector But, over time, it will add yet another bus to the mix 4

5 Agenda Mobile & mobile-influenced system evolution Low-speed I/O proliferation and standardization efforts System-level challenges Bus topologies (I 2 C, SPI, -I3C, -VGI, etc.) Routing congestions Reducing wires Aggregation / De-aggregation Summary 5

6 Challenge: Different Protocols and Bandwidths SPI 4 pin IF 10+ Mbps CSI2 CCI I2C like PDM 2 pin IF I2C 2 pin 400KHz 2 pin 100KHz 2 pin 1000KHz I3C 2 pin 12.5MHz SoundWire 2 pin IF UART 2 pin IF Various I2S 2 pin IF 6

7 System Architecture Trends: Routing Limitations POGO Pin architecture FlexPCB architecture Module A Module B Board A 1-2 layer Board B 7

8 Issues Identified SOCs are minimizing the number of direct signal connections PCBs are becoming smaller which adds to routing complexity Signals need to be pre-conditioned prior to reaching the SOC Localized or pre-processing demands are increasing 8

9 Agenda Mobile & mobile-influenced system evolution Low-speed I/O proliferation and standardization efforts System-level challenges Bus topologies (I 2 C, SPI, -I3C, -VGI, etc.) Routing congestions Reducing wires Aggregation / De-aggregation Summary 9

10 Signal Aggregation / De-Aggregation SPMI SoundWire SPI SoundWireXL I2C UART DSI Low power Low cost Small size FPGA #1 SLVS CSI-2 I3C I2S PDM RFFE SlimBus SMBus/PMBus SPMI SoundWire SPI SoundWireXL I2C UART DSI Low power Low cost Small size FPGA #2 SLVS CSI-2 I3C I2S PDM RFFE SlimBus SMBus/PMBus Module or Board A POGO Pins Or Flex Cable Module or Board B 10

11 Signal Aggregation / De-Aggregation SPMI SoundWire SPI SoundWireXL I2C UART DSI Low power Low cost Small size FPGA #1 SLVS CSI-2 I3C I2S PDM RFFE SlimBus SMBus/PMBus ~1-5 mw ~2x2 mm2 SPMI SoundWire SPI SoundWireXL I2C UART DSI Low power Low cost Small size FPGA #2 SLVS CSI-2 I3C I2S PDM RFFE SlimBus SMBus/PMBus Module or Board A POGO Pins Or Flex Cable Module or Board B 11

12 How Does Aggregation in an FPGA Work? 1 MHz UART 3 Mbps PDM 24 MHz SPI 50 Mbps Serialized Envelope 1 MHz UART 3 Mbps PDM 24 MHz SPI 1 MHz UART 3 Mbps PDM 24 MHz SPI Time Division Multiplexing Multiple Packets 12

13 How Does Aggregation in an FPGA Work? Packetized data across serialized interface 1 MHz UART 3 Mbps PDM 24 MHz SPI Serialized CDR interface for easier board routing Signals transmitted via a packet-based structure Improved data integrity (CRC, FEC, etc.), 8b/10b enc Transmitted using a clock tolerance compensation (CTC) Allows difference in reference clocks on each end Buffered / conditioned prior to reaching SOC Pre-processed for always-on capability Bridged to an interface the SOC can understand (i.e., SPI, I3C) 1 MHz UART 3 Mbps PDM 24 MHz SPI 13

14 Resources Used Block CDR Encoding RX Protocol Logic TX Protocol Logic interface I2C Local Slave interface I2S interface Other TOTAL TX Device Gates* Registers RAMs 3, , , , , K 1.4K 4 RX Device Gates* Registers RAMs 3, , , , , K 1.4K 4 * For ASIC gates ~= 10 x # of LUTs used. One RAM = 4Kb. One PLL also used. This has been implemented in a pair of 2K LUT FPGAs. 14

15 Summary Trend towards modular systems Notebooks, phones, drones, automotive, etc. Systems have a fair amount of low-speed signals Control busses, s, LEDs, etc. Routing congestions Signal aggregation/de-aggregation improves industrial design Reduces connections Low power, small size FPGAs offer custom implementations 15

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